U70F3035AY

UPD703034A RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 2.1 Port Pins
• 2.2 Non-Port Pins
• 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
• 3.1 Flash Memory Programming Mode ( µµµµPD70F3035A, 70F3035AY only)

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µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY V850/SB2 TM 32-BIT SINGLE-CHIP MICROCONTROLLERS Document No. U14780EJ2V1DS00 (2nd edition) Date Published December 2001 N CP(K) Printed in Japan DATA SHEET © 2000 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

DESCRIPTION

The µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY (V850/SB2) are 32-bit single- chip microcontrollers of the V850 Family TM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter, DMA controller, and so on are integrated on a single chip. The µPD70F3035A and 70F3035AY have flash memory in place of the internal mask ROM of the µPD703035A and 703035AY. Because flash memory allows the program to be written and erased electrically with the device mounted on the board, these products are ideal for the evaluation stages of system development, small-scale production, and rapid development of new products. The µPD703037A, 703037AY, 70F3037A, 70F3037AY, products with a different ROM/RAM size are also available. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. V850/SB1 TM , V850/SB2 User’s Manual Hardware: U13850E V850 Family User’s Manual Architecture: U10243E

FEATURES

{ Number of instructions: 74 { Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation) { General-purpose registers: 32 bits × 32 registers { Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { Memory space: 16 MB linear address space { Internal memory ROM: 128 KB ( µPD703034A, 703034AY: mask ROM)

256 KB (µPD703035A, 703035AY: mask ROM)

256 KB (µPD70F3035A, 70F3035AY: flash memory)

RAM: 12 KB (µPD703034A, 703034AY)

16 KB (µPD703035A, 703035AY, 70F3035A, 70F3035AY)

{ Interrupt/exception: µPD703034A, 703035A, 70F3035A (external: 8, internal: 33 sources, exception: 1 source) µPD703034AY, 703035AY, 70F3035AY (external: 8, internal: 34 sources, exception: 1 source) { I/O lines Total: 83 { Timer/counters: 16-bit timer (2 channels: TM0, TM1) 8-bit timer (6 channels: TM2 to TM7) { Watch timer: 1 channel { Watchdog timer: 1 channel { IEBus TM controller: 1 channel

µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY { Serial interface

• Asynchronous serial interface (UART0, UART1)
• Clocked serial interface (CSI0 to CSI3)
• 3-wire variable length serial interface (CSI4)
• I C bus interface (I C0, I C1) (µPD703034AY, 703035AY, 70F3035AY only) { 10-bit resolution A/D converter: 12 channels { DMA controller: 6 channels { Real-time output port: 8 bits × 1 channel or 4 bits × 2 channels { ROM correction: 4 places can be corrected { Power-saving function: HALT/IDLE/STOP modes { Packages: 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic QFP (14 × 20) { µPD70F3035A, 70F3035AY
• Can be replaced with µPD703035A and 703035AY (internal mask ROM) in mass production

APPLICATIONS

{ AV equipment (audio, car audio, VCR, TV, etc.)

ORDERING INFORMATION

Part Number Package Internal ROM µPD70F3035AGC-8EU µPD70F3035AYGC-8EU µPD70F3035AGF-3BA µPD70F3035AYGF-3BA 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic QFP (14 × 20) 100-pin plastic QFP (14 × 20) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic QFP (14 × 20) 100-pin plastic QFP (14 × 20) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic QFP (14 × 20) 100-pin plastic QFP (14 × 20) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Remarks 1. ××× indicates ROM code suffix. 2. ROMless versions are not provided.

Data Sheet U14780EJ2V1DS 3 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY PIN CONFIGURATION (Top View) 100-pin plastic LQFP (fine pitch) (14 ×××× 14)

• µPD703034AGC-×××-8EU • µPD70F3035AGC-8EU
• µPD703034AYGC-×××-8EU • µPD70F3035AYGC-8EU
• µPD703035AGC-×××-8EU
• µPD703035AYGC-×××-8EU P21/SO2 P22/SCK2/SCL1 Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/V PPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11 P71/ANI1 P70/ANI0 AV REF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BV SS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P107/RTP7/KR7/A12 P110/WAIT/A1 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC V SS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P20/SI2/SDA1 Note 2 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 P12/SCK0/SCL0 Note 2 P11/SO0 P10/SI0/SDA0 Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 100 Notes 1. IC: Connect directly to VSS (µPD703034A, 703034AY, 703035A, 703035AY). VPP: Connect to VSS in normal operation mode (µPD70F3035A, 70F3035AY). 2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703034AY, 703035AY, and 70F3035AY.

µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 100-pin plastic QFP (14 ×××× 20)

• µPD703034AGF-×××-3BA • µPD70F3035AGF-3BA
• µPD703034AYGF-×××-3BA • µPD70F3035AYGF-3BA
• µPD703035AGF-×××-3BA
• µPD703035AYGF-×××-3BA P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0 Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 100 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC V SS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AV REF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BV SS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1 Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/V PPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1 Notes 1. IC: Connect directly to VSS (µPD703034A, 703034AY, 703035A, 703035AY). VPP: Connect to VSS in normal operation mode (µPD70F3035A, 70F3035AY). 2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703034AY, 703035AY, and 70F3035AY.

Data Sheet U14780EJ2V1DS 5 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY PIN IDENTIFICATION A1 to A21: Address Bus P70 to P77: Port 7 AD0 to AD15: Address/Data Bus P80 to P83: Port 8 ADTRG: AD Trigger Input P90 to P96: Port 9 ANI0 to ANI11: Analog Input P100 to P107: Port 10 ASCK0, ASCK1: Asynchronous Serial Clock P110 to P113: Port 11 ASTB: Address Strobe RD: Read AV DD: Analog Power Supply REGC: Regulator Clock AVREF: Analog Reference Voltage RESET: Reset AVSS: Analog Ground RTP0 to RTP7: Real-time Output Port BVDD: Power Supply for Bus Interface RTPTRG: RTP Trigger Input BVSS: Ground for Bus Interface R/W: Read/Write Status CLKOUT: Clock Output RXD0, RXD1: Receive Data DSTB: Data Strobe SCK0 to SCK4: Serial Clock EV DD: Power Supply for Port SCL0, SCL1: Serial Clock EVSS: Ground for Port SDA0, SDA1: Serial Data HLDAK: Hold Acknowledge SI0 to SI4: Serial Input HLDRQ: Hold Request SO0 to SO4: Serial Output IC: Internally Connected TI00, TI01, TI10, : Timer I nput IERX: IEBus Receive Data TI11, TI2 to TI5 IETX: IEBus Transmit Data TO0 to TO5: Timer Output INTP0 to INTP6: Interrupt Request from Peripherals TXD0, TXD1: Transmit Data KR0 to KR7: Key Return UBEN: Upper Byte Enable LBEN: Lower Byte Enable V DD: Power Supply NMI: Non-Maskable Interrupt Request V PP: Programming Power Supply P00 to P07: Port 0 V SS: Ground P10 to P15: Port 1 WAIT: Wait P20 to P27: Port 2 WRH: Write Strobe High Level Data P30 to P37: Port 3 WRL: Write Strobe Low Level Data P40 to P47: Port 4 X1, X2: Crystal for Main Clock P50 to P57: Port 5 XT1, XT2: Crystal for Sub-clock P60 to P65: Port 6

µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY INTERNAL BLOCK DIAGRAM ROM CPU PC ROM correction HLDRQ (P96) HLDAK (P95) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) A1 to A12 (P100 to P107, P110 to P113) AD0 to AD15 (P40 to P47, P50 to P57) CLKOUT XT1 XT2 RESET V DD VSS BVDD BVSS EVDD EVSS VPPNote 4 ICNote 5 RTP0 to RTP7 RTPTRGREGC AVDD AVREF AVSS ANI0 to ANI11 ADTRG P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 ASTB (P94) DSTB/RD (P93) R/W/WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) Multiplier 16 × 16 → 32 32-bit barrel shifter System registers General-purpose registers 32 bits × 32 Note 1 Note 2 RAM INTC SIO CSI0/I2C0Note 3 CSI2/I2C1Note 3 CSI1/UART0 CSI3/UART1 Variable length CSI4 Key return function DMAC: 6ch SO0 SI0/SDA0Note 3 SCK0/SCL0Note 3 Watch timer Watchdog timer NMI INTP0 to INTP6 TI00, TI01, TI10, TI11 TO0, TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5 SO2 SI2/SDA1Note 3 SCK2/SCL1Note 3 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7 ALU Ports RTP CG

3.0 V Regulator

: TM0, TM1 8-bit timer : TM2 to TM7 IEBusIETX IERX Notes 1. µPD703034A, 703034AY: 128 KB (mask ROM) µPD703035A, 703035AY: 256 KB (mask ROM) µPD70F3035A, 70F3035AY: 256 KB (flash memory) 2. µPD703034A, 703034AY: 12 KB µPD703035A, 703035AY, 70F3035A, 70F3035AY: 16 KB 3. I C bus interface and SDAn and SCLn pins (n = 0, 1) are available only in the µPD703034AY, 703035AY, and 70F3035AY. 4. µPD70F3035A, 70F3035AY 5. µPD703034A, 703034AY, 703035A, 703035AY

µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 1. DIFFERENCES AMONG PRODUCTS ROMProduct Name Incorporated I C Type Size RAM Size Flash Memory Programming Pin Package µPD703034A No µPD703034AY Yes Mask ROM 128 KB 12 KB No 100-pin QFP (14 × 20) 100-pin LQFP (14 × 14) µPD703035A No µPD703035AY Yes Mask ROM 256 KB 16 KB No µPD70F3035A No µPD70F3035AY Yes Flash memory Yes (V PP) 100-pin QFP (14 × 20) 100-pin LQFP (14 × 14) µPD703037A No µPD703037AY Yes Mask ROM 512 KB 24 KB No µPD70F3037A No µPD70F3037AY Yes Flash memory Yes (V PP) 100-pin QFP (14 × 20) Cautions 1. There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. 2. When replacing the flash memory versions with mask ROM versions, write the same code in the empty area of the internal ROM.

Data Sheet U14780EJ2V1DS 9 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 2. PIN FUNCTIONS

2.1 Port Pins

(1/2) Pin Name I/O PULL Function Alternate Function P00 NMI P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4/ADTRG P06 INTP5/RTPTRG P07 I/O Yes Port 0 8-bit I/O port Input/output can be specified in 1-bit units. INTP6 P10 SI0/SDA0 Note P11 SO0 P12 SCK0/SCL0 Note P13 SI1/RXD0 P14 SO1/TXD0 P15 I/O Yes Port 1 6-bit I/O port Input/output can be specified in 1-bit units. SCK1/ASCK0 P20 SI2/SDA1 Note P21 SO2 P22 SCK2/SCL1 Note P23 SI3/RXD1 P24 SO3/TXD1 P25 SCK3/ASCK1 P26 TI2/TO2 P27 I/O Yes Port 2 8-bit I/O port Input/output can be specified in 1-bit units. TI3/TO3 P30 TI00 P31 TI01 P32 TI10/SI4 P33 TI11/SO4 P34 TO0/A13/SCK4 P35 TO1/A14 P36 TI4/TO4/A15 P37 I/O Yes Port 3 8-bit I/O port Input/output can be specified in 1-bit units. TI5/TO5 P40 to P47 I/O No Port 4 8-bit I/O port Input/output can be specified in 1-bit units. AD0 to AD7 P50 to P57 I/O No Port 5 8-bit I/O port Input/output can be specified in 1-bit units. AD8 to AD15 Note µPD703034AY, 703035AY, 70F3035AY only. Remark PULL: On-chip pull-up resistor

Data Sheet U14780EJ2V1DS10 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (2/2) Pin Name I/O PULL Function Alternate Function P60 to P65 I/O No Port 6 6-bit I/O port Input/output can be specified in 1-bit units. A16 to A21 P70 to P77 Input No Port 7 8-bit input port ANI0 to ANI7 P80 to P83 Input No Port 8 4-bit input port ANI8 to ANI11 P90 LBEN/WRL P91 UBEN P92 R/W/WRH P93 DSTB/RD P94 ASTB P95 HLDAK P96 I/O No Port 9 7-bit I/O port Input/output can be specified in 1-bit units. HLDRQ P100 RTP0/A5/KR0 P101 RTP1/A6/KR1 P102 RTP2/A7/KR2 P103 RTP3/A8/KR3 P104 RTP4/A9/KR4/IERX P105 RTP5/A10/KR5/IETX P106 RTP6/A11/KR6 P107 I/O Yes Port 10 8-bit I/O port Input/output can be specified in 1-bit units. RTP7/A12/KR7 P110 A1/WAIT P111 A2 P112 A3 P113 I/O Yes Port 11 4-bit I/O port Input/output can be specified in 1-bit units. Remark PULL: On-chip pull-up resistor

Data Sheet U14780EJ2V1DS 11 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY

2.2 Non-Port Pins

(1/4) Pin Name I/O PULL Function Alternate Function A1 P110/WAIT A2 P111 A3 P112 A4 P113 A5 P100/RTP0/KR0 A6 P101/RTP1/KR1 A7 P102/RTP2/KR2 A8 P103/RTP3/KR3 A9 P104/RTP4/KR4/IERX A10 P105/RTP5/KR5/IETX A11 P106/RTP6/KR6 A12 P107/RTP7/KR7 A13 P34/TO0/SCK4 A14 P35/TO1 A15 Output Yes Lower address bus used for external memory expansion P36/TO4/TI4 A16 to A21 Output No Higher address bus used for external memory expansion P60 to P65 AD0 to AD7 P40 to P47 AD8 to AD15 I/O No 16-bit multiplexed address/data bus used for external memory expansion P50 to P57 ADTRG Input Yes A/D converter external trigger input P05/INTP4 ANI0 to ANI7 P70 to P77 ANI8 to ANI11 Input No Analog input to A/D converter P80 to P83 ASCK0 Baud rate clock input for UART0 P15/SCK1 ASCK1 Input Yes Baud rate clock input for UART1 P25/SCK3 ASTB Output No External address strobe output P94 AVDD −− Positive power supply for A/D converter and alternate port − AVREF Input − Reference voltage input for A/D converter − AVSS −− Ground potential for A/D converter and alternate port − BVDD −− Positive power supply for bus interface and alternate port − BVSS −− Ground potential for bus interface and alternate port − CLKOUT Output − Internal system clock output − DSTB Output No External data strobe output P93/RD EVDD −− Positive power supply for I/O ports and alternate-function pins (except bus interface alternate port) EVSS −− Ground potential for I/O ports and alternate-function pins (except bus interface alternate port) HLDAK Output No Bus hold acknowledge output P95 HLDRQ Input No Bus hold request input P96 IC −− Internally connected (µPD703034A, 703034AY, 703035A, 703035AY only) Remark PULL: On-chip pull-up resistor

Data Sheet U14780EJ2V1DS12 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (2/4) Pin Name I/O PULL Function Alternate Function IERX Input IEBus data input P104/RTP4/A9/KR4 IETX Output Yes IEBus data output P105/RTP5/A10/KR5 INTP0 P01 INTP1 P02 INTP2 P03 INTP3 Input Yes External interrupt request input (analog noise elimination) P04 INTP4 P05/ADTRG INTP5 Input Yes External interrupt request input (digital noise elimination) P06/RTPTRG INTP6 Input Yes External interrupt request input (digital noise elimination supporting remote controller) P07 KR0 P100/RTP0/A5 KR1 P101/RTP1/A6 KR2 P102/RTP2/A7 KR3 P103/RTP3/A8 KR4 P104/RTP4/A9/IERX KR5 P105/RTP5/A10/IETX KR6 P106/RTP6/A11 KR7 Input Yes Key return input P107/RTP7/A12 LBEN Output No External data bus’s lower byte enable output P90/WRL NMI Input Yes Non-maskable interrupt request input P00 RD Output No Read strobe output P93/DSTB REGC −− Regulator output stabilization capacitance connection − RESET Input − System reset input − RTP0 P100/KR0/A5 RTP1 P101/KR1/A6 RTP2 P102/KR2/A7 RTP3 P103/KR3/A8 RTP4 P104/KR4/A9/IERX RTP5 P105/KR5/A10/IETX RTP6 P106/KR6/A11 RTP7 Output Yes Real-time output port P107/KR7/A12 RTPTRG Input Yes Real-time output port external trigger input P06/INTP5 R/W Output No External read/write status output P92/WRH RXD0 P13/SI1 RXD1 Input Yes Serial receive data input for UART0 and UART1 P23/SI3 Remark PULL: On-chip pull-up resistor

Data Sheet U14780EJ2V1DS 13 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (3/4) Pin Name I/O PULL Function Alternate Function SCK0 P12/SCL0 SCK1 P15/ASCK0 SCK2 P22/SCL1 SCK3 I/O Yes Serial clock I/O (3-wire type) for CSI0 to CSI3 P25/ASCK1 SCK4 I/O Yes Serial clock I/O (3-wire type) for variable length CSI4 P34/TO0/A13 SCL0 P12/SCK0 SCL1 I/O Yes Serial clock I/O for I C0 and I (µPD703034AY, 703035AY, 70F3035AY only) P22/SCK2 SDA0 P10/SI0 SDA1 I/O Yes Serial transmit/receive data I/O for I C0 and I (µPD703034AY, 703035AY, 70F3035AY only) P20/SI2 SI0 P10/SDA0 SI1 P13/RXD0 SI2 P20/SDA1 SI3 Input Yes Serial receive data input (3-wire type) for CSI0 to CSI3 P23/RXD1 SI4 Input Yes Serial receive data input (3-wire type) for variable length CSI4 P32/TI10 SO0 P11 SO1 P14/TXD0 SO2 P21 SO3 Output Yes Serial transmit data output (3-wire type) for CSI0 to CSI3 P24/TXD1 SO4 Output Yes Serial transmit data output (3-wire type) for variable length CSI4 P33/TI11 TI00 External count clock input for TM0/external capture trigger input for TM0 P30 TI01 External capture trigger input for TM0 P31 TI10 External count clock input for TM1/external capture trigger input for TM1 P32/SI4 TI11 Input Yes External capture trigger input for TM1 P33/SO4 TI2 P26/TO2 TI3 P27/TO3 TI4 P36/TO4/A15 TI5 Input Yes External count clock input for TM2 to TM5 P37/TO5 TO0 P34/A13/SCK4 TO1 Output Yes Pulse signal output for TM0 and TM1 P35/A14 TO2 P26/TI2 TO3 P27/TI3 TO4 P36/TI4/A15 TO5 Output Yes Pulse signal output for TM2 to TM5 P37/TI5 TXD0 P14/SO1 TXD1 Output Yes Serial transmit data output for UART0 and UART1 P24/SO3 UBEN Output No Higher byte enable output for external data bus P91 VDD −− Positive power supply pin − Remark PULL: On-chip pull-up resistor

Data Sheet U14780EJ2V1DS14 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (4/4) Pin Name I/O PULL Function Alternate Function VPP −− High voltage apply pin for program write/verify (µPD70F3035A, 70F3035AY only) VSS −− Ground potential − WAIT Input Yes Control signal input for inserting wait in bus cycle P 110/A1 WRH Output No Higher byte write strobe signal output for external data bus P92/R/W WRL Output No Lower byte write strobe signal output for external data bus P90/LBEN X1 Input − X2 − No Resonator connection for main clock XT1 Input − XT2 − No Resonator connection for sub system clock Remark PULL: On-chip pull-up resistor

Data Sheet U14780EJ2V1DS 15 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are show in Table 2-1. For the input/output schematic circuit diagram of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits (1/2) Pin Alternate Function I/O Circuit Type I/O Buffer Power Supply Recommended Connection of Unused Pins P00 NMI P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4/ADTRG P06 INTP5/RTPTRG P07 INTP6 8-A EV DD Input state: Independently connect to EV DD or EVSS via a resistor. Output state: Leave open. P10 SI0/SDA0 10-A P11 SO0 26 P12 SCK0/SCL0 10-A P13 SI1/RXD0 8-A P14 SO1/TXD0 26 P15 SCK1/ASCK0 10-A EVDD Input state: Independently connect to EV DD or EVSS via a resistor. Output state: Leave open. P20 SI2/SDA1 10-A P21 SO2 26 P22 SCK2/SCL1 10-A P23 SI3/RXD1 8-A P24 SO3/TXD1 26 P25 SCK3/ASCK1 10-A P26 TI2/TO2 P27 TI3/TO3 8-A EVDD Input state: Independently connect to EV DD or EVSS via a resistor. Output state: Leave open. P30 TI00 P31 TI01 P32 TI10/SI4 P33 TI11/SO4 P34 TO0/A13/SCK4 8-A P35 TO1/A14 5-A P36 TI4/TO4/A15 P37 TI5/TO5 8-A EVDD Input state: Independently connect to EV DD or EVSS via a resistor. Output state: Leave open. P40 to P47 AD0 to AD7 5 BV DD P50 to P57 AD8 to AD15 5 BV DD P60 to P65 A16 to A21 5 BV DD Input state: Independently connect to BV DD or BVSS via a resistor. Output state: Leave open.

Data Sheet U14780EJ2V1DS16 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Table 2-1. Types of Pin I/O Circuits (2/2) Pin Alternate Function I/O Circuit Type I/O Buffer Power Supply Recommended Connection of Unused Pins P70 to P77 ANI0 to ANI7 9 AV DD P80 to P83 ANI8 to ANI11 9 AV DD Independently connect to AV DD or AV SS via a resistor. P90 LBEN /WRL P91 UBEN P92 R/W /WRH P93 DSTB /RD P94 ASTB P95 HLDAK P96 HLDRQ 5B V DD Input state: Independently connect to BV DD or BVSS via a resistor. Output state: Leave open. P100 RTP0/A5/KR0 P101 RTP1/A6/KR1 P102 RTP2/A7/KR2 P103 RTP3/A8/KR3 P104 RTP4/A9/KR4/IERX P105 RTP5/A10/KR5/IETX P106 RTP6/A11/KR6 P107 RTP7/A12/KR7 10-A EV DD Input state: Independently connect to EV DD or EVSS via a resistor. Output state: Leave open. P110 A1/WAIT P111 A2 P112 A3 P113 A4 5-A EV DD Input state: Independently connect to EV DD or EVSS via a resistor. Output state: Leave open. CLKOUT – 4 BV DD Leave open. RESET – 2 EV DD – XT1 – 16 – Connect to V SS via a resistor. XT2 – 16 – Leave open. AVREF – – – Connect to AV SS via a resistor. IC Note 1 – – – Connect directly to V SS. VPP Note 2 – – – Connect to V SS. Notes 1. µPD703034A, 703034AY, 703035A, 703035AY 2. µPD70F3035A, 70F3035AY Caution Three power supply systems are available to supply power to the I/O buffers of the V850/SB2’s pins: EVDD, BVDD, and AV DD. The voltage ranges that can be used for these I/O buffer power supplies are shown below. EVDD, BVDD: 3.0 V to 5.5 V AVDD: 4.5 V to 5.5 V The electrical specifications differ depending on whether the power supply voltage range is 3.0 V to under 4.0 V, or 4.0 V to 5.5 V.

Data Sheet U14780EJ2V1DS 17 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Figure 2-1. Pin Input/Output Circuits (1/2) Type 2 Schmitt-triggered input with hysteresis characteristics Push-pull output that can be set for high-impedance output (both P-ch and N-ch off) IN Data Output disable P-ch OUT VDD N-ch Data Output disable P-ch IN/OUT VDD N-ch Input enable Data Output disable P-ch IN/OUT VDD N-ch Input enable P-ch VDD Pullup enable Data Output disable P-ch IN/OUT VDD N-ch P-ch VDD Pullup enable IN Comparator VREF (threshold voltage) P-ch N-ch Input enable Type 4 Type 5 Type 9 Type 8-A Type 5-A Caution V DD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.

Data Sheet U14780EJ2V1DS18 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Figure 2-1. Pin Input/Output Circuits (2/2) Data Output disable P-ch IN/OUT VDD N-ch P-ch VDD Pullup enable Open drain P-ch Feedback cut-off XT1 XT2 Data Output disable Open drain P-ch IN/OUT VDD N-ch P-ch VDD Pullup enable Type 10-A Type 26 Type 16 Caution V DD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.

Data Sheet U14780EJ2V1DS 19 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, VSS = 0 V) Parameter Symbol Conditions Ratings Unit VDD VDD pin –0.5 to +7.0 V VPP µPD70F3035A, 70F3035AY only −0.5 to +8.5 V AVDD AVDD pin –0.5 to +7.0 V BVDD BVDD pin –0.5 to +7.0 V EVDD EVDD pin –0.5 to +7.0 V AVSS AVSS pin –0.5 to +0.5 V BVSS BVSS pin –0.5 to +0.5 V Supply voltage EVSS EVSS pin –0.5 to +0.5 V VI1 Note 1 (BVDD pin) –0.5 to BV DD + 0.5 Note 4 VInput voltage VI2 Note 2, RESET (EVDD pin) –0.5 to EV DD + 0.5 Note 4 V Analog input voltage V IAN Note 3 (AVDD pin) –0.5 to AV DD + 0.5 Note 4 V Analog reference input voltage AV REF AVREF pin –0.5 to AV DD + 0.5 Note 4 V Per pin 4.0 mA Total for P00 to P07, P10 to P15, P20 to P25 25 mA Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 25 mA Total for P40 to P47, P90 to P96, CLKOUT 25 mA Output current, low I OL Total for P50 to P57, P60 to P65 25 mA Per pin –4.0 mA Total for P00 to P07, P10 to P15, P20 to P25 –25 mA Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 –25 mA Total for P40 to P47, P90 to P96, CLKOUT –25 mA Output current, high I OH Total for P50 to P57, P60 to P65 –25 mA VO1 Note 1, CLKOUT (BVDD pin) –0.5 to BV DD + 0.5 Note 4 VOutput voltage VO2 Note 2 (EVDD pin) –0.5 to EV DD + 0.5 Note 4 V Normal operation mode –40 to +85 °COperating ambient temperature T A Flash memory programming mode (µPD70F3035A, 70F3035AY only) Note 5 °C µPD703034A, 703034AY µPD703035A, 703035AY –65 to +150 °CStorage temperature T stg µPD70F3035A, 70F3035AY –40 to +125 °C Notes 1. Ports 4, 5, 6, 9, and their alternate-function pins 2. Ports 0, 1, 2, 3, 10, 11, and their alternate-function pins 3. Ports 7, 8, and their alternate-function pins 4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 5. I, K, E rank products: T A = 10 to 85°C P rank product: T A = −20 to +85°C The rank is indicated by the letter appearing as the 5th digit from the left in the lot number.

Data Sheet U14780EJ2V1DS20 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V DD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (T A = 25°C, VDD = AVDD = BVDD = EVDD = VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance C I 15 pF I/O capacitance C IO 15 pF Output capacitance C O fC = 1 MHz Unmeasured pins returned to 0 V 15 pF Operating Conditions (1) Operating frequency AVDDOperating Frequency (fXX)V DD Note 1 Note 2 BVDD EVDD Remark Notes 1. When A/D converter is used 2. When A/D converter is not used 3. During STOP mode (when only watch timer is operating), V DD = 3.5 to 5.5 V. Shifting to STOP mode or restoring from STOP mode must be performed at VDD = 4.0 V min. 4. Shifting to IDLE mode or restoring from IDLE mode must be performed at VDD = 4.0 V min. (2) CPU operating frequency Parameter Symbol Conditions MIN. TYP. MAX. Unit Main clock operation 0.25 13 MHzCPU operating frequency f CPU Subclock operation 32.768 kHz

Data Sheet U14780EJ2V1DS 21 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Recommended Oscillator (1) Main clock oscillator (T A = –40 to +85°C) (a) Connection of ceramic resonator or crystal resonator X2X1 Rf Rd Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency f XX 21 3 M H z – Upon reset release 2 /fXX sOscillation stabilization time – Upon STOP mode release Note s Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS). Cautions 1. The main clock oscillator operates on the output voltage of the on-chip regulator (3.0 V). External clock input is prohibited. 2. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance.

• ••• Keep the wiring length as short as possible.
• ••• Do not cross the wiring with the other signal lines.
• ••• Do not route the wiring near a signal line through which a high fluctuating current flows.
• ••• Always make the ground point of the oscillator capacitor the same potential as VSS.
• ••• Do not ground the capacitor to a ground pattern through which a high current flows.
• ••• Do not fetch signals from the oscillator. 3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. Sufficiently evaluate the matching between the µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY and the resonator.

Data Sheet U14780EJ2V1DS22 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (i) Murata Mfg. Co., Ltd.: Ceramic resonator (T A = –40 to +85°C) Recommended Circuit Constant Oscillation Voltage Range Manufacturer Part Number Oscillation Frequency fXX (MHz) C1 (pF) C2 (pF) Rf (k Ω)R d ( k Ω) MIN. (V) MAX. (V) CSTLS6M29G53-B0 6.290 On-chip On-chip − 04 . 0 5 . 5 CSTCR6M29G53-R0 On-chip On-chip − 04 . 0 5 . 5 CSTLA12M5T55001-B0 12.583 On-chip On-chip − 04 . 0 5 . 5 Murata Mfg. Co., Ltd. CSTCV12M5T54J01-R0 On-chip On-chip − 04 . 0 5 . 5 Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. (2) Subclock oscillator (T A = –40 to +85°C) (a) Connection of crystal resonator XT1 XT2 Parameter Symbol Conditions MIN. TYP. MAX. Unit Oscillation frequency f XT 32 32.768 35 kHz Oscillation stabilization time – 10 s Cautions 1. The subclock oscillator operates on the output voltage of the on-chip regulator (3.0 V). External clock input is prohibited. 2. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance.

• ••• Keep the wiring length as short as possible.
• ••• Do not cross the wiring with the other signal lines.
• ••• Do not route the wiring near a signal line through which a high fluctuating current flows.
• ••• Always make the ground point of the oscillator capacitor the same potential as VSS.
• ••• Do not ground the capacitor to a ground pattern through which a high current flows.
• ••• Do not fetch signals from the oscillator. 3. Sufficiently evaluate the matching between the µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY and the resonator.

Data Sheet U14780EJ2V1DS 23 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY DC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ BVDD ≤ 5.5 V 0.7BVDD BVDD VVIH1 Note 1 3.0 V ≤ BVDD < 4.0 V 0.8BVDD BVDD V 4.0 V ≤ EVDD ≤ 5.5 V 0.7EVDD EVDD VVIH2 Note 2 3.0 V ≤ EVDD < 4.0 V 0.8EVDD EVDD V 4.0 V ≤ EVDD ≤ 5.5 V 0.7EVDD EVDD VVIH3 Note 3, RESET 3.0 V ≤ EVDD < 4.0 V 0.8EVDD EVDD V Input voltage, high VIH4 Note 4 0.7AVDD AVDD V VIL1 Note 1 BVSS 0.3BVDD V VIL2 Note 2 EVSS 0.3EVDD V VIL3 Note 3, RESET EV SS 0.3EVDD V Input voltage, low VIL4 Note 4 AVSS 0.3AVDD V 3.0 V ≤ BVDD ≤ 5.5 V, IOH = –100 µA BVDD–0.5 VVOH1 Note 1, CLKOUT 4.0 V ≤ BVDD ≤ 5.5 V, IOH = –3 mA BVDD–1.0 V 3.0 V ≤ EVDD ≤ 5.5 V, IOH = –100 µA EVDD–0.5 V Output voltage, high VOH2 Notes 2, 3 4.0 V ≤ EVDD ≤ 5.5 V, IOH = –3 mA EVDD–1.0 V IOL = 3 mA, 3.0 V ≤ BVDD, EVDD ≤ 5.5 V

0.5 VOutput voltage, low V OL

IOL = 3 mA, 4.0 V ≤ BVDD, EVDD ≤ 5.5 V 0.4 V VPP power supply voltage V PP1 Normal operation 0 0.54 V Input leakage current, high I LIH VI = VDD = BVDD = EVDD = AVDD 5 µA Input leakage current, low I LIL VI = 0 V –5 µA Output leakage current, high I LOH VO = VDD = BVDD = EVDD = AVDD 5 µA Output leakage current, low I LOL VO = 0 V –5 µA Notes 1. Ports 4, 5, 6, 9, and their alternate-function pins 2. P11, P14, P21, P24, P34, P35, P110 to P113, and their alternate-function pins 3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P100 to P107, and their alternate-function pins 4. Ports 7, 8, and their alternate-function pins

Data Sheet U14780EJ2V1DS24 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY DC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit µPD703034A, I DD1 In normal operation mode Note 1 15 25 mA µPD703034AY, I DD2 In HALT mode Note 1 61 3 m A µPD703035A, IDD3 In IDLE mode Note 2 Watch timer operating 1 4 mA Watch timer, subclock oscillator operating 13 70 µAIDD4 In STOP mode Subclock oscillator stopped, XT1 = VSS 87 0 µA IDD5 In normal operation mode (subclock operation) Note 3 50 150 µA µPD703035AY IDD6 In IDLE mode (subclock operation) Note 3 13 70 µA µPD70F3035A, I DD1 In normal operation mode Note 1 25 48 mA IDD2 In HALT mode Note 1 71 5 m A IDD3 In IDLE mode Note 2 Watch timer operating 1 4 mA Watch timer, subclock oscillator operating 13 100 µAIDD4 In STOP mode Subclock oscillator stopped, XT1 = VSS 8 100 µA IDD5 In normal operation mode (subclock operation) Note 3 200 600 µA Supply current µPD70F3035AY IDD6 In IDLE mode (subclock operation) Note 3 90 180 µA Pull-up resistance R L VIN = 0 V 10 30 100 k Ω Notes 1. fCPU = fXX = 13 MHz, all peripheral functions operating 2. fXX = 13 MHz 3. fCPU = fXT = 32.768 kHz, main clock oscillator stopped Remark TYP. values are reference values for when TA = 25°C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current consumed by the output buffer is not included.

Data Sheet U14780EJ2V1DS 25 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Data Retention Characteristics (TA = –40 to +85°C, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage V DDDR STOP mode (all functions not operating) 2.7 Note 5.5 V µPD703034A, µPD703034AY, µPD703035A, µPD703035AY 87 0 µAData retention current I DDDR VDD = VDDDR, XT1 = VSS (Subclock stopped) µPD70F3035A, µPD70F3035AY 8 100 µA Power supply voltage rise time t RVD 200 µs Power supply voltage fall time t FVD 200 µs Power supply voltage hold time (from STOP mode setting) tHVD 0m s STOP mode release signal input time t DREL 0m s Data retention high-level input voltage V IHDR All input ports 0.9V DDDR VDDDR V Data retention low-level input voltage V ILDR All input ports 0 0.1V DDDR V Note During STOP mode (when only watch timer is operating), V DD = 3.5 to 5.5 V. Shifting to STOP mode or restoring from STOP mode must be performed at VDD = 4.0 V min. Remark TYP. values are reference values for when TA = 25°C. tHVD V DDDR tDREL V IHDR V IHDR tFVD tRVD VDD Stop mode release interrupt (NMI, etc.) (Release by falling edge) Stop mode release interrupt (NMI, etc.) (Release by rising edge) Setting STOP mode RESET (input) V ILDR

4.0 VNote

Note VDD = 4.0 V indicates the minimum operating voltage of the V850/SB2.

Data Sheet U14780EJ2V1DS26 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY AC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V (when A/D converter is used), AVDD = 4.0 to 5.5 V (when A/D converter is not used), VSS = AVSS = BVSS = EVSS = 0 V) AC Test Input Test Point (VDD: EVDD, BVDD, AVDD) VDD 0 V VIH VIL VIH VIL Measurement pointsInput signal AC Test Output Test Points (VDD: EVDD, BVDD) VOH VOL VOH VOL Measurement pointsOutput signal VDD 0 V Load Conditions DUT (Device under test) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.

Data Sheet U14780EJ2V1DS 27 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (1) Clock timing (a) T A = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V Parameter Symbol Conditions MIN. MAX. Unit CLKOUT output cycle <1> t CYK 76.9 ns 31.2 µs CLKOUT high-level width <2> t WKH 0.4tCYK – 12 ns CLKOUT low-level width <3> t WKL 0.4tCYK – 12 ns CLKOUT rise time <4> t KR 12 ns CLKOUT fall time <5> t KF 12 ns Parameter Symbol Conditions MIN. MAX. Unit CLKOUT output cycle <1> t CYK 76.9 ns 31.2 µs CLKOUT high-level width <2> t WKH 0.4tCYK – 15 ns CLKOUT low-level width <3> t WKL 0.4tCYK – 15 ns CLKOUT rise time <4> t KR 15 ns CLKOUT fall time <5> t KF 15 ns CLKOUT (output) <2> <4> <5> <3> <1>

Data Sheet U14780EJ2V1DS28 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (2) Output waveform (other than port 4, port 5, port 6, port 9, and CLKOUT) (TA = –40 to +85°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Output rise time <6> t OR 20 ns Output fall time <7> t OF 20 ns <7><6> Output signal (3) Reset timing (TA = –40 to +85°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit RESET pin high-level width <8> t WRSH 500 ns RESET pin low-level width <9> t WRSL 500 ns <8> <9> RESET (input)

Data Sheet U14780EJ2V1DS 29 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (4) Bus timing (a) Clock asynchronous (T A = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to ASTB↓) <10> t SAST 0.5T – 16 ns Address hold time (from ASTB↓) <11> t HSTA 0.5T – 15 ns Address float delay time from DSTB↓ <12> t FDA 0n s Data input setup time from address <13> t SAID (2 + n)T – 40 ns Data input setup time from DSTB↓ <14> t SDID (1 + n)T – 40 ns Delay time from ASTB↓ to DSTB↓ <15> t DSTD 0.5T – 15 ns Data input hold time (from DSTB↑) <16> t HDID 0n s Address output time from DSTB↑ <17> t DDA (1 + i)T – 15 ns Delay time from DSTB↑ to ASTB↑ <18> t DDST1 0.5T – 15 ns Delay time from DSTB↑ to ASTB↓ <19> t DDST2 (1.5 + i)T – 15 ns DSTB low-level width <20> t WDL (1 + n)T – 22 ns ASTB high-level width <21> t WSTH T – 15 ns Data output time from DSTB↓ <22> t DDOD 10 ns Data output setup time (to DSTB↑) <23> t SODD (1 + n)T – 25 ns Data output hold time (from DSTB↑) <24> t HDOD T – 20 ns <25> t SAWT1 n ≥ 1 1.5T – 40 nsWAIT setup time (to address) <26> t SAWT2 n ≥ 1 (1.5 + n)T – 40 ns <27> t HAWT1 n ≥ 1 (0.5 + n)T nsWAIT hold time (from address) <28> t HAWT2 n ≥ 1 (1.5 + n)T ns <29> t SSTWT1 n ≥ 1T – 32 nsWAIT setup time (to ASTB↓) <30> t SSTWT2 n ≥ 1 (1 + n)T – 32 ns <31> t HSTWT1 n ≥ 1n Tn sWAIT hold time (from ASTB↓) <32> t HSTWT2 n ≥ 1 (1 + n)T ns HLDRQ high-level width <33> t WHQH T + 10 ns HLDAK low-level width <34> t WHAL T – 15 ns Bus output delay time from HLDAK↑ <35> t DHAC –6n s Delay time from HLDRQ↓ to HLDAK↓ <36> t DHQHA1 (2n + 7.5)T + 25 ns Delay time from HLDRQ↑ to HLDAK↑ <37> t DHQHA2 0.5T 1.5T + 25 ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after a read cycle (0 or 1). 4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.

Data Sheet U14780EJ2V1DS30 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Address setup time (to ASTB↓) <10> t SAST 0.5T – 20 ns Address hold time (from ASTB↓) <11> t HSTA 0.5T – 20 ns Address float delay time from DSTB↓ <12> t FDA 0n s Data input setup time from address <13> t SAID (2 + n)T – 50 ns Data input setup time from DSTB↓ <14> t SDID (1 + n)T – 50 ns Delay time from ASTB↓ to DSTB↓ <15> t DSTD 0.5T – 15 ns Data input hold time (from DSTB↑) <16> t HDID 0n s Address output time from DSTB↑ <17> t DDA (1 + i)T – 15 ns Delay time from DSTB↑ to ASTB↑ <18> t DDST1 0.5T – 15 ns Delay time from DSTB↑ to ASTB↓ <19> t DDST2 (1.5 + i)T – 15 ns DSTB low-level width <20> t WDL (1 + n)T – 35 ns ASTB high-level width <21> t WSTH T – 15 ns Data output time from DSTB↓ <22> t DDOD 10 ns Data output setup time (to DSTB↑) <23> t SODD (1 + n)T – 35 ns Data output hold time (from DSTB↑) <24> t HDOD T – 25 ns <25> t SAWT1 n ≥ 1 1.5T – 55 nsWAIT setup time (to address) <26> t SAWT2 n ≥ 1 (1.5 + n)T – 55 ns <27> t HAWT1 n ≥ 1 (0.5 + n)T nsWAIT hold time (from address) <28> t HAWT2 n ≥ 1 (1.5 + n)T ns <29> t SSTWT1 n ≥ 1T – 45 nsWAIT setup time (to ASTB↓) <30> t SSTWT2 n ≥ 1 (1 + n)T – 45 ns <31> t HSTWT1 n ≥ 1n Tn sWAIT hold time (from ASTB↓) <32> t HSTWT2 n ≥ 1 (1 + n)T ns HLDRQ high-level width <33> t WHQH T + 10 ns HLDAK low-level width <34> t WHAL T – 25 ns Bus output delay time from HLDAK↑ <35> t DHAC –6n s Delay time from HLDRQ↓ to HLDAK↓ <36> t DHQHA1 (2n + 7.5)T + 25 ns Delay time from HLDRQ↑ to HLDAK↑ <37> t DHQHA2 0.5T 1.5T + 25 ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after a read cycle (0 or 1). 4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.

Data Sheet U14780EJ2V1DS 31 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (c) Clock synchronous (T A = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT↑ to address <38> t DKA 01 9 n s Delay time from CLKOUT↑ to address float <39> t FKA –12 10 ns Delay time from CLKOUT↓ to ASTB <40> t DKST 01 9 n s Delay time from CLKOUT↑ to DSTB <41> t DKD 01 9 n s Data input setup time (to CLKOUT↑) <42> t SIDK 20 ns Data input hold time (from CLKOUT↑) <43> t HKID 5n s Data output delay time from CLKOUT↑ <44> t DKOD 19 ns WAIT setup time (to CLKOUT↓) <45> t SWTK 20 ns WAIT hold time (from CLKOUT↓) <46> t HKWT 5n s HLDRQ setup time (to CLKOUT↓) <47> t SHQK 20 ns HLDRQ hold time (from CLKOUT↓) <48> t HKHQ 5n s Delay time from CLKOUT↑ to address float (during bus hold) <49> t DKF 19 ns Delay time from CLKOUT↑ to HLDAK <50> t DKHA 19 ns Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1. VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit Delay time from CLKOUT↑ to address <38> t DKA 02 2 n s Delay time from CLKOUT↑ to address float <39> t FKA –16 10 ns Delay time from CLKOUT↓ to ASTB <40> t DKST 01 9 n s Delay time from CLKOUT↑ to DSTB <41> t DKD 02 2 n s Data input setup time (to CLKOUT↑) <42> t SIDK 20 ns Data input hold time (from CLKOUT↑) <43> t HKID 5n s Data output delay time from CLKOUT↑ <44> t DKOD 22 ns WAIT setup time (to CLKOUT↓) <45> t SWTK 24 ns WAIT hold time (from CLKOUT↓) <46> t HKWT 5n s HLDRQ setup time (to CLKOUT↓) <47> t SHQK 24 ns HLDRQ hold time (from CLKOUT↓) <48> t HKHQ 5n s Delay time from CLKOUT↑ to address float (during bus hold) <49> t DKF 19 ns Delay time from CLKOUT↑ to HLDAK <50> t DKHA 19 ns Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.

Data Sheet U14780EJ2V1DS32 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) ASTB (output) T1 T2 TW <38> <15> <20> <45> DSTB, RD (output) WAIT (input) AD0 to AD15 (I/O) <39> <10> <43> <40> <42><13> <21> <16> <14> <19> <17> <18> <41> <12> <29> <31> <25> <27> <26> <28> <30> DataAddress <40> <11> <41> <32> A1 to A15 (output) A16 to A21 (output) Note (output) Note R/W, UBEN, LBEN Remarks 1. The broken lines indicate high impedance. 2. WRL and WRH are high level.

Data Sheet U14780EJ2V1DS 33 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) ASTB (output) T1 T2 TW <38> <15> <20> <45> A1 to A15 (output) A16 to A21 (output) Note (output) DSTB, WRL, WRH (output) WAIT (input) AD0 to AD15 (I/O) <44> <10> <40> <21> <23> <24> <18> <41> <22> <29> <31> <25> <27> <26> <28> <30> DataAddress <40> <11> <41> <32> Note R/W, UBEN, LBEN Remarks 1. The broken lines indicate high impedance. 2. RD is high level.

Data Sheet U14780EJ2V1DS34 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (g) Bus hold timing CLKOUT (output) TH A1 to A15 (output) <47>< 48> TH TH TH TI <47> <36> <50>< 50> <34> <37> <33> <49> <35> A16 to A21 (output) Note (output) HLDRQ (input) HLDAK (output) ASTB (output) DSTB, RD (output) WRL, WRH (output) AD0 to AD15 (I/O) Data Note R/W, UBEN, LBEN Remark The broken lines indicate high impedance.

Data Sheet U14780EJ2V1DS 35 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (5) Interrupt timing (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit NMI high-level width <51> t WNIH 500 ns NMI low-level width <52> t WNIL 500 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3T + 20 ns INTPn high-level width <53> t WITH n = 6, digital noise elimination 3Tsmp + 20 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3T + 20 ns INTPn low-level width <54> t WITL n = 6, digital noise elimination 3Tsmp + 20 ns Remarks 1. T = 1/fXX 2. Tsmp = Noise elimination sampling clock cycle <51> <52> NMI (input) <53> <54> INTPn (input) Remark n = 0 to 6

Data Sheet U14780EJ2V1DS36 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (6) RPU timing (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit TIn0, TIn1 high-level width <55> t TIHn n = 0, 1 2T sam + 20 Note ns TIn0, TIn1 low-level width <56> t TILn n = 0, 1 2T sam + 20 Note ns TIm high-level width <57> t TIHm m = 2 to 5 3T + 20 ns TIm low-level width <58> t TILm m = 2 to 5 3T + 20 ns Note Tsam can select the following count clocks by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0, n1 (PRMn0, PRMn1). When n = 0 (TM0), Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle When n = 1 (TM1), Tsam = 2T, 4T, 16T, 32T, 128T, or 256T However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T. Remark T = 1/fXX <55> <56> TIn0, TIn1 (input) <57> <58> TIm (input) Remark n = 0, 1 m = 2 to 5 (7) Asynchronous serial interface (UART0, UART1) timing (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit ASCKn cycle time <59> t KCY13 200 ns ASCKn high-level width <60> t KH13 80 ns ASCKn low-level width <61> t KL13 80 ns Remark n = 0, 1 <60> <61> <59> ASCKn (input) Remark n = 0, 1

Data Sheet U14780EJ2V1DS 37 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (8) 3-wire serial interface (CSI0 to CSI3) timing (a) Master mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCKn cycle <62> t KCY1 400 ns SCKn high-level width <63> t KH1 140 ns SCKn low-level width <64> t KL1 140 ns SIn setup time (to SCKn↑) <65> t SIK1 50 ns SIn hold time (from SCKn↑) <66> t KSI1 50 ns Delay time from SCKn↓ to SOn output <67> t KSO1 60 ns Remark n = 0 to 3 (b) Slave mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = VSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCKn cycle <62> t KCY2 400 ns SCKn high-level width <63> t KH2 140 ns SCKn low-level width <64> t KL2 140 ns SIn setup time (to SCKn↑) <65> t SIK2 50 ns SIn hold time (from SCKn↑) <66> t KSI2 50 ns 4.0 V ≤ EVDD ≤ 5.5 V 60 nsDelay time from SCKn↓ to SOn output <67> t KSO2 3.0 V ≤ EVDD < 4.0 V 100 ns Remark n = 0 to 3 <66> <67> <65> <62> <63> <64> Remarks 1. The broken lines indicate high impedance. 2. n = 0 to 3 SCKn (I/O) SIn (input) SOn (output) Input data Output data

Data Sheet U14780EJ2V1DS38 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (9) 3-wire variable length serial interface (CSI4) timing (a) Master mode (TA = –40 to +85°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit 4.0 V ≤ EVDD ≤ 5.5 V 200 nsSCK4 cycle <68> t KCY1 3.0 V ≤ EVDD < 4.0 V 400 ns 4.0 V ≤ EVDD ≤ 5.5 V 60 nsSCK4 high-level width <69> t KH1 3.0 V ≤ EVDD < 4.0 V 140 ns 4.0 V ≤ EVDD ≤ 5.5 V 60 nsSCK4 low-level width <70> t KL1 3.0 V ≤ EVDD < 4.0 V 140 ns 4.0 V ≤ EVDD ≤ 5.5 V 25 nsSI4 setup time (to SCK4↑) <71> t SIK1 3.0 V ≤ EVDD < 4.0 V 50 ns SI4 hold time (from SCK4↑) <72> t KSI1 20 ns Delay time from SCK4 ↓ to SO4 output <73> t KSO1 55 ns (b) Slave mode (TA = –40 to +85°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. MAX. Unit 4.0 V ≤ EVDD ≤ 5.5 V 200 nsSCK4 cycle <68> t KCY2 3.0 V ≤ EVDD < 4.0 V 400 ns 4.0 V ≤ EVDD ≤ 5.5 V 60 nsSCK4 high-level width <69> t KH2 3.0 V ≤ EVDD < 4.0 V 140 ns 4.0 V ≤ EVDD ≤ 5.5 V 60 nsSCK4 low-level width <70> t KL2 3.0 V ≤ EVDD < 4.0 V 140 ns 4.0 V ≤ EVDD ≤ 5.5 V 25 nsSI4 setup time (to SCK4↑) <71> t SIK2 3.0 V ≤ EVDD < 4.0 V 50 ns SI4 hold time (from SCK4↑) <72> t KSI2 20 ns 4.0 V ≤ EVDD ≤ 5.5 V 55 nsDelay time from SCK4 ↓ to SO4 output <73> t KSO2 3.0 V ≤ EVDD < 4.0 V 100 ns

Data Sheet U14780EJ2V1DS 39 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY <68> <70><69> <71> <72> <73> SI4 (input) SO4 (output) SCK4 (I/O) Output data Input data Remark The broken lines indicate high impedance.

Data Sheet U14780EJ2V1DS40 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (10)I C bus mode (µµµµPD703034AY, 703035AY, 70F3035AY only) (1/2) (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Normal Mode High-Speed ModeParameter Symbol MIN. MAX. MIN. MAX. Unit SCLn clock frequency – f CLK 0 100 0 400 kHz Bus-free time (between stop/start conditions) <74> t BUF 4.7 – 1.3 – µs Hold time Note 1 <75> t HD:STA 4.0 – 0.6 – µs SCLn clock low-level width <76> t LOW 4.7 – 1.3 – µs SCLn clock high-level width <77> t HIGH 4.0 – 0.6 – µs Setup time for start/restart conditions <78> t SU:STA 4.7 – 0.6 – µs CBUS compatible master 5.0 – – – µsData hold time I C mode <79> t HD:DAT Note 2 Note 2 0.9 Note 3 µs Data setup time <80> t SU:DAT 250 – 100 Note 4 –n s SDAn and SCLn signal rise time <81> t R – 1000 20 + 0.1Cb Note 5 300 ns SDAn and SCLn signal fall time <82> t F – 300 20 + 0.1Cb Note 5 300 ns Stop condition setup time <83> t SU:STO 4.0 – 0.6 – µs Pulse width of spike suppressed by input filter <84> t SP ––0 5 0 n s Capacitance load of each bus line – Cb – 400 – 400 pF Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at V IHmin.. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (t LOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the high-speed mode I C bus so that it meets the following conditions.

• If the system does not extend the SCLn signal’s low state hold time: tSU:DAT ≥ 250 ns
• If the system extends the SCLn signal’s low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0, 1

Data Sheet U14780EJ2V1DS 41 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY (10)I C bus mode (µµµµPD703034AY, 703035AY, 70F3035AY only) (2/2) Stop condition Start condition Restart condition Stop condition SCLn (I/O) SDAn (I/O) <75> <74> <76> <77> <81> <82> Remark n = 0, 1 A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V, Output pin load capacitance: CL = 50 pF) Parameter Symbol Conditions MIN. TYP. MAX. Unit R e s o l u t i o n – 1 01 01 0 b i t ADM2 = 00H ±0.6 %FSROverall error Note 1 ADM2 = 01H ±1.0 %FSR Conversion time t CONV 51 0 µs Zero-scale error Note 1 ±0.4 %FSR ADM2 = 00H ±0.4 %FSRFull-scale error Note 1 ADM2 = 01H ±0.6 %FSR ADM2 = 00H ±4.0 LSBIntegral linearity error Note 2 ADM2 = 01H ±6.0 LSB ADM2 = 00H ±4.0 LSBDifferential linearity error Note 2 ADM2 = 01H ±6.0 LSB Analog reference voltage AV REF AVREF = AVDD 4.5 5.5 V Analog power supply voltage AV DD 4.5 5.5 V Analog input voltage V IAN AVSS AVREF V AVREF input current AI REF 12 m A ADM2 = 00H 3 6 mAAVDD power supply current AI DD Operating current ADM2 = 01H 4 8 mA Notes 1. Excluding quantization error (±0.05 %FSR) 2. Excluding quantization error (±0.5 LSB) Remarks 1. LSB: Least Significant Bit FSR: Full Scale Range 2. ADM2: A/D converter mode register 2

Data Sheet U14780EJ2V1DS42 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY IEBus Controller Characteristics (TA = –40 to +85°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 6.0 Note 1 MHzIEBus system clock frequency fS Communication mode: fixed to mode 1 6.29 Notes 1, 2 MHz Notes 1. 6.0 MHz and 6.29 MHz can not be used together for the IEBus system clock frequency 2. Although the system clock specified in the IEBus specification is 6.0 MHz, operation is guaranteed at 6.29 MHz system clock in the V850/SB2. Regulator (TA = –40 to +85°°°°C, VDD = 4.0 to 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output stabilization time t REG Stabilization capacitance C = 1 µF (Connected to REGC pin) 1m s Cautions 1. Be sure to start inputting supply voltage V DD when RESET = V SS = EVSS = BVSS = 0 V (the above state), and make RESET high level after the tREG period has elapsed. 2. If supply voltage BV DD or EV DD is input before the t REG period has elapsed following the input of supply voltage V DD, note that data may be driven from the pins until the t REG period has elapsed because the I/O buffers’ power supply was turned on while the circuit was in an undefined state.

Data Sheet U14780EJ2V1DS 43 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY

3.1 Flash Memory Programming Mode ( µµµµPD70F3035A, 70F3035AY only)

Write/erase characteristics (TA = 10 to 85°°°°C … I, K, E rank product, TA = −−−−20 to +85°°°°C … P rank product, VDD = AVDD = BVDD = EVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VPP power supply voltage V PP2 During flash memory programming 7.5 7.8 8.1 V VDD power supply current I DD When VPP = VPP2, fXX = 13 MHz 51 mA VPP power supply current I PP VPP = VPP2 100 mA Step erase time t ER Note 1 0.2 s Overall erase time per area t ERA When the step erase time = 0.2 s, Note 2 20 s/area Write-back time t WB Note 3 1m s Number of write-backs per write-back command CWB When the write-back time = 1 ms, Note 4

300 Count/write-

Number of erase/write-backs C ERWB 16 Count Step writing time t WR Note 5 20 µs Overall writing time per word t WRW When the step writing time = 20 µs (1 word = 4 bytes), Note 6 20 200 µs/word Number of rewrites per area C ERWR 1 erase + 1 write after erase = 1 rewrite, Note 7 Note 8 Count/area Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. The recommended setting value of the write-back time is 1 ms. 4. Write-back is executed once by the issuance of the write-back command. Therefore, the retry count must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step writing time is 20 µs. 6. 20 µs is added to the actual writing time per word. The internal verify time during and after the writing is not included. 7. When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and “write only”. Example (P: Write, E: Erase) Shipped product → P → E → P → E → P: 3 rewrites Shipped product → E → P → E → P → E → P: 3 rewrites 8. I, K, E rank product: 20 writes/area P rank product: 100 writes/area Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 000000H to 01FFFFH Area 1 = 020000H to 03FFFFH

Data Sheet U14780EJ2V1DS44 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 4. PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 16.00 ±0.20 14.00 ±0.20 0.50 (T.P.) 1.00 J 16.00 ±0.20 K C 14.00 ±0.20 I 0.08 1.00 ±0.20 L 0.50 ±0.20 F 1.00 N P Q 0.08 1.40 ±0.05 0.10 ±0.05 S100GC-50-8EU, 8EA-2 S 1.60 MAX. H 0.22 +0.05 −0.04 M 0.17 +0.03 −0.07 R3 °+7° −3° 1 25 100 75 51 S SN J detail of lead end C D A B R K M L P I S Q G F MH

Data Sheet U14780EJ2V1DS 45 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 8081 50 1001 100-PIN PLASTIC QFP (14x20) HI J detail of lead end M Q R K M L P S SN G F NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 23.6 ±0.4 20.0 ±0.2 0.30 ±0.10 0.6 H 17.6 ±0.4 I C 14.0 ±0.2 0.15 J 0.65 (T.P.) K 1.8 ±0.2 L 0.8 ±0.2 F 0.8 P100GF-65-3BA1-4 N P Q 0.10 2.7 ±0.1 0.1 ±0.1 R5 °±5° S 3.0 MAX. M 0.15 +0.10 −0.05 C D A B S

Data Sheet U14780EJ2V1DS46 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY 5. RECOMMENDED SOLDERING CONDITIONS The µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 5-1. Surface Mounting Type Soldering Conditions (1/2) (1) µµµµPD703034AGC-××××××××××××-8EU: 100-pin plastic LQFP (fine pitch) (14 ×××× 14) µµµµPD703034AYGC-××××××××××××-8EU: 100-pin plastic LQFP (fine pitch) (14 ×××× 14) µµµµPD703035AGC-××××××××××××-8EU: 100-pin plastic LQFP (fine pitch) (14 ×××× 14) µµµµPD703035AYGC-××××××××××××-8EU: 100-pin plastic LQFP (fine pitch) (14 ×××× 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less Exposure limit: 7 days Note (after that, prebake at 125°C for 10 to 72 hours) IR35-107-2 Count: Two times or less Exposure limit: 7 days Note (after that, prebake at 125°C for 10 to 72 hours) VP15-107-2 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). (2) µµµµPD70F3035AGC-8EU: 100-pin plastic LQFP (fine pitch) (14 ×××× 14) µµµµPD70F3035AYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 ×××× 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less Exposure limit: 3 days Note (after that, prebake at 125°C for 10 to 72 hours) IR35-103-2 Count: Two times or less Exposure limit: 3 days Note (after that, prebake at 125°C for 10 to 72 hours) VP15-103-2 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14780EJ2V1DS 47 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Table 5-1. Surface Mounting Type Soldering Conditions (2/2) µµµµPD70F3035AGF-3BA: 100-pin plastic QFP (14 ×××× 20) µµµµPD70F3035AYGF-3BA: 100-pin plastic QFP (14 ×××× 20) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less Exposure limit: 7 days Note (after that, prebake at 125°C for 20 to 72 hours) IR35-207-2 Count: Two times or less Exposure limit: 7 days Note (after that, prebake at 125°C for 20 to 72 hours) VP15-207-2 Wave soldering Solder bath temperature: 260 °C max., Time: 10 seconds max., Count: Once Preheating temperature: 120°C max. (package surface temperature) Exposure limit: 7 days Note (after that, prebake at 125°C for 20 to 72 hours) WS60-207-1 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14780EJ2V1DS48 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY APPENDIX NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system as shown below. Appendix-1. 100-pin Plastic LQFP (Fine Pitch) (14 ×××× 14) Side view Target system NQPACK100SD YQPACK100SD 178 mm Note In-circuit emulator option board Conversion connector IE-703037-MC-EM1 In-circuit emulator IE-703002-MC YQGUIDE Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm). Top view Target system YQPACK100SD, NQPACK100SD, YQGUIDE IE-703037-MC-EM1 IE-703002-MC Pin 1 position Connection condition diagram 13.3 mm 25.4 mm 21.58 mm 17.78 mm 75 mm 31.84 mm Target system NQPACK100SD YQPACK100SD IE-703037-MC-EM1 Connection condition diagram Connect to IE-703002-MC. YQGUIDE Pin 1 position

Data Sheet U14780EJ2V1DS 49 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Appendix-2. 100-pin Plastic QFP (14 ×××× 20) Side view Target system NQPACK100RB YQPACK100RB NEXB-100-SD/RB 178 mm Note In-circuit emulator option board Conversion connector IE-703037-MC-EM1 In-circuit emulator IE-703002-MC YQGUIDE Note YQSOCKET100SDN (included with IE-703002-MC) to this portion for adjusting the height (height: 3.2 mm). Top view Target system YQPACK100RB, NQPACK100RB, YQGUIDE IE-703037-MC-EM1 IE-703002-MC NEXB-100-SD/RB 8 mm 20 mm Pin 1 position Connection condition diagram 33.2 mm 28 mm 18.5 mm 20 mm 38 mm Target system NQPACK100RB YQPACK100RB IE-703037-MC-EM1Connection condition diagram Connect to IE-703002-MC. NEXB-100-SD/RB 75 mm Pin 1 position

Data Sheet U14780EJ2V1DS50 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Caution Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. Related document µPD703037A, 703037AY, 70F3037A, 70F3037AY Data Sheet (U14894E) The related documents in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850/SB1, V850/SB2, V850 Family, and IEBus are trademarks of NEC Corporation.

Data Sheet U14780EJ2V1DS 51 µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 NEC Electronics (France) S.A. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2

µµµµPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: µPD70F3035A, 70F3035AY The customer must judge the need for license: µPD703034A, 703034AY, 703035A, 703035AY M8E 00. 4 The information in this document is current as of December, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": T ransportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).