U631H16D1K45

U631H16 ETC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

Features

/G70 H igh-perform ance CM O S non- volatile static R A M 2048 x 8 bits /G70 25, 35 and 45 ns Access Tim es /G70 12, 20 and 25 ns Ou tput Enable A ccess Tim es /G70 S oftw are STOR E Initiation (STORE Cycle Tim e < 10 m s) /G70 A utom atic STORE Tim ing /G70 105 STOR E cycles to E EPROM /G70 10 years data retention in E EPROM /G70 A utom atic RECA LL on Pow er Up /G70 S oftw are RE C ALL Initiation (REC ALL C ycle Tim e < 20 µs) /G70 U nlim ited RECA LL cycles from E EPROM /G70 U nlimited R ead and W rite to SRAM /G70 S ingle 5 V ± 10 % O peration /G70 O perating tem perature ranges: 0 to 70 °C -40 to 85 °C /G70 C ECC 90000 Qu ality Standard /G70 E SD characterization according /G70 M IL STD 883C M 3015.7-HB M (classification see IC Code N um bers) Pin Co nfiguration Pin D escription Top View 1n.c. VC C28 2n.c. W27 4A6 A825 5A5 A924 3A7 n.c.26 6A4 n.c.23 7A3 G22 8A2 A1021 12DQ1 DQ517 9A1 E20 10A0 DQ719 11DQ0 DQ618 13DQ2 DQ416 14VSS D Q 315 PDIP S ignal N ame Signal De scription A0 - A10 Address Inputs DQ 0 - D Q 7 Da ta In/Out E C hip Enable G Output Enable W Write Enable VCC Power Supply Voltage VSS Ground SOP Top View 2A6 A823 3A5 A922 1A7 VC C24 4A4 W21 5A3 G20 6A2 A1019 10DQ1 DQ 515 7A1 E18 8A0 DQ717 9DQ0 DQ 616 11DQ2 DQ 414 12VSS D Q 313 S O P

2 Decem ber 12, 1997

32 x (64 x 8) STO R E R E C A LLSR AM Array

32 R ow s x

G E W A0 A1 A 2 A3 A4A10 Software D etect A0 - A10 Input Buffers O perating M ode E W G D Q 0 - D Q 7 S tandby/not selected H ** High-Z Internal Read L H H High-Z Read L H L Data O utputs Low -Z Wr ite L L * Data Inputs High-Z Truth Table for SR A M O perations B lock Diagram a: Stresses greater than those listed under „A bsolute M aximum R atings“ m ay cause permanent dam age to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. E xposure to absolute maximum rating conditions for extended periods may affect reliability. A bsolute Maxim um Ratingsa Sym bol M in. M ax. U nit Pow er Supply Voltage VCC -0.5 7 V Input Voltage VI -0.3 VCC +0.5 V Ou tput Voltage VO -0.3 VCC +0.5 V Pow er Dissipation PD 1W Op erating Tem perature C -Type K-Type Ta -40 Storage Tem perature T stg -65 150 °C Ch aracteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the pow er supply voltage range and in the operating tem perature range specified. D ynamic m easurem ents are based on a rise and fall tim e of ≤ 5 ns, measured betw een 10 % and 90 % of VI, as w ell as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V , w ith the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 m V from steady-state voltage. *H o r L

3Decem ber 12, 1997 U631H16 b: IC C 1 and IC C 3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current IC C 1 is measured for W R ITE /R EAD - ratio of 1/2. c: IC C 2 is the average current required for the duration of the STO RE cycle (S TO RE C ycle Tim e). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. S ee M O DE S ELEC TIO N table. The current IC C(S B)1 is measured for WR ITE /R EA D - ratio of 1/2. DC Ch aracteristics Sym bol Co nditions C-Type K-Type U nit M in. M ax. M in. M ax. O perating Supply C urrentb ICC 1 VCC VIL VIH tc tc tc = 5.5 V = 0.8 V = 2.2 V = 25 ns = 35 ns = 45 ns mA mA mA Average S upply Current during STO R E c ICC 2 VCC E W VIL VIH = 5.5 V ≥ VCC -0.2 V ≥ VCC -0.2 V ≤ 0.2 V ≥ VCC -0.2 V 6 7 m A Standby Supply C urrentd (Cycling TTL Input Levels) ICC(SB)1 VCC E tc tc tc = 5.5 V ≥ VIH = 25 ns = 35 ns = 45 ns mA mA mA Average S upply Current at t cR = 200 nsb (Cycling C M OS Input Levels) ICC 3 VCC W VIL VIH = 5.5 V ≥ VCC -0.2 V ≤ 0.2 V ≥ VCC -0.2 V 15 15 mA Standby Supply C urrentd (Stable CM O S Input Levels) IC C(SB) VCC E VIL VIH = 5.5 V ≥ VCC -0.2 V ≤ 0.2 V ≥ VCC -0.2 V 1 1 m A R ecom m ended O peration C onditions Sym bol Con ditions M in. M ax. U nit P ow er Supply Voltage VCC 4.5 5.5 V Input Low Voltage V IL -2 V at Pulse W idth 10 ns perm itted -0.3 0.8 V Input High Voltage V IH 2.2 VCC +0.3 V

4 Decem ber 12, 1997

SR A M M E M O R Y OP ER ATIO N S e: Param eter guaranteed but not tested. f: D evice is continuously selected with E and G both LO W . g: Address valid prior to or at the sam e time with E transition LO W . h: M easured ± 200 m V from steady state output voltage. D C Characteristics Sym bol Con ditions C-Type K-Type U nit M in. Ma x. M in. Ma x. O utput High Voltage O utput Low Voltage VOH VOL VCC IOH IOL = 4.5 V =-4 m A = 8 mA 2.4 0.4 2.4 0.4 V V O utput High Current O utput Low Current I OH IOL VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V 8 -4 m A mA Input Leakage Cu rrent High Low IIH IIL VCC VIH VIL = 5.5 V = 5.5 V = 0 V -1 1 µA µA O utput Leakage Current High at Three-S tate- O utput Low at Three-S tate- O utput IO H Z IO LZ VCC VOH VOL = 5.5 V = 5.5 V = 0 V -1 1 µA µA No. Sw itching Characteristics R ead Cycle Sym bol 25 35 45 U nit

1 Read Cycle Tim ef tAVAV tcR 25 35 45 ns

2 Address Access Tim e to D ata Validg tAV Q V ta(A ) 25 35 45 ns

3 C hip Enable Access Tim e to Data Valid tELQV ta(E) 25 35 45 ns

4 O utput Enable Access Tim e to D ata Valid tGLQV ta(G) 12 20 25 ns

5E HIGH to O utput in High-Zh tEH Q Z tdis(E) 13 17 20 ns 6G HIGH to Output in High-Zh tGHQZ tdis(G) 13 17 20 ns 7E LO W to Output in Low -Z tELQX ten(E) 55 5 ns 8G LO W to Output in Low-Z tGLQX ten(G ) 00 0 ns 9 O utput Hold Tim e after A ddr. C hangeg tAX Q X tv(A ) 33 3 ns

19 C hip Enable to Pow er Activee tELICC H 00 0 ns

11 C hip Disable to P ow er Standbyd, e tEH ICC L 25 35 45 ns

5Decem ber 12, 1997 U631H16 tPU R ead C ycle 1: A i-controlled (during Read cycle: E = G = VIL, W = VIH)f R ead Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g No. Sw itching Characteristics Write C ycle Sym bol 25 35 45 Unit

12 W rite Cycle Tim e tAVAV tAVAV tcW 25 35 45 ns

13 W rite Pulse W idth tW LW H tw (W ) 20 30 35 ns

14 W rite Pulse W idth Setup Tim e tW LEH tsu(W ) 20 30 35 ns

15 Address Setup Tim e tAVW L tAV EL tsu(A ) 00 0 ns

16 Address Valid to End of Write tAVW H tAV EH tsu(A -WH) 20 30 35 ns

17 Ch ip Enable S etup Tim e tELW H tsu(E) 20 30 35 ns

18 Ch ip Enable to End of W rite tELEH tw(E) 20 30 35 ns

19 Data S etup Tim e to End of W rite tD VW H tDV EH tsu(D ) 12 18 20 ns

20 Data Hold Tim e after End of W rite tWH D X tEH D X th(D ) 00 0 ns

21 Address Hold after End of W rite tWH A X tEH A X th(A ) 00 0 ns

22 W LO W to Output in High-Zh, i tWLQZ tdis(W) 10 13 15 ns

23 W H IGH to Output in Low -Z tW H QX ten(W ) 55 5 ns

E G DQi O utput tdis(E) tcR ta(E) ten(E) ten(G ) ta(G ) tdis(G) Address Valid O utput Data Valid High Imp edance ICC ACT IVE STAND B Y tPD ta(A ) ta(A ) Previous D ata Valid O utput Data Valid tcR Address Valid tv(A) Ai DQi O utput AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA

6 Decem ber 12, 1997

A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA A AAA A AAA A AAAA AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A L- to H-level undefined H- to L-level i: If W is LO W and w hen E goes LO W , the outputs rem ain in the high impedance state. j: E or W must be > VIH during address transitions. Write Cycle #1: W -controlledj Wr ite Cycle #2: E-controlledj th(D ) Ai E W DQi Input DQi O utput tcW tsu(E) th(A ) tw(W ) tsu(D) tdis(W) ten(W) Address Valid Input D ata Valid High Imped ance tsu(A -W H ) 19 20 tsu(A ) th(D ) Ai E W DQi Input DQi O utput tcW tw (E) th(A) tsu(D ) Input Data Valid tsu(W ) 2019 Previous Data tsu(A ) Add ress Valid AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A

7Decem ber 12, 1997 U631H16 N O N VO LATILE M E M O R Y O P ER ATIO N S k: tR ES TO R E starts from the time V CC rises above VSW ITC H . STO R E C YCLE IN H IB IT and AUT O M ATIC PO W E R U P R E C A LL SO FTW AR E M O DE SE LEC TIO N l: The six consecutive addresses m ust be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a S tore cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a R E C A LL cycle. W m ust be high during all six consecutive cycles. S ee S TO RE cycle and RE C A LL cycle tables and diagram s for further details. The follow ing six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C. m : I/O state assum es that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G . No. STO R E CYC LE IN H IB IT and AU TO M ATIC PO WER UP R E C A LL Sym bol M in. Ma x. U nit A lt. IE C

24 Pow er Up RECA LL Durationk, e tRES TO R E 650 µs

Low Voltage Trigger Level VSWI TCH 4.0 4.5 V E W A 10 - A 0 (hex) Mo de I/O Pow er N otes LH 000 555 2AA 7FF 0F0 70F Read SR AM Read SR AM Read SR AM Read SR AM Read SR AM Nonvolatile STO R E Output D ata Output D ata Output D ata Output D ata Output D ata Ou tput High Z Active ICC 2 l, m l, m l, m l, m l, m l LH 000 555 2AA 7FF 0F0 70E Read SR AM Read SR AM Read SR AM Read SR AM Read SR AM Nonvolatile REC A LL Output D ata Output D ata Output D ata Output D ata Output D ata Ou tput High Z Active l, m l, m l, m l, m l, m l A A A A AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA VCC 5.0 V STO R E inhibit Pow er Up VSWI TCH tRESTORE RECA LL t

8 Decem ber 12, 1997

n: The software sequence is clocked with E controlled R EA D s. o: O nce the software controlled S TO RE or RE C A LL cycle is initiated, it completes autom atically, ignoring all inputs. p: N ote that S TO R E cycles (but not R E C A LL) are aborted by V CC < VS W ITCH (S TO R E inhibit). q: An autom atic RE C A LL also takes place at pow er up, starting w hen V CC exceeds VSW ITC H and takes tR ES TO R E . VCC m ust not drop below VS W ITCH once it has been exceeded for the R E C A LL to function properly. r: N oise on the E pin may trigger m ultiple R E AD cycles from the sam e address and abort the address sequence. s: If the C hip Enable P ulse W idth is less than ta(E ) (see R ead Cycle) but greater than or equal tw (E)S R , than the data m ay not be valid at the end of the low pulse, how ever the ST O RE or R EC ALL will still be initiated. No . Softw are Co ntrolled ST O RE/REC A LL C yclel, n Sym bol 25 35 45 U nit

25 STORE/REC A LL Initiation Tim e tAVAV tcR 25 35 45 ns

26 Ch ip E nable to O utput Inactiveo tELQZ tdis(E)SR 600 600 600 ns

27 STORE C ycle Tim ep tELQ X S td(E)S 10 10 10 ms

28 RECA LL Cycle Tim eq tELQ XR td(E)R 20 20 20 µs

29 Address Setup to C hip Enabler tAVELN tsu(A)SR 00 0 ns

30 Ch ip Enable Pulse W idthr, s tELE H N tw (E)SR 20 25 35 ns

31 Ch ip D isable to Address C hanger tEH A XN th(A)SR 00 0 ns

t: W m ust be HIG H when E is LO W during the address sequence in order to initiate a nonvolatile cycle. G m ay be either H IG H or LOW throughout. Addresses 1 through 6 are found in the m ode selection table. A ddress 6 determines w hether the U 631H 16 perform s a S TO R E or RE C A LL. u: E must be used to clock in the address sequence for the Software controlled S TO RE and RE C A LL cycles. AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA Ai E DQi O utput tcR ADDR E SS 1 VALID VALID SO FTW ARE C O NTR O LLE D STORE/R E C A LL C YCLE r, s, t, u (E = H IGH after STO RE initiation) AD DR E SS 6 25 25 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Ai E DQi O utput tcR tw(E )SR ADDR E SS 1 VALID VALID ADD R ES S 6 td(E )S / td(E)R 27 28/ th(A )SR tsu(A)S R tdis(E )SR th(A )SR tsu(A )SR tw (E)S R th(A)SR tsu(A )SR 29 5 tdis(E) SO FTW ARE C O NT R O LLED STO RE/REC A LL C YCLE r, s, t, u (E = LO W after S TO R E initiation) tdis(E)SR AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA td(E)S / td(E)R 27 28/ tcR AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA tw (E)SR th(A)S R tsu(A)S R AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA High Imp edance High Imp edance

9Decem ber 12, 1997 U631H16 All pins not under test m ust be connected w ith ground by capacitors. C apacitancee Co nditions Sym bol M in. M ax. U nit Input Capacitance VCC VI f Ta = 5.0 V = VSS = 1M H z = 25 °C C I 8 pF O utput Capacitance C O 7 pF Test Configuration for Functional Check VIH VIL VSS VCC w 480 255 30 pF v V O Sim ultaneous measure- m ent of all 8 output pins Input level according to the relevant test measurem ent D Q 0 D Q 1 D Q 2 D Q 3 D Q 4 D Q 5 D Q 6 D Q 7 v: In m easurem ent of tdis-times and ten-times the capacitance is 5 pF. w : Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances. A 10 E W G 5 V IC Code N umb ers Type Package A ccess Time D = PD IP28 (300 m il) 25 = 25 ns D 1= P DIP28 (600 m il) 35 = 35 ns (on special request) S = SO P 28 (300 m il) 45 = 45 ns (on special request) S1= SO P 24 (300 m il) O perating Tem perature R ange The date of m anufacture is given by the last 4 digits of the m ark, the first 2 digits indicating the year, and the last 2 digits the calendar w eek. x: E SD protection > 2000 V under developm ent B ESD Class blank > 2000 Vx B > 1000 V E xam ple DU 631H 16 25C C = 0 to 70 °C K = -40 to 85 °C

10 Decem ber 12, 1997

The U6 31H 16 has tw o separate m odes of operation: SRAM m ode and nonvolatile m ode. In SRAM m ode, the m em ory operates as a standard fast static RAM . In nonvolatile m ode, data is transferred from SR A M to EEPROM (the STORE operation) or from EE P ROM to SRAM (the REC A LL operation). In this m ode SRAM functions are disabled. SR A M RE A D The U 631H16 perform s a REA D cycle w henever E and G are LO W w hile W is HIGH. The address specified on pins A 0 - A10 determ ines which of the 2048 data bytes w ill be accessed. W hen the R E AD is initiated by an address transition, the outputs w ill be valid after a delay of tcR. If the READ is initiated by E or G , the outputs w ill be valid at ta(E) or at ta(G ), w hichever is later. The data outputs w ill repeatedly respond to address changes w ithin the tcR access tim e w ithout the need for transition on any control input pins, and w ill rem ain valid until another address change or until E or G is brought HIGH or W is brought LO W . SR A M WR ITE A W RITE cycle is performed w henever E and W are LO W . The address inputs m ust be stable prior to entering the W RITE cycle and m ust rem ain stable until ei-ther E or W goes H IGH at the end of the cycle. The data on pins D Q 0 - 7 w ill be w ritten into the m em ory if it is valid tsu(D ) before the end of a W controlled W RITE or tsu(D ) before the end of an E controlled W RITE . It is recom m ended that G is kept H IG H during the entire W RITE cycle to avoid data bus contention on the com m on I/O lines. If G is left LO W , internal circuitry w ill turn off the output buffers tdis(W ) after W goes LOW . N O ISE C O N SID ER ATIO N The U 631H1 6 is a high speed m em ory and therefore it m ust have a high frequency bypass capacitor of appro- xim ately 0.1 µF connected betwe en VCC and VSS using leads and traces that are as short as possible. As w ith all high speed C MO S ICs, normal carefull routing of pow er, ground and signals w ill help prevent noise pro- blem s. SO FTW A RE N ON VO LATILE STORE The U6 31H 16 softw are controlled STORE cycle is initiated by executing sequential R E AD cycles from six specific address locations. By relying on RE AD cycles only, the U6 31H 16 im plem ents nonvolatile operation w hile rem aining com patible w ith standard 2K x 8 SRA M s. During the STOR E cycle, an erase of the pre- vious nonvolatile data is first perform ed, follow ed by parallel program m ing of all nonvolatile elem ents. O nce a STOR E cycle is initiated, further inputs and outputs are disabled until the cycle is com pleted. B ecause a sequence of addresses is used for STOR E initiation, it is im portant that no other READ or WRITE accesses intervene in the sequence or the sequence w ill be aborted and no STORE or RECA LL will take place. To initiate the STORE c ycle the follow ing READ sequence m ust be perform ed: 1. Read address 000 (hex) Valid R E AD 2. Read address 555 (hex) Valid R E AD 3. Read address 2AA (hex) Valid R E AD 4. Read address 7FF (hex) Valid R E AD 5. Read address 0F0 (hex) Valid R E AD 6. Read address 70F (hex) Initiate STO R E O nce the sixth address in the sequence has been entered, the S TOR E cycle will com m ence and the chip w ill be disabled. It is im portant that RE A D cycles and not W R ITE cycles are used in the sequence. It is not necessary that G is LO W for the sequence to be valid. A fter the tST O R E cycle tim e has been fulfilled, the SRAM w ill again be activated for READ and WR ITE opera- tion. S O FTW A R E N O N VO LATILE REC A LL A R E CALL cycle of the EEPROM data into the SRAM is initiated with a sequence of REA D operations in a m anner sim ilar to the STORE initiation. To initiate the R E CALL cycle the follow ing sequence of READ opera- tions m ust be perform ed: 1. Read address 000 (hex) Valid R E AD 2. Read address 555 (hex) Valid R E AD 3. Read address 2AA (hex) Valid R E AD 4. Read address 7FF (hex) Valid R E AD 5. Read address 0F0 (hex) Valid R E AD 6. Read address 70E (hex) Initiate RECA LL Internally, RE CALL is a tw o step procedure. First, the S RA M data is cleared and second, the nonvolatile inform ation is transferred into the S RAM c ells. The R E CALL operation in no way alters the data in the E EPROM cells. The nonvolatile data can be recalled an unlim ited numb er of tim es. A U TO M ATIC P O WE R UP REC A LL O n pow er up, once VCC exceeds the sense voltage of V SW ITC H , a RECA LL cycle is autom atically initiated. The voltage on the VCC pin m ust not frop belw o V SW ITC H once it has risen above it in order for the RECA LL to operate properly. D ue to this autom atic REC A LL, S RA M operation cannot com m ence until tRESTORE after V CC exceeds VSWI TCH .

11Decem ber 12, 1997 U631H16 If the U6 31H 16 is in a W R ITE state at the end of pow er up RECA LL, the S RAM data w ill be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected betw een W and VC C . HA R D W ARE P R O TE C TIO N The U6 31H 16 offers hardw are protection against inad- vertent STOR E operation through VCC sense. For VCC < V SW ITC H the softw are initiated STOR E opera- tion w ill be inhibited. LO W AVER A GE A C TIV E P O W ER The U6 31H 16 has been designed to draw significantly less pow er w hen E is LO W (chip enabled) but the access cycle tim e is longer than 55 ns. W hen E is HIG H the chip consum es only standby cur- rent. The overall average current draw n by the part depends on the follow ing item s: 1. C M OS or TTL input levels 2. the time during w hich the chip is disabled (E HIG H) 3. the cycle tim e for accesses (E LOW ) 4. the ratio of READ s to W RITE s 5. the operating tem perature 6. the VCC level

ZM D products are not designed, intended, or authorized for use as components in systems intend for surgical im plant into the body, or other applications intended to support or sustain life, or for any other application in w hich the failure of the ZM D product could create a situation where personal injury or death m ay occur. Co m ponents used in life-support devices or systems must be expressly authorized by ZM D for such purpose. The inform ation describes the type of com ponent and shall not be considered as assured characteristics. Term s of delivery and rights to change design reserved. Memory Products 1998 SoftStore 2K x 8 nvSRAM U631H16 Zentrum M ikroelektronik D resden G m bH Grenzstraße 28 • D-01109 D resden • P. O. B. 80 01 34 • D -01101 D resden • Germ any Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Em ail: sales@ zmd .de Internet W eb Site: http://w w w .zmd.de