U631H16 SIMTEK | Alldatasheet
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Technical content
Obsolete - Not Recommended for New Designs
1 March 31, 2006
STK Control #ML0042 Rev 1.0 SimtekSoftStore 2K x 8 nvSRAM The U631H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disab- led. The U631H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resi- des in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE opera- tion), or from the EEPROM to the SRAM (the RECALL ) operation) are initiated through software sequences. The U631H16 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola- tile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
- High-performance CMOS nonvola- tile static RAM 2048 x 8 bits
- 25, 35 and 45 ns Access Times
- 12, 20 and 25 ns Output Enable Access Times
- Software STORE Initiation (STORE Cycle Time < 10 ms)
- Automatic STORE Timing
- 106 STORE cycles to EEPROM
- 100 years data retention in EEPROM
- Automatic RECALL on Power Up
- Software RECALL Initiation (RECALL Cycle Time < 20 μs)
- Unlimited RECALL cycles from EEPROM
- Unlimited Read and Write to SRAM
- Single 5 V ± 10 % Operation
- Operating temperature ranges: 0 to 70 °C -40 to 85 °C
- QS 9000 Quality Standard
- ESD protection > 2000 V (MIL STD 883C M3015.7-HBM)
- RoHS compliance and Pb- free
- Packages: PDIP28 (600 mil) SOP24 (300 mil) Pin Configuration Pin Description Top View 1n.c. VCC28 2n.c. W27 4A6 A825 5A5 A924 3A7 n.c.26 6A4 n.c.23 7A3 G22 8A2 A1021 12DQ1 DQ517 9A1 E20 10A0 DQ719 11DQ0 DQ618 13DQ2 DQ416 14VSS DQ315 PDIP Signal Name Signal Description A0 - A10 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W Write Enable VCC Power Supply Voltage VSS Ground Top View 2A6 A823 3A5 A922 1A7 VCC24 4A4 W21 5A3 G20 6A2 A1019 10DQ1 DQ515 7A1 E18 8A0 DQ717 9DQ0 DQ616 11DQ2 DQ414 12VSS DQ313 SOP Features Description
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STK Control #ML0042 Rev 1.0 Operating Mode E W G DQ0 - DQ7 Standby/not selected H ** High-Z Internal Read L H H High-Z Read L H L Data Outputs Low-Z Write L L * Data Inputs High-Z Block Diagram Truth Table for SRAM Operations * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply vo ltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. a: Stresses greater than those listed under „A bsolute Maximum Ratings“ may cause permanent damage to the device. This is a stres s rating only, and functional operation of the device at condition above those indicated in the operational sections of this spec ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum Ratingsa Symbol Min. Max. Unit Power Supply Voltage V CC -0.5 7 V Input Voltage V I -0.3 V CC+0.5 V Output Voltage V O -0.3 V CC+0.5 V Power Dissipation P D 1W Operating Temperature C-Type K-Type Ta -40 Storage Temperature T stg -65 150 °C EEPROM Array 32 x (64 x 8) STORE RECALLSRAM Array
32 Rows x
G E W Software Detect A0 - A10 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Column I/O Column Decoder A0 A1 A2 A3 A4A10 Input Buffers
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STK Control #ML0042 Rev 1.0 DC Characteristics Symbol Conditions C-Type K-Type Unit Min. Max. Min. Max. Operating Supply Currentb ICC1 VCC VIL VIH tc tc tc = 5.5 V = 0.8 V = 2.2 V = 25 ns = 35 ns = 45 ns mA mA mA Average Supply Current during STORE c ICC2 VCC E W VIL VIH = 5.5 V ≥ V CC-0.2 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 67 m A Standby Supply Currentd (Cycling TTL Input Levels) ICC(SB)1 VCC E tc tc tc = 5.5 V ≥ VIH = 25 ns = 35 ns = 45 ns mA mA mA Average Supply Current at t cR = 200 nsb (Cycling CMOS Input Levels) ICC3 VCC W VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 15 15 mA Standby Supply Currentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 11 m A Recommended Operation Conditions Symbol Conditions Min. Max. Unit Power Supply Voltage V CC 4.5 5.5 V Input Low Voltage V IL -2 V at Pulse Width 10 ns permitted -0.3 0.8 V Input High Voltage V IH 2.2 V CC+0.3 V b: I CC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: I CC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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STK Control #ML0042 Rev 1.0 DC Characteristics Symbol Conditions C-Type K-Type Unit Min. Max. Min. Max. Output High Voltage Output Low Voltage VOH VOL VCC IOH IOL = 4.5 V =-4 mA = 8 mA 2.4 0.4 2.4 0.4 V V Output High Current Output Low Current I OH IOL VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V 8 -4 mA mA Input Leakage Current High Low I IH IIL VCC VIH VIL = 5.5 V = 5.5 V = 0 V - 1 1 μA μA Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ VCC VOH VOL = 5.5 V = 5.5 V = 0 V - 1 1 μA μA SRAM Memory Operations No. Switching Characteristics Read Cycle Symbol 25 35 45 Unit
1 Read Cycle Time f tAVAV tcR 25 35 45 ns
2 Address Access Time to Data Valid g tAVQV ta(A) 25 35 45 ns
3 Chip Enable Access Time to Data Valid t ELQV ta(E) 25 35 45 ns
4 Output Enable Access Time to Data Valid t GLQV ta(G) 12 20 25 ns
5E HIGH to Output in High-Zh tEHQZ tdis(E) 13 17 20 ns 6G HIGH to Output in High-Zh tGHQZ tdis(G) 13 17 20 ns 7E LOW to Output in Low-Z t ELQX ten(E) 555n s 8G LOW to Output in Low-Z t GLQX ten(G) 000n s 9 Output Hold Time after Addr. Change g tAXQX tv(A) 333n s
10 Chip Enable to Power Active e tELICCH 000n s
11 Chip Disable to Power Standby d, e tEHICCL 25 35 45 ns
e: Parameter guaranteed but not tested. f: Device is continuously selected with E and G both LOW. g: Address valid prior to or at the same time with E transition LOW. h: Measured ± 200 mV from steady state output voltage.
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STK Control #ML0042 Rev 1.0 tPU (10) Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g No. Switching Characteristics Write Cycle Symbol 25 35 45 Unit
12 Write Cycle Time t AVAV tAVAV tcW 25 35 45 ns
13 Write Pulse Width t WLWH tw(W) 20 30 35 ns
14 Write Pulse Width Setup Time t WLEH tsu(W) 20 30 35 ns
15 Address Setup Time t AVWL tAVEL tsu(A) 000 n s
16 Address Valid to End of Write t AVWH tAVEH tsu(A-WH) 20 30 35 ns
17 Chip Enable Setup Time t ELWH tsu(E) 20 30 35 ns
18 Chip Enable to End of Write t ELEH tw(E) 20 30 35 ns
19 Data Setup Time to End of Write t DVWH tDVEH tsu(D) 12 18 20 ns
20 Data Hold Time after End of Write t WHDX tEHDX th(D) 000 n s
21 Address Hold after End of Write t WHAX tEHAX th(A) 000 n s
22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 10 13 15 ns
23 W HIGH to Output in Low-Z t WHQX ten(W) 555 n s
E G DQi Output tdis(E) tcR ta(E) ten(E) ten(G) ta(G) tdis(G) Address Valid Output Data ValidHigh Impedance ICC ACTIVE STANDBY tPD (1) (3) (4) (5) (7) (6) (8) (11)ta(A) (2) ta(A) Previous Data Valid Output Data Valid tcR Address Valid tv(A) Ai DQi Output (1) (2) (9)
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STK Control #ML0042 Rev 1.0 High Impedance L- to H-level undefined H- to L-level i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state. j: E or W must be > VIH during address transitions. Write Cycle #1: W-controlledj Write Cycle #2: E-controlledj th(D) Ai E W DQi Input DQi Output tcW tsu(E) th(A) tw(W) tsu(D) tdis(W) ten(W) Address Valid Input Data Valid High Impedance tsu(A-WH) (12) (16) (13) (19) (20) (23) (21) tsu(A) th(D) Ai E W DQi Input DQi Output tcW tw(E) th(A) tsu(D) Input Data Valid tsu(W) (12) (18) (21) (20)(19) (17) (22) Previous Data Valid (15) (14) (15)tsu(A) Address Valid
7 March 31, 2006
STK Control #ML0042 Rev 1.0 Nonvolatile Memory Operations k: t RESTORE starts from the time VCC rises above VSWITCH. No. STORE Cycle Inhibit and Automatic Power Up RECALL Symbol Min. Max. Unit Alt. IEC
24 Power Up RECALL Duration k, e tRESTORE 650 μs
Low Voltage Trigger Level V SWITCH 4.0 4.5 V STORE Cycle Inhibit and Automatic Power Up RECALL (24) tRESTORE VCC 5.0 V STORE inhibit Power Up VSWITCH RECALL t Software Mode Selection E W A10 - A0 (hex) Mode I/O Power Notes LH 0 0 0 555 2AA 7FF 0F0 70F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z Active I CC2 l, m l, m l, m l, m l, m l LH 0 0 0 555 2AA 7FF 0F0 70E Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active l, m l, m l, m l, m l, m l l: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purpos es and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C. m: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G .
8 March 31, 2006
STK Control #ML0042 Rev 1.0 n: The software sequence is clocked with E controlled READs. o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. p: Note that STORE cycles (but not RECALL) are aborted by V CC < VSWITCH (STORE inhibit). q: An automatic RECALL also takes place at power up, starting when V CC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for t he RECALL to function properly. r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. s: If the Chip Enable Pulse Width is less than t a(E) (see Read Cycle) but greater than or equal t w(E)SR, than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. No. Software Controlled STORE/RECALL Cyclel, n Symbol 25 35 45 Unit
25 STORE/RECALL Initiation Time t AVAV tcR 25 35 45 ns
26 Chip Enable to Output Inactive o tELQZ tdis(E)SR 600 600 600 ns
27 STORE Cycle Time p tELQXS td(E)S 10 10 10 ms
28 RECALL Cycle Time q tELQXR td(E)R 20 20 20 μs
29 Address Setup to Chip Enable r tAVELN tsu(A)SR 000 n s
30 Chip Enable Pulse Width r, s tELEHN tw(E)SR 20 25 35 ns
31 Chip Disable to Address Change r tEHAXN th(A)SR 000 n s
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selecti on table. Address 6 determines whether the U631H16 performs a ST ORE or RECALL. u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles. Ai E DQi Output tcR ADDRESS 1 VALID VALID Software Controlled STORE/RECALL Cycler, s, t, u (E = HIGH after STORE initiation) ADDRESS 6 (25) (25) Ai E DQi Output tcR tw(E)SR ADDRESS 1 VALID VALID ADDRESS 6 td(E)S (27) (28) (25) th(A)SR (31)(30) tsu(A)SR (29) tdis(E)SR (26) th(A)SR(31) tsu(A)SR (29) tw(E)SR th(A)SR(31) (30) tsu(A)SR (29) (5)tdis(E) Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation) tdis(E)SR (26) td(E)S (27) (28) tcR tw(E)SR th(A)SR (31)(30) tsu(A)SR (29) High Impedance High Impedance td(E)R td(E)R (25)
9 March 31, 2006
STK Control #ML0042 Rev 1.0 Test Configuration for Functional Check VIH VIL VSS VCC w 480 255 30 pF v VO Simultaneous measure- ment of all 8 output pins Input level according to the relevant test measurement DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A10 E W G 5 V v: In measurement of t dis-times and ten-times the capacitance is 5 pF. w: Between V CC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances. Capacitancee Conditions Symbol Min. Max. Unit Input Capacitance VCC VI f Ta = 5.0 V = V SS = 1 MHz = 25 °C C I 8p F Output Capacitance CO 7p F All pins not under test must be connected with ground by capacitors. Operating Temperature Range C= 0t o 7 0 ° C K=- 4 0t o 8 5 ° C G1S1 25CU631H16 Type Package D1 = PDIP28 (600 mil) S1 = SOP24 (300 mil) Ordering Code Leadfree Option blank = Standard Package G1 = Leadfree Green Package Access Time 25 = 25 ns 35 = 35 ns x 45 = 45 ns x Device Marking (example) x: on special request Example Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package Product specification Internal Code ZMD U631H16S1C
25 Z 0425
10 March 31, 2006
STK Control #ML0042 Rev 1.0 Device Operation The U631H16 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The U631H16 performs a READ cycle whenever E and G are LOW while W is HIGH. The address specified on pins A0 - A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of t cR. If the READ is initiated by E or G, the outputs will be valid at t a(E) or at t a(G), whichever is later. The data outputs will repeatedly respond to address changes within the t cR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until ei-ther E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid t su(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The U631H16 is a high speed memory and therefore it must have a high frequency bypass capacitor of appro- ximately 0.1 μF connected between V CC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise pro- blems. Software Nonvolatile STORE The U631H16 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U631H16 implements nonvolatile operation while remaining compatible with standard 2K x 8 SRAMs. During the STORE cycle, an erase of the pre- vious nonvolatile data is first performed, followed by parallel programming of all non- volatile elements. Once a STORE cycle is initiated, fur- ther inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed: 1. Read address 000 (hex) Valid READ 2. Read address 555 (hex) Valid READ 3. Read address 2AA (hex) Valid READ 4. Read address 7FF (hex) Valid READ 5. Read address 0F0 (hex) Valid READ 6. Read address 70F (hex) Initiate STORE Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Software Nonvolatile RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ opera- tions must be performed: 1. Read address 000 (hex) Valid READ 2. Read address 555 (hex) Valid READ 3. Read address 2AA (hex) Valid READ 4. Read address 7FF (hex) Valid READ 5. Read address 0F0 (hex) Valid READ 6. Read address 70E (hex) Initiate RECALL Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Automatic Power Up RECALL On power up, once V CC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the V CC pin must not frop belwo V SWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until t RESTORE after VCC exceeds VSWITCH.
11 March 31, 2006
STK Control #ML0042 Rev 1.0 If the U631H16 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected between W and VCC. Hardware Protection The U631H16 offers hardware protection against inad- vertent STORE operation through VCC sense. For VCC < VSWITCH the software initiated STORE opera- tion will be inhibited. Low Average Active Power The U631H16 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby cur- rent. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the V CC level The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
March 31, 2006 U631H16 LIFE SUPPORT POLICY Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Simtek product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms and conditions of sale. Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
01.11.2001 Ivonne Steffens format revision and release for „Memory CD 2002“
20.04.2004 Matthias Schniebel adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
7.4.2005 Stefan Günther delete PDIP28 (300mil) and SOP28 (300mil), add 10 6 endurance
cycles and 100a data retention and ESD protection > 2000V