U630H16 SIMTEK | Alldatasheet
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Obsolete - Not Recommended for New Designs U630H16
1 March 31, 2006
STK Control #ML0036 Rev 1.0
- High-performance CMOS nonvo- latile static RAM 2048 x 8 bits
- 25, 35 and 45 ns Access Times
- 12, 20 and 25 ns Output Enable Access Times
- Hardware STORE Initiation (STORE Cycle Time < 10 ms)
- Automatic STORE Timing
- 106 STORE cycles to EEPROM
- 100 years data retention in EEPROM
- Automatic RECALL on Power Up
- Hardware RECALL Initiation (RECALL Cycle Time < 20 ms)
- Unlimited RECALL cycles from EEPROM
- Unlimited Read and Write to SRAM
- Single 5 V ± 10 % Operation
- Operating temperature ranges: 0to70 ×C -40to85 ×C -40to125 °C(only 35 ns)
- QS 9000 Quality Standard
- ESD protection > 2000 V (MIL STD 883C M3015.7-HBM)
- RoHS compliance and Pb- free
- Packages:SOP28 (300 mil), PDIP28 (300/600 mil) The U630H16 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory ope- rates as an ordinary static RAM. In nonvolatile operation, data is trans- ferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U630H16 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resi- des in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through the state of the NE pin. The U630H16 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola- tile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. HardStore 2K x 8 nvSRAM Pin Configuration Pin Description Top View 1NE VCC28 2n.c. W27 4A6 A825 5A5 A924 3A7 n.c.26 6A4 n.c.23 7A3 G22 8A2 A1021 12DQ1 DQ517 9A1 E20 10A0 DQ719 11DQ0 DQ618 13DQ2 DQ416 14VSS DQ315 PDIP SOP Signal Name Signal Description A0 - A10 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W Write Enable NE Nonvolatile Enable VCC Power Supply Voltage VSS Ground Features Description
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STK Control #ML0036 Rev 1.0 Block Diagram Operating Mode E NE W G DQ0 - DQ7 Standby/not selected H *** High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z Truth Table for SRAM Operations a: Stresses greater than those listed under „A bsolute Maximum Ratings“ may cause permanent damage to the device. This is a stres s rating only, and functional operation of the device at condition abov e those indicated in the operational sections of this spec ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum Ratingsa Symbol Min. Max. Unit Power Supply Voltage V CC -0.5 7 V Input Voltage V I -0.3 V CC+0.5 V Output Voltage V O -0.3 V CC+0.5 V Power Dissipation P D 1W Operating Temperature C-Type K-Type A-Type T a -40 -40 Storage Temperature T stg -65 150 °C Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the o perating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. * H or L EEPROM Array 32 x (64 x 8) STORE RECALLSRAM Array
32 Rows x
G NE E W DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Column I/O Column Decoder A0 A 1 A2 A3 A4A10 Input Buffers
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STK Control #ML0036 Rev 1.0 b: I CC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: I CC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2. DC Characteristics Symbol Conditions C-Type K-Type A-Type Unit Operating Supply Currentb ICC1 VCC VIL VIH tc tc tc = 5.5 V = 0.8 V = 2.2 V = 25 ns = 35 ns = 45 ns mA mA mA Average Supply Current during STORE c ICC2 VCC E W VIL VIH = 5.5 V ≥ VCC-0.2 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 677 m A Standby Supply Currentd (Cycling TTL Input Levels) ICC(SB)1 VCC E tc tc tc = 5.5 V ≥ VIH = 25 ns = 35 ns = 45 ns mA mA mA Average Supply Current at t cR = 200 nsb (Cycling CMOS Input Levels) ICC3 VCC W VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 15 15 15 mA Standby Supply Currentd (Stable CMOS Input Levels) ICC(SB) VCC E VIL VIH = 5.5 V ≥ VCC-0.2 V ≤ 0.2 V ≥ VCC-0.2 V 112 m A Recommended Operating Conditions Symbol Conditions Min. Max. Unit Power Supply Voltage V CC 4.5 5.5 V Input Low Voltage V IL -2 V at Pulse Width 10 ns permitted -0.3 0.8 V Input High Voltage V IH 2.2 V CC+0.3 V
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STK Control #ML0036 Rev 1.0 DC Characteristics Symbol Conditions Min. Max. Unit Output High Voltage Output Low Voltage VOH VOL VCC IOH IOL = 4.5 V =-4 mA = 8 mA 2.4 0.4 V V Output High Current Output Low Current I OH IOL VCC VOH VOL = 4.5 V = 2.4 V = 0.4 V 8 -4 mA mA Input Leakage Current High Low I IH IIL VCC VIH VIL = 5.5 V = 5.5 V = 0 V - 1 1 μA μA Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ VCC VOH VOL = 5.5 V = 5.5 V = 0 V - 1 1 μA μA SRAM Memory Operations No. Switching Characteristics Read Cycle Symbol 25 35 45 Unit
1 Read Cycle Time f tAVAV tcR 25 35 45 ns
2 Address Access Time to Data Valid g tAVQV ta(A) 25 35 45 ns
3 Chip Enable Access Time to Data Valid t ELQV ta(E) 25 35 45 ns
4 Output Enable Access Time to Data Valid t GLQV ta(G) 12 20 25 ns
5E HIGH to Output in High-Zh tEHQZ tdis(E) 13 17 20 ns 6G HIGH to Output in High-Zh tGHQZ tdis(G) 13 17 20 ns 7E LOW to Output in Low-Z t ELQX ten(E) 555 n s 8G LOW to Output in Low-Z t GLQX ten(G) 000 n s 9 Output Hold Time after Addr. Change g tAXQX tv(A) 333 n s
10 Chip Enable to Power Active e tELICCH tPU 000 n s
11 Chip Disable to Power Standby d, e tEHICCL tPD 25 35 45 ns
e: Parameter guaranteed but not tested. f: Device is continuously selected with E and G both LOW. g: Address valid prior to or coincident with E transition LOW. h: Measured ± 200 mV from steady state output voltage.
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STK Control #ML0036 Rev 1.0 Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f ta(A) Output Data Valid tcR Address Valid tv(A) Ai DQi Output Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g Ai E G DQi Output tdis(E) tcR ta(E) ten(E) ten(G) ta(G) tdis(G) Address Valid High Impedance ICC ACTIVE STANDBY tPD tPU No. Switching Characteristics Write Cycle Symbol 25 35 45 Unit
12 Write Cycle Time t AVAV tAVAV tcW 25 35 45 ns
13 Write Pulse Width t WLWH tw(W) 20 30 35 ns
14 Write Pulse Width Setup Time t WLEH tsu(W) 20 30 35 ns
15 Address Setup Time t AVWL tAVEL tsu(A) 000n s
16 Address Valid to End of Write t AVWH tAVEH tsu(A-WH) 20 30 35 ns
17 Chip Enable Setup Time t ELWH tsu(E) 20 30 35 ns
18 Chip Enable to End of Write t ELEH tw(E) 20 30 35 ns
19 Data Setup Time to End of Write t DVWH tDVEH tsu(D) 12 18 20 ns
20 Data Hold Time after End of Write t WHDX tEHDX th(D) 000n s
21 Address Hold after End of Write t WHAX tEHAX th(A) 000n s
22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 10 13 15 ns
23 W HIGH to Output in Low-Z t WHQX ten(W) 555n s
(1) (2) (9) (1) (3) (4) (5)(7) (6) (8) (10) (11) ta(A) (2) Previous Data Valid Output Data Valid
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STK Control #ML0036 Rev 1.0 th(D) Write Cycle #1: W-controlledj Ai E W DQi Input DQi Output tcW tsu(E) th(A) tw(W)tsu(A) tsu(D) tdis(W) ten(W) Input Data Valid High Impedance tsu(A) Write Cycle #2: E-controlledj th(D) Ai E W DQi Input DQi Output tcW tw(E) th(A) tsu(D) tdis(W)ten(E) Input Data Valid High Impedance tsu(W) L- to H-level undefined H- to L-level i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state. j: E or W and NE must be > VIH during address transitions. tsu(A-WH) Previous Data (12) (17) (16) (13) (19) (20) (23)(22) (15) (21) (12) (15) (18) (21) (14) (20)(19) (22)(7) Address Valid Address Valid
7 March 31, 2006
STK Control #ML0036 Rev 1.0 Nonvolatile Memory Operations No. STORE Cycle Inhibit and Automatic Power Up RECALL Symbol Min. Max. Unit Alt. IEC
24 Power Up RECALL Duration k, e tRESTORE 650 μs
Low Voltage Trigger Level V SWITCH 4.0 4.5 V k: t RESTORE starts from the time VCC rises above VSWITCH. STORE Cycle Inhibit and Automatic Power Up RECALL VCC 5.0 V STORE inhibit Power Up VSWITCH tRESTORE RECALL (24) t Mode Selection E W G NE Mode Power Notes L H L L Nonvolatile RECALL Active l L L H L Nonvolatile STORE I CC2 L L L H L H L No operation Active * H or L l: An automatic RECALL also takes pl ace at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly.
8 March 31, 2006
STK Control #ML0036 Rev 1.0 STORE Cycles No. STORE Cycle W -controlled Symbol Min. Max. Unit Alt. IEC
25 STORE Cycle Time m tWLQX td(W)S 10 ms
26 STORE Initiation Cycle Time n tWLNH tw(W)S 25 ns
27 Output Disable Setup to NE Fall t GHNL tsu(G)S 5n s
28 NE Setup t NLWL tsu(N)S 5n s
29 Chip Enable Setup t ELWL tsu(E)S 5n s
STORE Cycle: W-controlledo tsu(G)S tsu(N)S tw(W)S tsu(E)S td(W)S High Impedance (25) (29) (28)(27) (26) NE G W E DQi Output STORE Cycle: E-controlledo No. STORE Cycle E -controlled Symbol Min. Max. Unit Alt. IEC
30 STORE Cycle Time t ELQXS td(E)S 10 ms
31 STORE Initiation Cycle Time t ELNHS tw(E)S 25 ns
32 Output Disable Setup to E Fall t GHEL tsu(G)S 5n s
33 NE Setup t NLEL tsu(N)S 5n s
34 Write Enable Setup t WLEL tsu(W)S 5n s
tsu(N)S tsu(G)S tsu(W)S td(E)S High Impedance (30) (31) (33) (32) (34) tw(E)S NE G W E DQi Output
9 March 31, 2006
STK Control #ML0036 Rev 1.0 RECALL Cycles No. RECALL Cycle NE -controlled Symbol Min. Max. Unit Alt. IEC
35 RECALL Cycle Time p tNLQX td(N)R 20 μs
36 RECALL Initiation Cycle Time q tNLNH tw(N)R 25 ns
37 Output Enable Setup t GLNL tsu(G)R 5n s
38 Write Enable Setup t WHNL tsu(W)R 5n s
39 Chip Enable Setup t ELNL tsu(E)R 5n s
40 NE Fall to Output Inactive t NLQZ tdis(N)R 25 ns
RECALL Cycle: NE-controlledo tw(N)R (36) NE G W E DQi Output tsu(G)R tsu(W)R tsu(E)R td(N)R tdis(N)R (37) (38) (40) (35)(39) High Impedance No. RECALL Cycle E -controlled Symbol Min. Max. Unit Alt. IEC
41 RECALL Cycle Time t ELQXR td(E)R 20 μs
42 RECALL Initiation Cycle Time t ELNHR tw(E)R 25 ns
43 NE Setup t NLEL tsu(N)R 5n s
44 Output Enable Setup t GLEL tsu(G)R 5n s
45 Write Enable Setup t WHEL tsu(W)R 5n s
RECALL Cycle: E-controlledo NE G W E DQi Output tsu(N)R tsu(G)R tsu(W)R tw(E)R td(E)R High Impedance (41) (42) (43) (45) (44)
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STK Control #ML0036 Rev 1.0 No. RECALL Cycle G -controlled Symbol Min. Max. Unit Alt. IEC
46 RECALL Cycle Time t GLQXR td(G)R 20 μs
47 RECALL Initiation Cycle Time t GLNH tw(G)R 25 ns
48 NE Setup t NLGL tsu(N)R 5n s
49 Write Enable Setup t WHGL tsu(W)R 5n s
50 Chip Enable Setup t ELGL tsu(E)R 5n s
RECALL Cycle: G-controlledo, r NE G W E DQi Output tsu(N)R tsu(W)R tsu(E)R tw(G)R td(G)R High Impedance (48) (47) (49) (50) (46) m: Measured with W and NE both returned HIGH, and G returned LOW. Note that STORE cycles are inhibited/aborted by V CC < VSWITCH (STORE inhibit). n: Once t w(W)S has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE , G, W and E may be used to terminate the STORE initiation cycle. o: If E is LOW for any period of time in which W is HIGH while G and NE are LOW, than a RECALL cycle may be initiated. For E-controlled STORE during tw(E)S W, G, NE have to be static. p: Measured with W and NE both HIGH, and G and E LOW. q: Once t w(N)R has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE , G or E may be used to terminate the RECALL initiation cycle. r: If W is LOW at any point in which both E and NE are LOW and G is HIGH, than a STORE cycle will be initiated instead of a RECALL.
11 March 31, 2006
STK Control #ML0036 Rev 1.0 Test Configuration for Functional Check s: In measurement of t dis-times and ten-times the capacitance is 5 pF. t: Between V CC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances. Capacitancee Conditions Symbol Min. Max. Unit Input Capacitance VCC VI f Ta = 5.0 V = V SS = 1 MHz = 25 °C C I 8p F Output Capacitance CO 7p F All pins not under test must be connected with ground by capacitors. VIH VIL VSS VCC t 255 30 pF s VO Simultaneous measure- ment of all 8 output pins Input level according to the relevant test measurement DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A10 E W G 5 V NE 480 G1S 25CU630H16 Type Package D u= PDIP28 (300 mil) D1 = PDIP28 (600 mil) S = SOP28 (300 mil) Ordering Code Device Marking (example) u: on special request Example Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package Product specification Internal Code ZMD U630H16SC
25 Z 0425
Operating Temperature Range C= 0t o 7 0 ° C K=- 4 0t o 8 5 ° C A=- 4 0t o1 2 5 ° C (only 35 ns and SOP28 package) Leadfree Option blank = Standard Package G1 = Leadfree Green Package Access Time 25 = 25 ns 35 = 35 ns (C/K Type on special request) 45 = 45 ns
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STK Control #ML0036 Rev 1.0 Device Operation The U630H16 has two separate modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. In SRAM mode, the memory opera- tes as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The U630H16 performs a READ cycle whenever E and G are LOW while W and NE are HIGH. The address specified on pins A0 - A10 determines which of the 2048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of t cR. If the READ is initiated by E or G, the outputs will be valid at t a(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the t cR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or NE is brought LOW. SRAM WRITE A WRITE cycle is performed whenever E and W are LOW and NE is HIGH. The address inputs must be sta- ble prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid t su(D) before the end of a W control- led WRITE or t su(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the en- tire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The U630H16 is a high speed memory and therefore must have a high frequency bypass capacitor of appro- ximately 0.1 μF connected between V CC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise pro- blems. Hardware Nonvolatile STORE A STORE cycle is performed when NE , E and W are LOW while G is HIGH. While any sequence to achieve this state will initiate a STORE, only W initiation and E initiation are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output is disabled and the DQ0 - 7 pins are tristated until the cycle is completed. If E and G are LOW and W and NE are HIGH at the end of the cycle, a READ will be performed and the out- puts will go active, indicating the end of the STORE. Hardware Nonvolatile RECALL A RECALL cycle is performed when E , G and NE are LOW while W is HIGH. Like the STORE cycle, RECALL is initiated when the last of the three clock-signals goes to the RECALL state. Once initiated, the RECALL cycle will take „RECALL Cycle Time“ to complete, during which all inputs are ignored. When the RECALL com- pletes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. Like the STORE cycle, a transition must occur on some control pins to cause a RECALL, preventing inadver- tend multi-triggering. Automatic Power Up RECALL On power up, once V CC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the V CC pin must not drop below V SWITCH once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until t RESTORE after VCC exceeds V SWITCH. If the U630H16 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 KΩ resistor should be connected between W and system VCC. Hardware Protection The U630H16 offers two levels of protection to sup- press inadvertent STORE cycles. If the control signals , G, W and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, the U630H16 offers hardware protection through V CC Sense. When V CC < V SWITCH the externally initiated STORE operation will be inhibited.
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STK Control #ML0036 Rev 1.0 The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Low Average Active Power The U630H16 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby cur- rent. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the V CC level
March 31, 2006 U630H16 LIFE SUPPORT POLICY Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Simtek product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However, Simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document descri- bes the type of component and shall not be considered as assured characteristics. Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trade- mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms and conditions of sale. Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
01.11.2001 Ivonne Steffens format revision and release for „Memory CD 2002“
11.08.2003 Matthias Schniebel adding A-Type with ICC1 = 85mA; ICC2 = 7mA; ICC3 = 15mA;
ICC(SB) = 2mA; ICC(SB)1 = 27 mA
20.04.2004 Matthias Schniebel adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
7.4.2005 Stefan Günther changing to 10 6 endurance cycles and 100a data retention, delete ESD
classes, change ordering code, PDIP 300 on special request, RoHS and Pb- free added, C/K limitation for PDIP deleted