U62H256A ZMD | Alldatasheet
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Technical content
1 April 20, 2004
! 32768 x 8 bit static CMOS RAM ! 35 and 55 ns Access Time ! Common data inputs and data outputs ! Three-state outputs ! Typ. operating supply current 35 ns: 45 mA 55 ns: 30 mA ! Standby current < 50 µA at 125 °C ! TTL/CMOS-compatible ! Power supply voltage 5 V ! Operating temperature range -40 °C to 85 °C -40 °C to 125 °C ! QS 9000 Quality Standard ! ESD protection > 2000 V (MIL STD 883C M3015.7) ! Latch-up immunity >100 mA ! Package: SOP28 (300/330 mil) The U62H256A is a static RAM manufactured using a CMOS pro- cess technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the fal- ling edge of E . The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G , afterwards the data word will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information is available. The data outputs have no preferred stat e. The Read cycle is finished by the falling edge of W or by the rising edge of E , respec- tively. Data retention is guaranteed down to 2 V. With the exception of E , all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. Automotive Fast 32K x 8 SRAM Pin Configuration Top View Signal Name Signal Description A0 - A14 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W Write Enable VCC Power Supply Voltage VSS Ground Pin Description 1A14 VCC28 2A12 W27 4A6 A8 25 5A5 A9 24 3A7 A13 26 6A4 A11 23 7A3 G22 8A2 A10 21 12DQ1 DQ5 17 9A1 E20 10A0 DQ7 19 11DQ0 DQ6 18 13DQ2 DQ4 16 14VSS DQ3 15 SOP Features Description
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- H or L Operating Mode E W G DQ0 - DQ7 Standby/not selected H * * High-Z Internal Read L H H High-Z Read L H L Data Outputs Low-Z Write L L * Data Inputs High-Z Truth Table Block Diagram DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VSS W GE Row Address Inputs Column Address Inputs Address Change Detector Column Decoder Row Decoder Sense Amplifier/ Write Control Logic Clock Generator Common Data I/O Memory Cell Array
512 Rows x
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d -2 V at Pulse Width 10 ns Recommended Operating Conditions Symbol Conditions Min. Max. Unit Power Supply Voltage V CC 4.5 5.5 V Input Low Voltage d VIL -0.3 0.8 V Input High Voltage V IH 2.2 V CC + 0.3 V Characteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage. a Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability b Maximum voltage is 7 V c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Absolute Maximum Ratings a Symbol Min. Max. Unit Power Supply Voltage V CC -0.5 7 V Input Voltage V I -0.5 V CC + 0.5 b V Output Voltage V O -0.5 V CC + 0.5 b V Power Dissipation P D -1 W Operating Temperature K-Type A-Type Ta -40 -40 125 Storage Temperature T stg -65 150 °C Output Short-Circuit Current at VCC = 5 V and VO = 0 V c | IOS | 200 mA
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Electrical Characteristics Symbol Conditions Min. Max. Unit Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) ICC(OP) ICC(SB) ICC(SB)1 VCC VIL VIH tcW tcW VCC VE K-Type A-Type V CC VE = 5 . 5 V = 0 . 8 V =2 . 2 V = 35 ns = 55 ns =5 . 5 V = V CC - 0.2 V = 5.5 V = 2.2 V mA mA µA µA mA Output High Voltage Output Low Voltage VOH VOL VCC IOH VCC IOL = 4.5 V = -4.0 mA =4 . 5 V =8 . 0 m A 2.4 0.4 V V Input High Leakage Current Input Low Leakage Current I IH IIL VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0 V 2µ A µA Output High Current Output Low Current I OH IOL VCC VOH VCC VOL =4 . 5 V =2 . 4 V =4 . 5 V =0 . 4 V -4 mA mA Output Leakage Current High at Three-State Outputs Low at Three-State Outputs I OHZ IOLZ VCC VOH VCC VOL =5 . 5 V =5 . 5 V =5 . 5 V =0 V 2µ A µA
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Read Cycle Time t RC tcR 35 55 ns Address Access Time to Data Valid t AA ta(A) 35 55 ns Chip Enable Access Time to Data Valid t ACE ta(E) 35 55 ns G LOW to Data Valid t OE ta(G) 15 25 ns E HIGH to Output in High-Z t HZCE tdis(E) 15 20 ns G HIGH to Output in High-Z t HZOE tdis(G) 12 15 ns E LOW to Output in Low-Z t LZCE ten(E) 33 n s G LOW to Output in Low-Z t LZOE ten(G) 00 n s Output Hold Time from Address Change t OH tv(A) 33 n s E LOW to Power-Up Time t PU 00 n s E HIGH to Power-Down Time t PD 35 55 ns Switching Characteristics Write Cycle Symbol 35 55 Unit Write Cycle Time t WC tcW 35 55 ns Write Pulse Width t WP tw(W) 20 35 ns Write Setup Time t WP tsu(W) 20 35 ns Address Setup Time t AS tsu(A) 00 n s Address Valid to End of Write t AW tsu(A-WH) 25 40 ns Chip Enable Setup Time t CW tsu(E) 25 40 ns Pulse Width Chip Enable to End of Write t CW tw(E) 25 40 ns Data Setup Time t DS tsu(D) 15 25 ns Data Hold Time t DH th(D) 00 n s Address Hold from End of Write t AH th(A) 00 n s W LOW to Output in High-Z t HZWE tdis(W) 15 20 ns G HIGH to Output in High-Z t HZOE tdis(G) 12 15 ns W HIGH to Output in Low-Z t LZWE ten(W) 00 n s G LOW to Output in Low-Z t LZOE ten(G) 00 n s
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4.5 V tsu(DR) trec VCC E VCC(DR) ≥ 2 V 0 V 2.2 V2.2 V VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V Data Retention Characteristics Symbol Conditions Min. Typ. Max. Unit Alt. IEC Data Retention Supply Voltage V CC(DR) 25 . 5 V Data Retention Supply Current I CC(DR) VCC(DR) = 3 V VE = V CC(DR) - 0.2 V K-Type A-Type µA µA Data Retention Setup Time t CDR tsu(DR) See Data Retention Waveforms (above) 0n s Operating Recovery Time t R trec tcR ns Test Configuration for Functional Check DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VIH VIL VSS VCC 5 V 481 255 30 pF e VO Input level according to the relevant test measurement Simultaneous measure- ment of all 8 output pins A10 A11 A12 A13 A14 E W G e In measurement of t dis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF. Data Retention Mode
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Capacitance Conditions Symbol Min. Max. Unit Input Capacitance VCC VI f Ta = 5.0 V = V SS = 1 MHz = 25 °C C I 7p F Output Capacitance Co 7p F All pins not under test must be connected with ground by capacitors. Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package Product specification Assembly location and trace code Internal Code Ordering Code Device Marking (example) ZMD U62H256ASK 35LL C 0425
1 ZZ G1
35 = 35 ns 55 = 55 ns LLS 35KU62H256A Type Package S = SOP28 (300 mil) S2 = SOP28 (330 mil) Type 2 Operating Temperature Range K = -40 to 85 °C A = -40 to 125 °C Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Power Consumption blank = Standard (only A-Type) LL = Very Low Power (only K-Type) f on special request Example
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tdis(G) tdis(E) tcR Previous Data Valid Output Data Valid Address Valid Address Valid tsu(A) High-Z ten(E) ten(G) ta(G) ta(E) Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH) Read Cycle 2: G -, E-controlled (during Read Cycle: W = VIH) ta(A) tcR tv(A) Ai DQi Output Ai G DQi Output tPD ICC(OP) ICC(SB) 50 % 50 % Output Data Valid E
9 April 20, 2004
Write Cycle1: W-controlled th(D) Ai E W DQi Input G DQi Output tcW tsu(E) th(A) tw(W)tsu(A) tsu(D) tdis(W) ten(W) Address Valid Input Data Valid High-Z tsu(A-WH) Write Cycle 2: E-controlled Input Data Valid tsu(A) th(D) Ai E W DQi Input G DQi Output tcW tw(E) th(A) tsu(W) tsu(D) tdis(W)ten(E) High-Z Address Valid tdis(G) L- to H-level undefined H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG Grenzstraße 28 • D-01109 Dresden • P . O. B. 80 01 34 • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de April 20, 2004 U62H256A LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured charac- teristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade- mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMDs warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.