U6264AS1A07 ZMD | Alldatasheet

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/G70 8192 x 8 bit static C M O S R A M /G70 70 ns A ccess Tim e /G70 Comm on data inputs and outputs /G70 Three-state outputs /G70 Typ. operating supply current: 30 m A /G70 TTL/CM OS-com patible /G70 Autom atic reduction of pow er dissipation in long Read or W rite cycles /G70 Pow er supply voltage 5 V /G70 Op erating tem perature ranges -40 to 125 °C /G70 Qu ality assessm ent according to CECC 90000, CE CC 90100 and CECC 90111 /G70 ESD protection > 2000 V (MIL STD 883C M3015.7) /G70 Latch-up im m unity > 100 m A /G70 Packages: SOP 28 (300 m il) SOP 28 (330 m il) Pin Configuration 1n.c. VC C28 2A12 W (W E)27 4A6 A825 5A5 A924 3A7 E2 (CE2)26 6A4 A1123 7A3 G (O E)22 8A2 A1021 12D Q 1 D Q 517 9A1 E1 (C E1)20 10A0 D Q 719 11D Q 0 D Q 618 13D Q 2 D Q 416 14VSS DQ 315 SOP Pin Description Signal N ame S ignal D escription A0 - A 12 Address Inputs D Q 0 - D Q 7 D ata In/O utputs E1 Ch ip Enable 1 E2 Ch ip Enable 2 G O utput Enable W R ead/W rite Enable VCC Pow er Supply Voltage VSS G round n.c. not connected Top View A utom otive 8K x 8 SRA M

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*H or L O perating M ode E1 E2 W G DQ 0 - D Q7 Standby/not selected * L * * H igh-Z H *** H igh-Z Internal Read L H H H H igh-Z Read L H H L D ata Outputs, Low-Z Write L H L * Data Inputs, High-Z Truth Table M axim um R atings S ym bol M in. M ax. U nit P ow er Supply Voltage VCC -0.3 7 V Input Voltage VI -0.3 VCC + 0.5 V O utput Voltage VO -0.3 VCC + 0.5 V P ow er Dissipation PD 1W O perating Tem perature Ta -40 125 °C S torage Tem perature Tstg -65 150 °C C haracteristics A10 Address C hange D etector B lock D iagram M em ory C ell Array

256 R ows x

256 C olum ns

C om m on Data I/OSense A mplifier/ W rite Control Logic C lock G enerator D Q 0 D Q 1 D Q 2 D Q 3 D Q 4 D Q 5 D Q 6 D Q 7 C olum n Address Inputs VCC VSS W G A11 A12 All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the pow er supply voltage range and in the operating temperature range specified. Dynamic measurem ents are based on a rise and fall time of ≤ 5 ns, m easured betw een 10 % and 90 % of VI, as w ell as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V , with the exception of the tdis-times, in which cases transition is m easured ± 200 m V from steady-state voltage.

3Decem ber 12, 1997 U6264ASA07 Electrical Characteristics S ym bol C onditions M in. M ax. U nit Supply C urrent - Op erating Mode Supply Current - Standby M ode (TTL level) ICC(OP) IC C(SB)1 VCC VIL VIH tcW VCC VE1 = VE2 or VE2 = 5.5 V = 0.8 V = 2.2 V = 70 ns = 5.5 V = 2.2 V = 0.8 V mA mA Ou tput High Voltage TTL com patible C M OS com patible Ou tput Low Voltage V OH VOH VOL VCC IOH VCC IOL = 4.5 V = -1.0 mA = 4.5 V = 3.2 mA 2.4 0.85*VCC 0.4 V V V Ou tput High Current Ou tput Low Current I OH IOL VCC VOH VCC VOL = 4.5 V = 2.4 V = 4.5 V = 0.4 V 3.2 mA mA Supply Current - Standby M ode (CM OS level) Supply C urrent - Data Retention Mo de I CC (SB) ICC(D R) VCC VE1 = VE2 or VE2 VCC (DR ) VE1 = VE2 or VE2 = 5.5 V = VCC - 0.2 V = 0.2 V = 3 V = VC C(DR ) - 0.2 V = 0.2 V µA µA Input High Leakage Current Input Low Leakage Current I IH IIL VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0 V µA µA Ou tput Leakage Current H igh at Three-S tate O utputs Low at Three-State O utputs IOHZ IOLZ VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0 V µA µA * -2 V at Pulse W idth 10 ns Re com m ended O perating Conditions S ym bol Co nditions M in. M ax. Un it Pow er Supply Voltage VCC 4.5 5.5 V Data R etention Voltage V CC(D R ) 2.0 - V Input Low Voltage* VIL -0.3 0.8 V Input High Voltage VIH 2.2 V CC +0.3 V

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Sw itching Characteristics Sym bol M in. Ma x. U nit Alt. IE C Tim e to O utput in Low -Z tLZ tt(Q X) 5 10 ns Cycle Tim e W rite C ycle Time Read Cycle Tim e tWC tRC tcW tcR ns ns Access Time LO W or E2 HIGH to D ata Valid G LO W to Data Valid Address to D ata Valid tAC E tOE tAA ta(E) ta(G) ta(A ) ns ns ns Pulse W idths W rite Pulse W idth Ch ip Enable to End of W rite t WP tCW tw(W) tw(E) ns ns Setup Tim es Address Setup Tim e Ch ip Enable to End of W rite W rite Pulse W idth Data Setup Tim e t AS tCW tWP tDS tsu(A ) tsu(E) tsu(W ) tsu(D ) ns ns ns ns Data Hold Tim e Address H old from End of W rite t DH tAH th(D) th(A ) ns ns Ou tput Hold Tim e from Address C hange t OH tv(A ) 5 - ns E1 HIGH or E2 LO W to O utput in High-Z W LO W to O utput in High-Z G HIGH to O utput in High-Z tHZCE tHZWE tHZOE tdis(E) tdis(W ) tdis(G ) ns ns ns VCC (D R ) ≥ 2 V D ata Retention M ode E 1-Controlled D ata Retention M ode E2-Controlled D ata Retention 4.5 V tDR trec VCC VC C (DR ) ≥ 2 V V E2(DR) ≥ VCC(D R ) - 0.2 V or VE2(DR ) ≤ 0.2 V V CC(D R ) - 0.2 V ≤ VE1(D R) ≤ VCC (DR) + 0.3 V 0 V D ata Retention tDR 0.8 V0.8 V VE2(DR ) ≤ 0.2 V 2.2 V2.2 V 4.5 V 0 V VCC Ch ip Deselect to D ata R etention Time tDR : m in 0 ns Op erating R ecovery Time trec: m in tcR trec

5Decem ber 12, 1997 U6264ASA07 Test Configuration for Functional Check (for TTL output levels) VIH VIL VSS VCC 5 V 960 510 30 pF1) VO Sim ultaneous measure- m ent of all 8 output pins Input level according to the relevant test measurem ent 1) In m easurem ent of tdis(E), tdis(W ), tdis(G ) the capacitance is 5 pF. IC Code N um bers E xam ple All pins not under test m ust be connected w ith ground by capacitors. A10 A11 A12 W G D Q 0 D Q 1 D Q 2 D Q 3 D Q 4 D Q 5 D Q 6 D Q 7 Ca pacitance Co nditions S ym bol M in. M ax. U nit Input Capacitance VCC = 5.0 V VI = VSS C I 8 pF O utput C apacitance f = 1 M Hz Ta = 25 °C C O 10 pF SU 6264A 07A Type Package S1 = S OP28 (300 m il) S = SO P 28 (330 m il) A ccess Tim e 07 = 70 ns O perating Tem perature R ange A = -40 to 125 °C Internal Code The date of m anufacture is given by the last 4 digits of the m ark, the first 2 digits indicating the year, and the last 2 digits the calendar w eek.

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th(D ) Re ad Cycle 1 (during Read cycle: E1 = G = V IL, E2 = W = VIH) Re ad Cycle 2 (during Read cycle: W = VIH) Write C ycle 1 (W-controlled) ta(A ) Previous D ata Valid O utput Data Valid tcR Addresses Valid tv(A) AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA A i DQ i Ai G DQ i O utput O utput tdis(E) tcR tsu(A ) ta(E) tsu(A ) tt(Q X) tt(Q X ) tt(Q X) ta(G) ta(E) tdis(E) tdis(G ) Addresses Valid O utput Data Valid AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Ai W DQ i Input G DQ i O utput tcW tsu(E) th(A) tw (W)tsu(A ) tsu(E ) tsu(D ) tdis(W) tt(QX ) Addresses Valid Input Data Valid High-Z AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AA AA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA High-Z AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA

7Decem ber 12, 1997 U6264ASA07 tsu(A ) Input Data Valid th(D) tsu(W ) tw (E) tsu(D ) tcW Addresses Valid tsu(E) th(A ) tt(QX ) tdis(W) AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA Ai W DQ i Input G DQ i O utput High-Z tsu(A ) AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A AAAA A AAA A AAA A AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA A A A A A undefined L- or H-level Write Cycle 2 (E 1-controlled) Write Cycle 3 (E2-controlled) th(D ) Ai W DQ i Input G DQ i O utput tcW tw(E ) th(A ) tsu(W) tsu(E ) tsu(D) tdis(W )tt(QX ) Addresses Valid Input Data Valid High-Z AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA

ZM D products are not designed, intended, or authorized for use as components in systems intend for surgical im plant into the body, or other applications intended to support or sustain life, or for any other application in w hich the failure of the ZM D product could create a situation where personal injury or death m ay occur. Co m ponents used in life-support devices or systems must be expressly authorized by ZM D for such purpose. The inform ation describes the type of com ponent and shall not be considered as assured characteristics. Term s of delivery and rights to change design reserved. Memory Products 1998 Automotive 8K x 8 SRAM U6264ASA07 Zentrum M ikroelektronik D resden G m bH Grenzstraße 28 • D-01109 D resden • P. O. B. 80 01 34 • D -01101 D resden • Germ any Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Em ail: sales@ zmd .de Internet W eb Site: http://w w w .zmd.de