IRFR1111 IRF | Alldatasheet
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HEXFET ® Power MOSFET VDSS = 30V R DS(on) = 0.031Ω ID = 33A 8/25/97 Parameter Typ. Max. Units RθJC Junction-to-Case ––– 2.2 RθJA Junction-to-Ambient (PCB mount)** ––– 50 °C/W RθJA Junction-to-Ambient ––– 110 Thermal Resistance D-Pak TO-252AA I-Pak TO-251AA l Ultra Low On-Resistance l Surface Mount (IRFR3303) l Straight Lead (IRFU3033) l Advanced Process Technology l Fast Switching l Fully Avalanche Rated
Description
Parameter Max. Units ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 33 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 21 A IDM Pulsed Drain Current 120 PD @T C = 25°C Power Dissipation 57 W Linear Derating Factor 0.45 W/°C VGS Gate-to-Source Voltage ± 20 V EAS Single Pulse Avalanche Energy 95 mJ IAR Avalanche Current 18 A EAR Repetitive Avalanche Energy 5.7 mJ dv/dt Peak Diode Recovery dv/dt 5.0 V/ns TJ Operating Junction and -55 to + 150 TSTG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Absolute Maximum Ratings Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. S D G PD - 9.1642A
Parameter Min. Typ. Max. Units Conditions V(BR)DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V V GS = 0V, ID = 250µA ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.032 ––– V/°C Reference to 25°C, ID = 1mA R DS(on) Static Drain-to-Source On-Resistance ––– ––– 0.031Ω VGS = 10V, ID = 18A VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V V DS = VGS , ID = 250µA gfs Forward Transconductance 9.3 ––– ––– S V DS = 25V, ID = 18A ––– ––– 25 µA VDS = 30V, VGS = 0V ––– ––– 250 V DS = 24V, VGS = 0V, TJ = 150°C Gate-to-Source Forward Leakage ––– ––– 100 V GS = 20V Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V Q g Total Gate Charge ––– ––– 29 I D = 18A Q gs Gate-to-Source Charge ––– ––– 7.3 nC V DS = 24V Q gd Gate-to-Drain ("Miller") Charge ––– ––– 13 V GS = 10V, See Fig. 6 and 13 td(on) Turn-On Delay Time ––– 11 ––– V DD = 15V tr Rise Time ––– 99 ––– I D = 18A td(off) Turn-Off Delay Time ––– 16 ––– R G = 13Ω tf Fall Time ––– 28 ––– R D = 0.8Ω, See Fig. 10 Between lead,––– ––– 6mm (0.25in.) from package and center of die contact C iss Input Capacitance ––– 750 ––– V GS = 0V C oss Output Capacitance ––– 400 ––– pF V DS = 25V C rss Reverse Transfer Capacitance ––– 140 ––– ƒ = 1.0MHz, See Fig. 5 nH Electrical Characteristics @ TJ = 25°C (unless otherwise specified) LD Internal Drain Inductance LS Internal Source Inductance ––– ––– IGSS ns 4.5 7.5 IDSS Drain-to-Source Leakage Current Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions IS Continuous Source Current MOSFET symbol (Body Diode) ––– ––– showing the ISM Pulsed Source Current integral reverse (Body Diode) ––– ––– p-n junction diode. VSD Diode Forward Voltage ––– ––– 1.3 V T J = 25°C, IS = 18A, VGS = 0V trr Reverse Recovery Time ––– 53 80 ns T J = 25°C, IF = 18A Q rr Reverse RecoveryCharge ––– 94 140 nC di/dt = 100A/µs ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD ) 120 A Notes: ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact Starting TJ = 25°C, L = 590µH RG = 25Ω , IAS = 18A. (See Figure 12) Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) ISD ≤ 18A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS , TJ ≤ 150°C Pulse width ≤ 300µs; duty cycle ≤ 2%. S D G S D G Caculated continuous current based on maximum allowable junction temperature; Package limitation current = 20A.
Fig 4. Normalized On-Resistance Vs. Temperature Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics Fig 3. Typical Transfer Characteristics -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 T , Junction Temperature( C) R , Drain-to-Source On Resistance (Normalized) J DS(on) V = I = GS D 10V 30A 0.1 100 4 5 6 7 8 9 10 V = 25V 20µs PULSE WIDTH DS V , Gate-to-Source Voltage (V) I , Drain-to-Source Current (A) GS D T = 25 CJ ° T = 150 CJ ° 0.01 0.1 100 1000 0.1 1 10 100 20µs PULSE WIDTH T = 25CJ ° TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V V , Drain-to-Source Voltage (V) I , Drain-to-Source Current (A) DS D 4.5V 100 1000 0.1 1 10 100 20µs PULSE WIDTH T = 150CJ ° TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V V , Drain-to-Source Voltage (V) I , Drain-to-Source Current (A) DS D 4.5V 15V
Fig 8. Maximum Safe Operating Area Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 7. Typical Source-Drain Diode Forward Voltage 0.1 100 1000 V ,Source-to-Drain Voltage (V) I , Reverse Drain Current (A) SD SD V = 0 V GS T = 25 CJ ° T = 150 CJ ° 100 1000 1 10 100 OPERATION IN THIS AREA LIMITED BY RDS(on) Single Pulse T T = 150 C = 25 C° C V , Drain-to-Source Voltage (V) I , Drain Current (A)I , Drain Current (A) DS D 10us 100us 1ms 10ms 0 5 10 15 20 25 30 Q , Total Gate Charge (nC) V , Gate-to-Source Voltage (V) G GS FOR TEST CIRCUIT SEE FIGURE I =D 18A V = 15VDS V = 24VDS 1 10 100 200 400 600 800 1000 1200 1400 V , Drain-to-Source Voltage (V) C, Capacitance (pF) DS V C C C 0V, C C C f = 1MHz + C + C C SHORTED GS iss gs gd , ds rss gd oss ds gd C iss C oss C rss
Fig 10a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr td(off) tf Fig 10b. Switching Time Waveforms VDS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % R D VGS RG D.U.T. 10V -VDD Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case Fig 9. Maximum Drain Current Vs. Case Temperature 25 50 75 100 125 150 T , Case Temperature( C) I , Drain Current (A) D LIMITED BY PACKAGE 0.01 0.1 Notes: 1. Duty factor D =t / t 2. Peak T= P x Z + T 1 2 J DM thJC C P t t DM t , Rectangular Pulse Duration (sec) Thermal Response (Z ) thJC 0.01 0.02 0.05 0.10 0.20 D = 0.50 SINGLE PULSE (THERMAL RESPONSE)
Fig 12a. Unclamped Inductive Test Circuit Fig 12b. Unclamped Inductive Waveforms VDS L D.U.T. VDD IAS tp 0.01Ω R G + tp VDS IAS VDD V(BR)DSS 10 V Q G Q GS Q GD VG Charge D.U.T. VDS IDIG 3mA VGS .3µF 50KΩ .2µF12V Current Regulator Same Type as D.U.T. Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 13b. Gate Charge Test Circuit 10 V 25 50 75 100 125 150 100 150 200 Starting T , Junction Temperature( C) E , Single Pulse Avalanche Energy (mJ) J AS ID TOP BOTTOM 8.0A 11A 18A
P.W. Period di/dt Diode Recovery dv/dt Ripple ≤ 5% Body Diode Forward Drop Re-Applied Voltage Reverse Recovery Current Body Diode Forward Current VGS =10V VDD ISD Driver Gate Drive D.U.T. ISD Waveform D.U.T. VDS Waveform Inductor Curent D = P.W . Period * VGS = 5V for Logic Level Devices RG VDD
- dv/dt controlled by RG
- Driver same type as D.U.T.
- ISD controlled by Duty Factor "D"
- D.U.T. - Device Under Test D.U.T Circuit Layout Considerations
- Low Stray Inductance
- Ground Plane
- Low Leakage Inductance Current Transformer Fig 14. For N-Channel HEXFETS Peak Diode Recovery dv/dt Test Circuit
Dimensions are shown in millimeters (inches) TO-252AA (D-Pak) Part Marking Information 6.73 (.265) 6.35 (.250) - A - 1 2 3 6.22 (.245) 5.97 (.235) - B - 3X 0.89 (.035) 0.64 (.025) 0.25 (.010) M A M B 4.57 (.180) 2.28 (.090) 2X 1.14 (.045) 0.76 (.030) 1.52 (.060) 1.15 (.045) 1.02 (.040) 1.64 (.025) 5.46 (.215) 5.21 (.205) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) 0.51 (.020) MIN. 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - G ATE 2 - DRA IN 3 - S OUR CE 4 - DRA IN 10.42 (.410) 9.40 (.370) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006). INTERNATIONAL RECT IFIER LOGO ASSEMBLY LOT CODE EXAMPLE : THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 9U1P FIRST PORTION OF PART NUMBER SECOND PORTION OF PART NUMBER 120 IRFR 9U 1P A
Dimensions are shown in millimeters (inches) TO-251AA (I-Pak) Part Marking Information INTE RNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE FIRST PORTION OF PART NUMBER SECOND PORTION OF PART NUMBER 120 9U 1P EXAMPLE : THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 9U1P IRFU 6.73 (.265) 6.35 (.250) - A - 6.22 (.245) 5.97 (.235) - B - 3X 0.89 (.035) 0.64 (.025) 1.14 (.045) 0.76 (.030) 5.46 (.215) 5.21 (.205) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - G ATE 2 - DRA IN 3 - SOURCE 4 - DRA IN NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLI NG DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOW N ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006). 9.65 (.380) 8.89 (.350) 2.28 (.090) 1.91 (.075) 1.52 (.060) 1.15 (.045) 1 2 3 6.45 (.245) 5.68 (.224) 0.58 (.023) 0.46 (.018)
Tape & Reel Information TO-252AA TR 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( . 318 ) 7.9 ( . 312 ) 12. 1 ( .476 ) 11. 9 ( .469 ) FEED DIRECTION FEED DIRECTION 16.3 ( .641 ) 15.7 ( .619 ) TRR TRL NOTES : 1. CONTROLLING DIMENSI ON : MILLIMETER. 2. ALL DIMENSIONS ARE SHOW N IN MI LLI METERS ( I NCHES ) . 3. OUTLINE CONFORMS TO EI A-481 & EI A-541. NOTES : 1. OUTLI NE CONFORMS TO EIA-481. 16 mm
13 I NCH
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