TXS0102V-Q1 TI | Alldatasheet

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TXS0102V-Q1 Automotive 2-Bit Bi-Directional, Level-Shifting, Voltage Translator for Open-Drain and Push-Pull Applications

1 Features

  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results: – Device temperature grade 1: -40°C to + 125°C ambient operating temperature range – Device HBM ESD classification level 2 – Device CDM ESD classification level C5 – ESD protection per JESD 22:
  • A port: – 2000V Human-Body Model (A114-B) – 500V Charged-Device Model (C101)
  • B port: – 5000V Human-Body Model (A114-B) – 500V Charged-Device Model (C101)
  • No direction-control signal needed
  • Maximum data rates: – 24 Mbps (push pull) – 2 Mbps (open drain)
  • Available in the Texas Instruments NanoStar™ integrated circuit package
  • 1.65V to 3.6V on A port and 2.3V to 5.5V on B port (VCCA ≤ VCCB)
  • VCC isolation feature: if either VCC input is at GND, both ports are in the High-Impedance state
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II

2 Applications

  • I2C / SMBus
  • UART
  • GPIO

3 Description

This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power- supply rails, with the A ports supporting operating voltages from 1.65V to 3.6V while it tracks the V CCA supply, and the B ports supporting operating voltages from 2.3V to 5.5V while it tracks the V CCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes. When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption. To put the device in the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TXS0102V-Q1 DCU (VSSOP, 8) 2mm × 3.1mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Processor Peripheral VCCA VCCB Typical Application Block Diagram for TXS0102V-Q1 TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

1 B18

Figure 4-1. DCU Package, 8-Pin VSSOP (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. A1 5 I/O Input/output A. Referenced to VCCA. A2 4 I/O Input/output A. Referenced to VCCA. B1 8 I/O Input/output B. Referenced to VCCB. B2 1 I/O Input/output B. Referenced to VCCB. GND 2 — Ground OE 6 I Output enable (active High). Pull OE low to place all outputs in 3-state mode. Referenced to VCCA. VCCA 3 P A-port supply voltage. 1.65V ≤ VCCA ≤ 3.6V and VCCA ≤ VCCB VCCB 7 P B-port supply voltage. 2.3V ≤ VCCB ≤ 5.5V (1) I = input, O = output, I/O = input and output, P = power www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TXS0102V-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA Supply voltage A –0.5 4.6 V VCCB Supply voltage B –0.5 6.5 V VI Input Voltage(2) I/O Ports (A Port) –0.5 4.6 V I/O Ports (B Port) –0.5 6.5 VO Voltage applied to any output in the high-impedance or power-off state(2) A Port –0.5 4.6 V B Port –0.5 6.5 VO Voltage applied to any output in the high or low state(2) (3) A Port –0.5 VCCA + 0.5 V B Port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Section 5.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 Exposure beyond the limits listed in Section 5.3 may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) A Port ±2000 V B Port ±5000 Charged device model (CDM), per AEC Q100-011 A Port ±500 B Port ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3) VCCA VCCB MIN MAX UNIT VCCA Supply voltage A 1.65 3.6 V VCCB Supply voltage B 2.3 5.5 V VIH High-level input voltage A-port I/O's 1.65 V to 1.95 V 2.3 V to 5.5 V VCCI - 0.2 VCCI V 1.65 V to 3.6 V VCCI - 0.4 VCCI B-port I/O's 1.65 V to 3.6 V 2.3 V to 5.5 V VCCI - 0.4 VCCI OE Input 1.65 V to 3.6 V VCCA x 0.65 5.5 VIL Low-level input voltage A-port I/O's 1.65 V to 3.6 V 2.3 V to 5.5 V 0.15 VB-port I/O's 1.65 V to 3.6 V 0.15 OE Input 1.65 V to 3.6 V VCCA x 0.35 Δt/Δv Input transition rise and fall time Push-Pull Driving 1.65 V to 3.6 V 2.3 V to 5.5 V 10 ns/V TA Operating free-air temperature –40 125 °C (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the device. The input leakage from these weak pulldowns is defined by the II specification indicated under Section 5.5. TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) TXS0102V-Q1 UNITDCU

8 PINS

RθJA Junction-to-ambient thermal resistance 239.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 88.5 °C/W RθJB Junction-to-board thermal resistance 151.6 °C/W YJT Junction-to-top characterization parameter 30.9 °C/W YJB Junction-to-board characterization parameter 150.5 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT25°C –40°C to 85°C –40°C to 125°C MIN TYP MAX MIN TYP MAX MIN TYP MAX VOHA Port A output high voltage (3) IOH = –20 uA 1.65 V to 3.6 V 2.3 V to 5.5 V 0.67 x VCC A 0.67 x VCC A 0.67 x VCC A V VOLA Port A output low voltage (4) IOL = 1 mA 1.65 V to 3.6 VOHB Port B output high voltage 1.65 V to 3.6 V 2.3 V to 5.5 V 0.67 x VCC B 0.67 x VCC B 0.67 x VCC B V VOLB Port B output low voltage (4) 1.65 V to 3.6 II Input leakage current OE VI = VCC or GND 1.65 V to 3.6 V 2.3 V to 5.5 V 1 2 2 µA Ioff Partial power down current A port 0 V 0 V to 5.5 V 1 2 2 µA B port 0 V to 3.6 V 0 V 1 2 2 µA IOZ Tri-state output current A or B Port: VI = VCCI or GND VO = VCCO or GND OE = GND 1.65 V to 3.6 V 2.3 V to 5.5 V –2 2 –2 2 –3 3 µA ICCA VCCA supply current VI = VCCI or GND IO = 0

1.65 V to

2.3 V to 5.5 V 3 3 5 µA0 V 5.5 V –3 –3 –3 3.6 V 0 V 2.2 2.2 2.2 ICCB VCCB supply current VI = VCCI or GND IO = 0 2.3 V to 5.5 V 12 12 21 µA0 V 5.5 V 5 5 8

3.6 V 0 V –1 –1 –1

VI = VCCI or GND IO = 0 2.3 V to 5.5 V 14.4 14.4 25 µA Ci Input Cio A or B port OE = GND, VO = 1.65V DC +1 MHz -16 dBm sine wave 3.3 V 3.3 V 10 pFA port 5 6 6 B port 6 7.5 7.5 (1) VCCI is the VCC associated with the input port (2) VCCO is the VCC associated with the output port (3) Tested at VI = VT+(MAX) (4) Tested at VI = VT-(MIN) www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TXS0102V-Q1

5.6 Switching Characteristics, VCCA = 1.8 ± 0.15 V PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX tPHL Propagation Delay (Hight-to-Low) A B Push-Pull 5 5 6 ns Open-Drain 8.8 9.6 10 tPLH Propagation Delay (Low-to-High) A B Push-Pull 6.5 7 7 ns Open-Drain 250 200 185 tPHL Propagation Delay (Hight-to-Low) B A Push-Pull 4 4 5 ns Open-Drain 5.3 4.4 4 tPLH Propagation Delay (Low-to-High) B A Push-Pull 5 4 1 ns Open-Drain 173 89 66 ten Enable Time OE A or B -40°C to 125°C 200 200 200 ns tdis Disable Time 250 250 250 trA Ouput Rise Time B A Push-Pull 9 9 7 ns Open-Drain 150 120 80 trB Ouput Rise Time A B Push-Pull 10 9 7 ns Open-Drain 145 106 58 tfA Output Fall Time B A Push-Pull 5 6 13 ns Open-Drain 6 6 6 tfB Output Fall Time A B Push-Pull 7 7 8 ns Open-Drain 13 16 16 5.7 Switching Characteristics, VCCA = 2.5 ± 0.2 V PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX tPHL Propagation Delay (Hight-to-Low) A B Push-Pull 3.2 3.7 5 ns Open-Drain 6.3 6 5.8 tPLH Propagation Delay (Low-to-High) A B Push-Pull 3 4 4 ns Open-Drain 200 200 190 tPHL Propagation Delay (Hight-to-Low) B A Push-Pull 3 3 4 ns Open-Drain 4.7 4.2 4 tPLH Propagation Delay (Low-to-High) B A Push-Pull 2.1 1.6 1 ns Open-Drain 170 140 103 ten Enable Time OE A or B -40°C to 125°C 200 200 200 ns tdis Disable Time 250 250 250 trA Ouput Rise Time B A Push-Pull 7 6 5 ns Open-Drain 156 120 80 trB Ouput Rise Time A B Push-Pull 8 7 6 ns Open-Drain 151 112 64 tfA Output Fall Time B A Push-Pull 5.1 5.2 5 ns Open-Drain 6 6 5 tfB Output Fall Time A B Push-Pull 7 6.4 8.7 ns Open-Drain 8 9 10 TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

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5.8 Switching Characteristics, VCCA = 3.3 ± 0.3 V PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) UNIT3.3 ± 0.3 V 5.0 ± 0.5 V MIN TYP MAX MIN TYP MAX tPHL Propagation Delay (Hight- to-Low) A B Push-Pull 2.4 3.1 ns Open-Drain 4.2 4.6 tPLH Propagation Delay (Low- to-High) A B Push-Pull 4 4 ns Open-Drain 204 165 tPHL Propagation Delay (Hight- to-Low) B A Push-Pull 2.5 3.3 ns Open-Drain 124 97 tPLH Propagation Delay (Low- to-High) B A Push-Pull 2.5 2.6 ns Open-Drain 139 105 ten Enable Time OE A or B -40°C to 125°C 200 200 ns tdis Disable Time 250 250 trA Ouput Rise Time B A Push-Pull 5 4 ns Open-Drain 116 85 trB Ouput Rise Time A B Push-Pull 6 7 ns Open-Drain 117 116 tfA Output Fall Time B A Push-Pull 5.4 5 ns Open-Drain 6 5 tfB Output Fall Time A B Push-Pull 7.4 7.6 ns Open-Drain 7 8

5.9 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Push-Pull Driving 1.8 ± 0.15 V 2.5 V ± 0.2 V 18 Mbps3.3 V ± 0.3 V 21 5 V ± 0.5 V 23 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Push-Pull Driving 2.5 V ± 0.2 V 2.5 V ± 0.2 V 20 Mbps3.3 V ± 0.3 V 22 5 V ± 0.5 V 24 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Push-Pull Driving 3.3 V ± 0.3 V 3.3 V ± 0.3 V 22 Mbps 5 V ± 0.5 V 24 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Open-Drain Driving 1.8 ± 0.15 V 2.5 V ± 0.2 V 2 Mbps3.3 V ± 0.3 V 2 5 V ± 0.5 V 2 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Open-Drain Driving 2.5 V ± 0.2 V 2.5 V ± 0.2 V 2 Mbps3.3 V ± 0.3 V 2 5 V ± 0.5 V 2 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Open-Drain Driving 3.3 V ± 0.3 V 3.3 V ± 0.3 V 2 Mbps 5 V ± 0.5 V 2 tw Pulse Duration, Data Inputs Push-Pull Driving 1.8 V ± 0.15 V to 3.3 V ± 0.3 V 2.5 V ± 0.2 V 5.0 V ± 0.5 V 41 ns tw Pulse Duration, Data Inputs Open-Drain Driving 1.8 V ± 0.15 V to 3.3 V ± 0.3 V 2.5 V ± 0.2 V 5.0 V ± 0.5 V 500 ns www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TXS0102V-Q1

5.9 Switching Characteristics: Tsk, TMAX (continued)

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX tsk - Output skew Skew between any two outputs of the same package switching in the same direction Push-Pull Driving 1.8 V ± 0.15 V to 3.3 V ± 0.3 V 2.5 V ± 0.2 V 5.0 V ± 0.5 V 1 ns tsk - Output skew Skew between any two outputs of the same package switching in the same direction Open-Drain Driving 1.8 V ± 0.15 V to 3.3 V ± 0.3 V 2.5 V ± 0.2 V 5.0 V ± 0.5 V 1 ns TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

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5.10 Typical Characteristics

Figure 5-1. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx)) Figure 5-2. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx)) Figure 5-3. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx)) www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TXS0102V-Q1

6 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

  • PRR 10MHz
  • ZO = 50 W
  • dv/dt ≥ 1V/ns Note All parameters and waveforms are not applicable to all devices. DUT IN OUT 15 pF 1 M VCCI VCCO Figure 6-1. Data Rate, Pulse Duration, Propagation Delay, Output Rise And Fall Time Measurement Using A Push-Pull Driver DUT IN OUT 15 pF 1 M VCCI VCCO Figure 6-2. Data Rate, Pulse Duration, Propagation Delay, Output Rise And Fall Time Measurement Using An Open-Drain Driver From Output Under Test 15 pF 50 k 50 k Open 2 x VCCO Figure 6-3. Load Circuit For Enable / Disable Time Measurement Table 6-1. Switch Configuration For Enable / Disable Timing TEST S1 tPZL (2), tPLZ (1) 2 × VCCO tPHZ (1), tPZH (2) Open (1) tPLZ and tPHZ are the same as tdis. (2) tPZL and tPZH are the same as ten. TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The TXS0102V-Q1 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A port can accept I/O voltages ranging from 1.65V to 3.6V, while the B port can accept I/O voltages from 2.3V to 5.5V. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to improve the overall data rate. 10k Ω pullup resistors, commonly used in open-drain applications, have been conveniently integrated so that an external resistor is not needed. While this device is designed for open-drain applications, the device can also translate push-pull CMOS logic outputs.

7.2 Functional Block Diagram

10 NŸ One Shot Accelerator 10 NŸ

10 NŸ10 NŸ

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7.3 Feature Description

7.3.1 Architecture

The TXS0102V-Q1 architecture (see Figure 7-1 ) is an auto-direction-sensing based translator that does not require a direction-control signal to control the direction of data flow from A to B or from B to A. B Gate Bias One shot T2T1 VCCA VCCB A Gate Bias One- shot 10k 10k One shot One- shot Figure 7-1. Architecture of a TXS0102V-Q1 Cell These two bidirectional channels independently determine the direction of data flow without a direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is how this auto-direction feature is realized. The TXS0102V-Q1 device is part of TI's "Switch" type voltage translator family and employs two key circuits to enable this voltage translation: 1. An N-channel pass-gate transistor topology that ties the A-port to the B-port 2. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B ports For bidirectional voltage translation, pull-up resistors are included on the device for dc current sourcing capability. The V GATE gate bias of the N-channel pass transistor is set at approximately one threshold voltage (VT) above the VCC level of the low-voltage side. Data can flow in either direction without guidance from a control signal. The O.S. rising-edge rate accelerator circuitry speeds up the output slew rate by monitoring the input edge for transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S. circuits turn on the PMOS transistors (T1 and T2) to increase the current drive capability of the driver for approximately 30ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal 10k Ω pull-up resistors during the low-to-high transition to speed up the signal. The output resistance of the driver is decreased to approximately 50 Ω to 70Ω during this acceleration phase. To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width number provided in the Section 5.6 section of this data sheet. www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TXS0102V-Q1

7.3.2 Input Driver Requirements

the external system-level open-drain (or push-pull) drivers that are interfaced to the TXS0102V-Q1 I/O pins determines the continuous dc-current sinking capability. Since the high bandwidth of these bidirectional I/O circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a modest dc-current sourcing capability of hundreds of micro-Amps, as determined by the internal 10k Ω pullup resistors. The fall time (t fA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving TXS0102V-Q1 data I/Os, as well as the capacitive loading on the data lines. Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50Ω.

7.3.3 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to determine that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough so that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by allowing any reflection sees a low impedance at the driver. The O.S. circuits are designed to stay on for approximately 30ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXS0102V-Q1 device output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.

7.3.4 Enable and Disable

The TXS0102V-Q1 device has an OE input that is used to disable the device by setting OE low, which places all I/Os in the Hi-Z state. The disable time (t dis) indicates the delay between the time when OE goes low and when the outputs are disabled (Hi-Z). The enable time (t en) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

7.3.5 Pullup or Pulldown Resistors on I/O Lines

Each A-port I/O has an internal 10k Ω pullup resistor to V CCA, and each B-port I/O has an internal 10k Ω pullup resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O to VCCA or VCCB (in parallel with the internal 10k Ω resistors). Adding lower value pull-up resistors will effect V OL levels, however. The internal pull-ups of the TXS0102V-Q1 are disabled when the OE pin is low.

7.4 Device Functional Modes

The device has two functional modes, enabled and disabled. To disable the device set the OE input low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device. TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TXS0102V-Q1 device can be used to bridge the digital-switching compatibility gap between two voltage nodes to successfully interface logic threshold levels found in electronic systems. It should be used in a point-to- point topology for interfacing devices or systems operating at different interface voltages with one another. Its primary target application use is for interfacing with open-drain drivers on the data I/Os such as I 2C or 1-wire, where the data is bidirectional and no control signal is available. The device can also be used in applications where a push-pull driver is connected to the data I/Os, but the TXB0102 might be a better option for such push-pull applications.

8.2 Typical Application

TXS0102V-Q1 3.3V System 1.8V System Controller Data Data OE VCCA VCCB 1.8V 3.3V GND 0.1μF 0.1μF Figure 8-1. Typical Application Circuit

8.2.1 Design Requirements

Use the parameters listed in Table 8-1 for this design example, and ensure the VCCA ≤ VCCB. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.65 to 3.6V Output voltage range 2.3 to 5.5V www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TXS0102V-Q1

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range – Use the supply voltage of the device that is driving the TXS0102V-Q1 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
  • Output voltage range – Use the supply voltage of the device that the TXS0102V-Q1 device is driving to determine the output voltage range. – The TXS0102V-Q1 device has 10kΩ internal pullup resistors. External pullup resistors can be added to reduce the total RC of a signal trace if necessary.
  • An external pull down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a result of an external pull down resistor. – V O H = V C Cx × R P D / R P D + 10 k Ω (1)
  • Where:
  • VCCx is the supply voltage on either VCCA or VCCB
  • RPD is the value of the external pull down resistor

8.2.3 Application Curves

Figure 8-2. Level-Translation of a 2.5MHz Signal

8.3 Power Supply Recommendations

During operation, ensure that V CCA ≤ VCCB at all times. The sequencing of each power supply will not damage the device during the power up operation, so either power supply can be ramped up first. The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To put the outputs in the high-impedance state during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until V CCA and VCCB are fully ramped and stable. The current-sourcing capability of the driver determines the minimum value of the pulldown resistor to ground. TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

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8.4 Layout

8.4.1 Layout Guidelines

For device reliability, it is recommended to follow common printed-circuit board layout guidelines such as follows:

  • Bypass capacitors should be used on power supplies and should be placed as close as possible to the VCCA, VCCB pin, and GND pin.
  • Short trace lengths should be used to avoid excessive loading.
  • PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 30ns, causing any reflection encounters low impedance at the source driver.

8.4.2 Layout Example

0.1 μFTo System To Controller Bypass Capacitor B2 B1 GND VCCA VCCB OE To System To Controller LEGEND Polygonal Copper Pour VIA to Power Plane VIA to GND Plane (Inner Layer)

6 Keep OE low until VCCA

Capacitor 0.1 µF Figure 8-3. TXS0102V-Q1 Layout Example www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TXS0102V-Q1

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:

  • Texas Instruments, A Guide to Voltage Translation With TXS-Type Translators application note
  • Texas Instruments, Factors Affecting VOL for TXS and LSF Auto-bidirectional Translation Devices application note
  • Texas Instruments, Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators application note
  • Texas Instruments, Effects of pullup and pulldown resistors on TXS and TXB devices application note
  • Texas Instruments, Introduction to logic application note
  • Texas Instruments, TI Logic and Linear Products Guide selection and solution guides
  • Texas Instruments, Washing Machine Solutions Guide selection and solution guides
  • Texas Instruments, TI Smartphone Solutions Guide selection and solution guides

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

NanoStar™ is a trademark of Texas Instruments Incorporated. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2024) to Revision A (September 2024) Page DATE REVISION NOTES June 2024 * Initial Release TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 www.ti.com

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: TXS0102V-Q1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TXS0102V-Q1 SCES973A – JUNE 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TXS0102V-Q1

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TXS0102VQDCURQ1 Active Production VSSOP (DCU) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TXS0102VQDCURQ1.A Active Production VSSOP (DCU) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXS0102V-Q1 :

  • Catalog : TXS0102V Addendum-Page 1

www.ti.com 23-May-2025 NOTE: Qualified Version Definitions:

  • Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXS0102VQDCURQ1 VSSOP DCU 8 3000 180.0 180.0 18.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 6X 0.5 1.5 8X 0.25 0.17 3.2

3.0 TYP

0.1 0.0 0.12 GAGE PLANE 0 -6 0.9 0.6 B 2.4 2.2 NOTE 3 A 2.1 1.9 NOTE 3 0.35 0.20 (0.13) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 4 5

0.08 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-187 variation CA. A 30 DETAIL A TYPICAL SCALE 6.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (0.85) 8X (0.3) 6X (0.5) (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X SYMM SYMM 4 5 SEE SOLDER MASK DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (0.85) 8X (0.3) 6X (0.5) (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 25X SYMM SYMM 4 5

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