TXS0102_V01 TI | Alldatasheet
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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TXS0102 SCES640I –JANUARY 2007–REVISED OCTOBER 2018 TXS01022-BitBidirectionalVoltage-LevelTranslatorforOpen-DrainandPush-Pull
Applications
1 Features
1• No Direction-Control Signal Needed
- Maximum Data Rates – 24 Mbps (Push Pull) – 2 Mbps (Open Drain)
- Available in the Texas Instruments NanoStar™ Package
- 1.65 V to 3.6 V on A Port and 2.3 V to 5.5 V on B Port (VCCA ≤ VCCB)
- VCC Isolation Feature: If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
- No Power-Supply Sequencing Required: Either VCCA or VCCB Can Be Ramped First
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22 – A Port: – 2500-V Human-Body Model (A114-B) – 250-V Machine Model (A115-A) – 1500-V Charged-Device Model (C101) – B Port: – 8-kV Human-Body Model (A114-B) – 250-V Machine Model (A115-A) – 1500-V Charged-Device Model (C101)
2 Applications
- I2C / SMBus
- UART
- GPIO
3 Description
This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power- supply rails, with the A ports supporting operating voltages from 1.65 V to 3.6 V while it tracks the VCCA supply, and the B ports supporting operating voltages from 2.3 V to 5.5 V while it tracks the VCCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TXS0102DCT SSOP (8) 2.95 mm × 2.80 mm TXS0102DCU VSSOP (8) 2.30 mm × 2.00 mm TXS0102DQE X2SON (8) 1.40 mm × 1.00 mm TXS0102DQM X2SON (8) 1.80 mm × 1.20 mm TXS0102YZP DSBGA (8) 1.90 mm × 0.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Block Diagram for TXS0102
SCES640I –JANUARY 2007–REVISED OCTOBER 2018 www.ti.com Product Folder Links: TXS0102 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation Updates 20
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (April 2018) to Revision I Page
- Updated the VIH A-port I/O VCCA value in the Recommended Operating Conditions table From: "1.65 V to 3.6 V", To: Changes from Revision G (January 2018) to Revision H Page Changes from Revision F (August 2014) to Revision G Page
8 B11B2 A1
1 B18
www.ti.com SCES640I –JANUARY 2007–REVISED OCTOBER 2018 Product Folder Links: TXS0102 Submit Documentation FeedbackCopyright © 2007–2018, Texas Instruments Incorporated (1) I = input, O = output, I/O = input and output, P = power
5 Pin Configuration and Functions
TYPE(1) DESCRIPTION NAME NO. DCT, DCU DQE, DQM YZP B2 1 6 A1 I/O Input/output B. Referenced to VCCB. GND 2 4 B1 — Ground VCCA 3 1 C1 P A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB A2 4 3 D1 I/O Input/output A. Referenced to VCCA. A1 5 2 D2 I/O Input/output A. Referenced to VCCA. OE 6 5 C2 I Output enable (active High). Pull OE low to place all outputs in 3-state mode. Referenced to VCCA. VCCB 7 8 B2 P B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V B1 8 7 A2 I/O Input/output B. Referenced to VCCB.
SCES640I –JANUARY 2007–REVISED OCTOBER 2018 www.ti.com Product Folder Links: TXS0102 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCCA and VCCB are provided in the recommended operating conditions table.
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage range, VCCA –0.5 4.6 V Supply voltage range, VCCB –0.5 6.5 V Input voltage range, VI(2) A port –0.5 4.6 V B port –0.5 6.5 Voltage range applied to any output in the high-impedance or power-off state, VO(2) A port –0.5 4.6 V B port –0.5 6.5 Voltage range applied to any output in the high or low state, VO(2)(3) A port –0.5 VCCA + 0.5 V B port –0.5 VCCB + 0.5 Input clamp current, IIK VI < 0 –50 mA Output clamp current, IOK VO < 0 –50 mA Continuous output current, IO ±50 mA Continuous current through VCCA, VCCB, or GND ±100 mA Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins, A Port(1) ±2500 V Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins, B Port(1) ±8000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 V 250-V Machine Model (A115-A), all pins ±250 V
www.ti.com SCES640I –JANUARY 2007–REVISED OCTOBER 2018 Product Folder Links: TXS0102 Submit Documentation FeedbackCopyright © 2007–2018, Texas Instruments Incorporated (1) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V. (2) The maximum VIL value is provided to ensure that a valid VOL is maintained. The VOL value is VIL plus the voltage drop across the pass- gate transistor.
6.3 Recommended Operating Conditions
VCCI is the supply voltage associated with the input port. VCCO is the supply voltage associated with the output port. MIN MAX UNIT VCCA Supply voltage(1) 1.65 3.6 V VCCB Supply voltage 2.3 5.5 V VIH High-level input voltage A-port I/Os VCCA = 1.65 V to 1.95 V VCCB = 2.3 V to 5.5 V VCCI – 0.2 VCCI V VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V VCCI – 0.4 VCCI B-port I/Os VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V VCCI – 0.4 VCCI V OE input VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V VCCA × 0.65 5.5 V VIL(2) Low-level input voltage A-port I/Os VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V 0 0.15 V B-port I/Os VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V 0 0.15 V OE input VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V 0 VCCA × 0.35 V Δt/Δv Input transition rise or fall rate A-port I/Os push-pull driving VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V 10 ns/V B-port I/Os push-pull driving VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V 10 ns/V Control input VCCA = 1.65 V to 3.6 V VCCB = 2.3 V to 5.5 V 10 ns/V TA Operating free-air temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC(1) TXS0102 UNITDCT DCU DQE DQM YZP
8 PINS 8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal RθJC(top) Junction-to-case (top) thermal RθJB Junction-to-board thermal ψJT Junction-to-top characterization ψJB Junction-to-board characterization RθJC(bot) Junction-to-case (bottom) thermal resistance — — — — — °C/W
SCES640I –JANUARY 2007–REVISED OCTOBER 2018 www.ti.com Product Folder Links: TXS0102 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port (3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)(1) (2) (3) PARAMETER TEST CONDITIONS VCCA VCCB TA = 25°C TA = –40°C to +85°C UNIT MIN TYP MAX MIN TYP MAX VOHA Port A output high voltage IOH = –20 µA VOLA Port A output low voltage IOL = 1 mA VOHB Port B output VOLB Port B output II Input leakage current OE 1.65 V to 3.6 V 2.3 V to 5.5 V ±1 ±2 µAIoff Partial power down current A port 0 V 0 V to 5.5 V ±1 ±2 B port 0 V to 3.6 V 0 V ±1 ±2 IOZ High-impedance state output current A or B port 1.65 V to 3.6 V 2.3 V to 5.5 V ±1 ±2 ICCA VCCA supply current VI = VO = open IO = 0 1.65 V to VCCB 2.3 V to 5.5 V 2.4 µA3.6 V 0 V 2.2 0 V 5.5 V –1 ICCB VCCB supply current VI = VO = open IO = 0 1.65 V to VCCB 2.3 V to 5.5 V 12 µA3.6 V 0 V –1 0 V 5.5 V 1 ICCA ICCB Combined supply current VI = VCCI or GND IO = 0 1.65 V to VCCB 2.3 V to 5.5 V 14.4 µA CI Input capacitance OE 3.3 V 3.3 V 2.5 3.5 pF Cio Input-to-output internal capacitance A or B port 3.3 V 3.3 V 10 pFA port 5 6 B port 6 7.5
www.ti.com SCES640I –JANUARY 2007–REVISED OCTOBER 2018 Product Folder Links: TXS0102 Submit Documentation FeedbackCopyright © 2007–2018, Texas Instruments Incorporated 6.6 Timing Requirements: VCCA = 1.8 V ±0.15 V UNIT MIN MAX MIN MAX MIN MAX Data rate Push-pull driving 21 22 24 Mbps Open-drain driving 2 2 2 tw Pulse duration Push-pull driving (data inputs) 47 45 41 ns Open-drain driving (data inputs) 500 500 500 6.7 Timing Requirements: VCCA = 2.5 V ± 0.2 V UNIT MIN MAX MIN MAX MIN MAX Data rate Push-pull driving 20 22 24 Mbps Open-drain driving 2 2 2 tw Pulse duration Push-pull driving (data inputs) 50 45 41 ns Open-drain driving (data inputs) 500 500 500 6.8 Timing Requirements: VCCA = 3.3 V ± 0.3 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX Data rate Push-pull driving 23 24 Mbps Open-drain driving 2 2 tw Pulse duration Push-pull driving (data inputs) 43 41 ns Open-drain driving (data inputs) 500 500
SCES640I –JANUARY 2007–REVISED OCTOBER 2018 www.ti.com Product Folder Links: TXS0102 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated 6.9 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX MIN MAX tPHL Propagation delay time high-to-low output A-to-B Push-pull driving 5.3 5.4 6.8 ns tPLH Propagation delay time low-to-high output A-to-B Push-pull driving 6.8 7.1 7.5 ns Open-drain driving 45 260 36 208 27 198 tPHL Propagation delay time high-to-low output B-to-A Push-pull driving 4.4 4.5 4.7 ns tPLH Propagation delay time low-to-high output B-to-A Push-pull driving 5.3 4.5 0.5 ns Open-drain driving 45 175 36 140 27 102 ten Enable time OE-to-A or B 200 200 200 ns tdis Disable time OE-to-A or B 50 40 35 ns trA Input rise time A port rise time ns Open-drain driving 38 165 30 132 22 95 trB Input rise time B port rise time ns Open-drain driving 34 145 23 106 10 58 tfA Input fall time A port fall time Push-pull driving 2 5.9 1.9 6 1.7 13.3 ns tfB Input fall time B port fall time ns tSK(O) Skew (time), output Channel -to- channel skew 0.7 0.7 0.7 ns Maximum data rate Push-pull driving 21 22 24 Mbps Open-drain driving 2 2 2
www.ti.com SCES640I –JANUARY 2007–REVISED OCTOBER 2018 Product Folder Links: TXS0102 Submit Documentation FeedbackCopyright © 2007–2018, Texas Instruments Incorporated 6.10 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX MIN MAX tPHL Propagation delay time high-to-low output A-to-B Push-pull driving 3.2 3.7 3.8 nsOpen-drain driving 1.7 6.3 2 6 2.1 5.8 tPLH Propagation delay time low-to-high output A-to-B Push-pull driving 3.5 4.1 4.4 nsOpen-drain driving 43 250 36 206 27 190 tPHL Propagation delay time high-to-low output B-to-A Push-pull driving 3 3.6 4.3 nsOpen-drain tPLH Propagation delay time low-to-high output B-to-A Push-pull driving 2.5 1.6 1 nsOpen-drain driving 44 170 37 140 27 103 ten Enable time OE-to-A or B 200 200 200 ns tdis Disable time OE-to-A or B 50 40 35 ns trA Input rise time A port rise time nsOpen-drain driving 3 149 28 121 24 89 trB Input rise time B port rise time nsOpen-drain driving 35 151 24 112 12 64 tfA Input fall time A port fall time nsOpen-drain tfB Input fall time B port fall time nsOpen-drain tSK(O) Skew (time), output Channel-to-channel skew 0.7 0.7 0.7 ns Maximum data rate Push-pull driving 20 22 24 MbpsOpen-drain driving 2 2 2
SCES640I –JANUARY 2007–REVISED OCTOBER 2018 www.ti.com Product Folder Links: TXS0102 Submit Documentation Feedback Copyright © 2007–2018, Texas Instruments Incorporated 6.11 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 3.3 V ±0.2 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX tPHL Propagation delay time high-to-low output A-to-B Push-pull driving 2.4 3.1 ns Open-drain driving 1.3 4.2 1.4 4.6 tPLH Propagation delay time low-to-high output A-to-B Push-pull driving 4.2 4.4 ns Open-drain driving 36 204 28 165 tPHL Propagation delay time high-to-low output B-to-A Push-pull driving 2.5 3.3 ns Open-drain driving 1 124 1 97 tPLH Propagation delay time low-to-high output B-to-A Push-pull driving 2.5 2.6 ns Open-drain driving 3 139 3 105 ten Enable time OE-to-A or B 200 200 ns tdis Disable time OE-to-A or B 40 35 ns trA Input rise time A port rise time Push-pull driving 2.3 5.6 1.9 4.8 ns Open-drain driving 25 116 19 85 trB Input rise time B port rise time Push-pull driving 2.5 6.4 2.1 7.4 ns Open-drain driving 26 116 14 72 tfA Input fall time A port fall time Push-pull driving 2 5.4 1.9 5 ns Open-drain driving 4.3 6.1 4.2 5.7 tfB Input fall time B port fall time Push-pull driving 2.3 7.4 2.4 7.6 ns Open-drain driving 5 7.6 4.8 8.3 tSK(O) Skew (time), output Channel-to-channel skew 0.7 0.7 ns Maximum data rate Push-pull driving 23 24 Mbps Open-drain driving 2 2
6.12 Typical Characteristics
Figure 1. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Figure 2. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Figure 3. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx))
(1) tPZL and tPZH are the same as ten. (2) tPLZ and tPHZ are the same as tdis.
7 Parameter Measurement Information
- PRR 10 MHz
- ZO = 50 W
- dv/dt ≥ 1 V/ns NOTE All parameters and waveforms are not applicable to all devices.
Figure 4. Data Rate, Pulse Duration, Propagation Delay, Output Rise Figure 5. Data Rate, Pulse Duration, Propagation Delay, Output Rise Figure 6. Load Circuit For Enable / Disable Time Measurement Table 1. Switch Configuration For Enable / Disable Timing
10 N One Shot Accelerator 10 N
10 N10 N
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8 Detailed Description
8.1 Overview
The TXS0102 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.65 V to 3.6 V, while the B port can accept I/O voltages from 2.3 V to 5.5 V. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to improve the overall data rate. 10-kΩ pullup resistors, commonly used in open-drain applications, have been conveniently integrated so that an external resistor is not needed. While this device is designed for open-drain applications, the device can also translate push-pull CMOS logic outputs.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Architecture
direction-control signal to control the direction of data flow from A to B or from B to A. Figure 10. Architecture of a TXS0102 Cell direction feature is realized. For bidirectional voltage translation, pull-up resistors are included on the device for dc current sourcing capability. the VCC level of the low-voltage side. Data can flow in either direction without guidance from a control signal. transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S. ac drive by bypassing the internal 10-kΩ pull-up resistors during the low-to-high transition to speed up the signal. number provided in the Timing Requirements section of this data sheet.
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8.3.2 Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or push- pull) drivers that are interfaced to the TXS0102 I/O pins. Since the high bandwidth of these bidirectional I/O circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup resistors. The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving TXS0102 data I/Os, as well as the capacitive loading on the data lines. Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50 Ω.
8.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXS0102 device output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.
8.3.4 Enable and Disable
The TXS0102 device has an OE input that is used to disable the device by setting OE low, which places all I/Os in the Hi-Z state. The disable time (tdis) indicates the delay between the time when OE goes low and when the outputs are disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the one- shot circuitry to become operational after OE is taken high.
8.3.5 Pullup or Pulldown Resistors on I/O Lines
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O to VCCA or VCCB (in parallel with the internal 10-kΩ resistors). Adding lower value pull-up resistors will effect VOL levels, however. The internal pull-ups of the TXS0102 are disabled when the OE pin is low.
8.4 Device Functional Modes
The device has two functional modes, enabled and disabled. To disable the device set the OE input low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 11. Typical Application Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3. And make sure the VCCA ≤ VCCB. Table 2. Design Parameters
9.2.2 Detailed Design Procedure
- Input voltage range - Use the supply voltage of the device that is driving the TXS0102 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
- Output voltage range - Use the supply voltage of the device that the TXS0102 device is driving to determine the output voltage range. - The TXS0102 device has 10-kΩ internal pullup resistors. External pullup resistors can be added to reduce the total RC of a signal trace if necessary.
- An external pull down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a result of an external pull down resistor. VOH = VCCx × RPD / (RPD + 10 kΩ) Where:
- VCCx is the supply voltage on either VCCA or VCCB
- RPD is the value of the external pull down resistor
9.2.3 Application Curves
Figure 12. Level-Translation of a 2.5-MHz Signal
6 Keep OE low until VCCA
10 Power Supply Recommendations
sourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
- Bypass capacitors should be used on power supplies and should be placed as close as possible to the VCCA, VCCB pin, and GND pin.
- Short trace lengths should be used to avoid excessive loading.
- PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the source driver.
11.2 Layout Example
Figure 13. TXS0102 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
- Texas Instruments, A Guide to Voltage Translation With TXS-Type Translators application note
- Texas Instruments, Factors Affecting VOL for TXS and LSF Auto-bidirectional Translation Devices application note
- Texas Instruments, Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators application note
- Texas Instruments, Effects of pullup and pulldown resistors on TXS and TXB devices application note
- Texas Instruments, Introduction to logic application note
- Texas Instruments, TI Logic and Linear Products Guide selection and solution guides
- Texas Instruments, Washing Machine Solutions Guide selection and solution guides
- Texas Instruments, TI Smartphone Solutions Guide selection and solution guides
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.4 Trademarks
NanoStar, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 30-Aug-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TXS0102DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFE (R, Z) TXS0102DCTRE4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFE (R, Z) TXS0102DCTT ACTIVE SM8 DCT 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFE (R, Z) TXS0102DCTTE4 ACTIVE SM8 DCT 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFE (R, Z) TXS0102DCTTG4 ACTIVE SM8 DCT 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFE (R, Z) TXS0102DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (FE, NFEQ, NFER) NZ TXS0102DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFER TXS0102DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (FE, NFEQ, NFER) NZ TXS0102DCUTG4 ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFER TXS0102DQER ACTIVE X2SON DQE 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 2H TXS0102DQMR ACTIVE X2SON DQM 8 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 2H (2H7, 2HR) (2HG, 2HH) TXS0102YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (2H, 2HN) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
www.ti.com 30-Aug-2021 Addendum-Page 2 RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXS0102 :
- Automotive : TXS0102-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXS0102DCTR SM8 DCT 8 3000 183.0 183.0 20.0 TXS0102DCTR SM8 DCT 8 3000 182.0 182.0 20.0 TXS0102DCTT SM8 DCT 8 250 182.0 182.0 20.0 TXS0102DCUR VSSOP DCU 8 3000 182.0 182.0 20.0 TXS0102DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0 TXS0102DCUTG4 VSSOP DCU 8 250 202.0 201.0 28.0 TXS0102DQER X2SON DQE 8 5000 202.0 201.0 28.0 TXS0102DQMR X2SON DQM 8 3000 202.0 201.0 28.0 TXS0102DQMR X2SON DQM 8 3000 184.0 184.0 19.0 TXS0102YZPR DSBGA YZP 8 3000 182.0 182.0 20.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 4.25
3.75 TYP
1.3 1.0 6X 0.65 8X 0.30 0.15 1.95 (0.15) TYP 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.2 A 3.15 2.75 NOTE 3 B 2.9 2.7 NOTE 4 4220784/C 06/2021 SSOP - 1.3 mm max heightDCT0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 1 8
0.13 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.500
www.ti.com EXAMPLE BOARD LAYOUT (3.8)
0.07 MAX
0.07 MIN
8X (1.1) 8X (0.4) 6X (0.65) (R0.05) TYP 4220784/C 06/2021 SSOP - 1.3 mm max heightDCT0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (3.8) 6X (0.65) 8X (0.4) 8X (1.1) 4220784/C 06/2021 SSOP - 1.3 mm max heightDCT0008A SMALL OUTLINE PACKAGE NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X
www.ti.com PACKAGE OUTLINE C 1.05 0.95 1.45 1.35 0.40 0.34 0.05 0.00 2X 1.05 6X 0.35 7X 0.35 0.25 8X 0.20 0.15 0.45 0.35 (0.13) TYP X2SON - 0.4 mm max heightDQE0008A PLASTIC SMALL OUTLINE - NO LEAD 4225204/A 08/2019 0.05 C
0.07 C A B
0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package complies to JEDEC MO-287 variation X2EAF. PIN 1 INDEX AREA SEATING PLANE 0.05 C PIN 1 ID SYMM SYMM 4 5 SCALE 9.000 AB
www.ti.com EXAMPLE BOARD LAYOUT 6X (0.35) (R0.05) TYP
0.05 MAX
0.05 MIN
7X (0.5) 8X (0.175) (0.9) (0.6) X2SON - 0.4 mm max heightDQE0008A PLASTIC SMALL OUTLINE - NO LEAD 4225204/A 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 40X SEE SOLDER MASK DETAIL 4 5 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN 7X (0.5) 8X (0.175) 6X (0.35) (0.9) (R0.05) TYP (0.6) X2SON - 0.4 mm max heightDQE0008A PLASTIC SMALL OUTLINE - NO LEAD 4225204/A 08/2019 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.075 MM THICK STENCIL SCALE: 40X SYMM SYMM 4 5
www.ti.com PACKAGE OUTLINE C
0.5 MAX
0.19 0.15 1.5 TYP
0.5 TYP
8X 0.25 0.21 0.5 TYP B E A D 4223082/A 07/2016 DSBGA - 0.5 mm max heightYZP0008 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C B 1 2
0.015 C A B
C A D SCALE 8.000 D: Max = E: Max = 1.918 mm, Min = 0.918 mm, Min = 1.858 mm 0.858 mm
www.ti.com EXAMPLE BOARD LAYOUT 8X ( 0.23) (0.5) TYP (0.5) TYP ( 0.23) METAL 0.05 MAX ( 0.23) SOLDER MASK OPENING DSBGA - 0.5 mm max heightYZP0008 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE SCALE:40X 1 2 A B C D NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING SOLDER MASK DEFINED METAL UNDER SOLDER MASK
www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP METAL TYP 4223082/A 07/2016 DSBGA - 0.5 mm max heightYZP0008 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 1 2 A B C D
www.ti.com PACKAGE OUTLINE C 6X 0.5 1.5 8X 0.25 0.17 3.2
3.0 TYP
0.1 0.0 0.12 GAGE PLANE 0 -6 0.9 0.6 B 2.4 2.2 NOTE 3 A 2.1 1.9 NOTE 3 0.35 0.20 (0.13) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 4 5
0.08 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-187 variation CA. A 30 DETAIL A TYPICAL SCALE 6.000
www.ti.com EXAMPLE BOARD LAYOUT 8X (0.85) 8X (0.3) 6X (0.5) (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X SYMM SYMM 4 5 SEE SOLDER MASK DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (0.85) 8X (0.3) 6X (0.5) (3.1) (R0.05) TYP VSSOP - 0.9 mm max heightDCU0008A SMALL OUTLINE PACKAGE 4225266/A 09/2014 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 25X SYMM SYMM 4 5
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