TXS0101DCKT

TXS0101_V01 TI | Alldatasheet

Document overview

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Technical content

TXS0101 1-Bit Bidirectional Level-Shifting, Voltage-Level Translator With Auto- Direction-Sensing for Open-Drain and Push-Pull Applications

1 Features

• Latch-up performance exceeds 100mA per JESD 78, class II
• ESD protection exceeds JESD 22: – A Port:
• 2500V Human-Body Model (A114-B)
• 200V Machine Model (A115-A)
• 1500V Charged-Device Model (C101) – B port:
• 8kV Human-Body Model (A114-B)
• 200V Machine Model (A115-A)
• 1500V Charged-Device Model (C101)
• No direction-control signal needed
• Maximum data rates: – 24Mbps (push pull) – 2Mbps (open drain)
• Available in the Texas Instruments NanoFree™ package
• 1.65V to 3.6V on A port and 2.3V to 5.5V on B port ( VCCA ≤ VCCB)
• VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
• No power-supply sequencing required – either VCCA or VCCB can be ramped first
• Ioff supports partial-power-down mode operation

2 Applications

• Handsets
• Smartphones
• Tablets
• Desktop PCs

3 Description

This one-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65V to 3.6V. VCCA must be less than or equal to VCCB . The B port is designed to track V CCB. VCCB accepts any supply voltage from 2.3V to 5.5V. This allows for low voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes. When the output-enable (OE) input is low, all outputs are placed in the high-impedance state. To put the device in the high-impedance state during power up or power down, tie OE to GND through a pull-down resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.

Package Information

PART NUMBER PACKAGE (1) PACKAGE SIZE (2) TXS0101 DBV (SOT-23, 6) 2.9mm × 2.8mm DCK (SC70, 6) 2mm × 2.1mm DRL (SOT-5X3, 6) 1.6mm × 1.6mm DRY (SON, 6) 1.45mm x 1mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. Data GNDGNDGND Data VCCA VCCB OE 3.3 V1.8 V 1.8-V System Controller A B 3.3-V System Typical Operating Circuit TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. DRY Package Figure 4-2. DBV, DCK, and DRL Package Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME DBV, DCK, DRL, DRY A 3 I/O Input/output A. Referenced to VCCA B 4 I/O Input/output B. Referenced to VCCB GND 2 G Ground OE 5 I Output enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA. VCCA 1 I A-port supply voltage. 1.65V ≤ VCCA ≤ 3.6V and VCCA ≤ VCCB VCCB 6 I B-port supply voltage. 2.3V ≤ VCCB ≤ 5.5V (1) I = input, O = output, G = ground www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TXS0101

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA Supply voltage A –0.5 4.6 V VCCB Supply voltage B –0.5 6.5 V VI Input Voltage(2) I/O Ports (A Port) –0.5 4.6 V VI Input Voltage(2) I/O Ports (B Port), OE –0.5 6.5 VO Voltage applied to any output in the high-impedance or power-off state(2) A Port –0.5 4.6 V B Port –0.5 6.5 VO Voltage applied to any output in the high or low state(2) (3) A Port –0.5 VCCA + 0.5 V B Port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Section 5.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 Exposure beyond the limits listed in Section 5.3 may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) A Port ±2500 V B Port ±8000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) B Port ±1500 A Port ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3) VCCA VCCB MIN MAX UNIT VCCA Supply voltage A 1.65 3.6 V VCCB Supply voltage B 2.3 5.5 V VIH High-level input voltage A-port I/O's 1.65 V to 1.95 V 2.3 V to 5.5 V VCCI - 0.2 VCCI V 2.3 V to 3.6 V VCCI - 0.4 VCCI B-port I/O's 1.65 V to 3.6 V 2.3 V to 5.5 V VCCI - 0.4 VCCI OE Input VCCA x 0.65 5.5 VIL Low-level input voltage A-port I/O's 1.65 V to 3.6 V 2.3 V to 5.5 V 0 0.15 VB-port I/O's 0 0.15 OE Input 0 VCCA x 0.35 Δt/Δv Input transition rise and fall time A//B Port I/Os, Push-Pull Driving 1.65 V to 3.6 V 2.3 V to 5.5 V 10 ns/V TA Operating free-air temperature –40 85 °C (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the device. The input leakage from these weak pulldowns is defined by the II specification indicated under Section 5.5 TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) TXS0101 UNITDCK DRY DRL DBV

6 PINS 6 PINS 6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 222.9 277.6 207.5 195.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 157.0 163.1 108.9 114.5 °C/W RθJB Junction-to-board thermal resistance 77.4 158.9 88.5 76.0 °C/W YJT Junction-to-top characterization parameter 58.6 29.3 6.3 51.7 °C/W YJB Junction-to-board characterization parameter 77.1 158.2 88.1 75.7 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 85°C MIN TYP MAX VOHA Port A output high 0.67 V VOLA Port A output low VOHB Port B output high 0.67 V VOLB Port B output low II Input leakage current OE VI = VCC or GND, TA= 25°C 1.65 V to 3.6 V 1.65 V to 5.5 V -1 1 µA II Input leakage current OE VI = VCC or GND, -40°C- 85°C 1.65 V to 3.6 V 1.65 V to 5.5 V -2 2 µA Ioff Partial power down current A port 0 V 0 V to 5.5 V -2 2 µA B port 0 V to 3.6 V 0 V -2 2 µA IOZ Tri-state output current A or B Port: VI = VCCI or GND VO = VCCO or GND OE = GND 1.65 V to 3.6 V 2.3 V to 5.5 V –2 2 µA ICCA VCCA supply current VI = VCCI or GND IO = 0 1.65 V to VCCB 2.3 V to 5.5 V 2.4 µA3.6 V 0 V 2.2 0 V 5.5 V -1 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.65 V to VCCB 2.3 V to 5.5 V 12 µA3.6 V 0 V -1 0 V 5.5 V 1 ICCA + ICCB Combined supply current VI = VCCI or GND IO = 0 1.65 V to VCCB 2.3 V to 5.5 V 14.4 µA Ci Input Capacitance OE 3.3 V 3.3 V 3.5 pF Cio A port TA= 25°C 3.3 V 3.3 V pF -40°C - 85°C 6 Cio B port TA= 25°C 3.3 V 3.3 V pF -40°C - 85°C 7.5 (1) VCCI is the VCC associated with the input port (2) VCCO is the VCC associated with the output port (3) Tested at VI = VT+(MAX) www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TXS0101

(4) Tested at VI = VT-(MIN) 5.6 Switching Characteristics, VCCA = 1.8 ± 0.15 V PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX tPHL Propagation Delay (Hight-to-Low) A B Push-Pull 5.3 5.4 6.8 ns tPLH Propagation Delay (Low-to-High) A B Push-Pull 6.8 7.1 7.5 ns Open-Drain 45 260 36 208 27 198 tPHL Propagation Delay (Hight-to-Low) B A Push-Pull 4.4 4.5 4.7 ns tPLH Propagation Delay (Low-to-High) B A Push-Pull 5.3 4.5 0.5 ns Open-Drain 45 175 36 140 27 102 ten Enable Time OE A or B Push-Pull 200 200 200 ns tdis Disable Time 50 40 35 trA Ouput Rise Time B A ns Open-Drain 38 165 30 132 22 95 trB Ouput Rise Time A B Push-Pull 1.1 10.8 1 9.1 1 7.6 ns Open-Drain 34 145 23 106 10 76 tfA Output Fall Time B A ns tfB Output Fall Time A B ns 5.7 Switching Characteristics, VCCA = 2.5 ± 0.2 V PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX tPHL Propagation Delay (Hight-to-Low) A B Push-Pull 3.2 3.7 3.8 ns Open-Drain 1.7 6.3 2 6 2.1 5.8 tPLH Propagation Delay (Low-to-High) A B Push-Pull 3.5 4.1 4.4 ns Open-Drain 43 250 36 206 27 190 tPHL Propagation Delay (Hight-to-Low) B A Push-Pull 3 3.6 4.3 ns tPLH Propagation Delay (Low-to-High) B A Push-Pull 2.5 1.6 1 ns Open-Drain 44 170 37 140 27 103 ten Enable Time OE A or B Push-Pull 200 200 200 ns tdis Disable Time 50 40 35 trA Ouput Rise Time B A ns Open-Drain 34 149 28 121 24 89 trB Ouput Rise Time A B ns Open-Drain 35 151 24 112 12 81 tfA Output Fall Time B A ns tfB Output Fall Time A B ns TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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5.8 Switching Characteristics, VCCA = 3.3 ± 0.3 V PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) UNIT3.3 ± 0.3 V 5.0 ± 0.5 V MIN TYP MAX MIN TYP MAX tPHL Propagation Delay (Hight- to-Low) A B Push-Pull 2.4 3.1 ns Open-Drain 1.3 4.2 1.4 4.6 tPLH Propagation Delay (Low- to-High) A B Push-Pull 4.2 4.4 ns Open-Drain 36 204 28 165 tPHL Propagation Delay (Hight- to-Low) B A Push-Pull 2.5 3.3 ns Open-Drain 1 124 1 97 tPLH Propagation Delay (Low- to-High) B A Push-Pull 2.5 2.6 ns Open-Drain 3 139 3 105 ten Enable Time OE A or B Push-Pull 200 200 ns tdis Disable Time 40 9.8 trA Ouput Rise Time B A Push-Pull 2.3 5.6 1.9 4.8 ns Open-Drain 25 116 19 85 trB Ouput Rise Time A B Push-Pull 1.6 6.4 0.6 7.4 ns Open-Drain 26 116 14 72 tfA Output Fall Time B A Push-Pull 1.4 5.4 1 5 ns Open-Drain 4.3 6.1 4.2 5.7 tfB Output Fall Time A B Push-Pull 2.3 7.4 2.4 7.6 ns Open-Drain 5 7.6 4.8 8.3

5.9 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching Push-Pull Driving 1.8 ± 0.15 V 2.5 V ± 0.2 V 21 Mbps 3.3 V ± 0.3 V 22 5 V ± 0.5 V 24 2.5 V ± 0.2 V 2.5 V ± 0.2 V 20 3.3 V ± 0.3 V 22 5 V ± 0.5 V 24 3.3 V ± 0.3 V 3.3 V ± 0.3 V 23 5 V ± 0.5 V 24 Open-Drain Driving 1.8 ± 0.15 V 2.5 V ± 0.2 V 2 3.3 V ± 0.3 V 2 5 V ± 0.5 V 2 2.5 V ± 0.2 V 2.5 V ± 0.2 V 2 3.3 V ± 0.3 V 2 5 V ± 0.5 V 1 3.3 V ± 0.3 V 3.3 V ± 0.3 V 2 5 V ± 0.5 V 2 tw Pulse Duration, Data Inputs Push-Pull Driving 1.8 V ± 0.15 V to 3.3 V ± 0.3 V 2.5 V ± 0.2 V to 5.5 V ± 0.5 V ns Open-Drain Driving 1.8 V ± 0.15 V to 3.3 V ± 0.3 V 2.5 V ± 0.2 V to 5.5 V ± 0.5 V 500 www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TXS0101

5.10 Typical Characteristics

Figure 5-1. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx)) Figure 5-2. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx)) Figure 5-3. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx)) TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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6 Parameter Measurement Information

6.1 Load Circuits

Figure 6-1 shows the push-pull driver circuit used for measuring data rate, pulse duration, propagation delay, output rise-time and fall-time. Figure 6-2 shows the open-drain driver circuit used for measuring data rate, pulse duration, propagation delay, output rise-time and fall-time. 1 M 15 pF VCCOVCCI DUT IN OUT Figure 6-1. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement Using a Push-Pull Driver 1 M 15 pF VCCOVCCI DUT IN OUT Figure 6-2. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement Using an Open-Drain Driver From Output Under Test 2 × VCCO 50 k 50 k 15 pF Open Figure 6-3. Load Circuit for Enable-Time and Disable-Time Measurement TEST S1 tPZL / tPLZ (tdis) 2 × VCCO tPHZ / tPZH (ten) Open 1. tPLZ and tPHZ are the same as tdis. 2. tPZL and tPZH are the same as ten. 3. VCCI is the VCC associated with the input port. 4. VCCO is the VCC associated with the output port. www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TXS0101

6.2 Voltage Waveforms

tW . VOHA/VOHBInput VOHA/VOHB VCCI 0 V Figure 6-4. Pulse Duration (Push-Pull) tPLH tPHL VCCI 0 V VCCO / 2 VOH VOL Input Output VCCI / 2 VCCI / 2

0.9 V CCO

0.1 V CCO

Figure 6-5. Propagation Delay Times Output Waveform 1 S1 at 2 × V (see Note 2) CCO VCCO VOL OE input Output Waveform 2 S1 at GND (see Note 2) tPZL tPZH tPLZ tPHZ V / 2CCAV / 2CCA 0 V VCCO × 0.2 V / 2CCO VOH × 0.9 V / 2CCO 0 V VCCA VOH

• CL includes probe and jig capacitance.
• Waveform 1 in Figure 6-6 is for an output with internal such that the output is high, except when OE is high (see Figure 6-3). Waveform 2 in Figure 6-6 is for an output with conditions such that the output is low, except when OE is high.
• All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO = 50Ω, dv/dt ≥ 1V/ns.
• The outputs are measured one at a time, with one transition per measurement.
• tPLZ and tPHZ are the same as tdis.
• tPZL and tPZH are the same as ten.
• tPLH and tPHL are the same as tpd.
• VCCI is the VCC associated with the input port.
• VCCO is the VCC associated with the output port. Figure 6-6. Enable and Disable Times TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The TXS0101 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The A port can accept I/O voltages ranging from 1.65V to 3.6V, while the B port can accept I/O voltages from 2.3V to 5.5V. The device is a pass gate architecture with edge rate accelerators (one shots) to improve the overall data rate. 10k Ω pullup resistors, commonly used in open drain applications, have been conveniently integrated so that an external resistor is not needed. While this device is designed for open drain applications, the device can also translate push-pull CMOS logic outputs.

7.2 Functional Block Diagram

A One Shot Accelerator Gate Bias OE VCCA VCCB B One Shot Accelerator 10NŸ10NŸ www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TXS0101

7.3 Feature Description

7.3.1 Architecture

As shown in Figure 7-1 , the TXS0101 architecture does not require a direction-control signal to control the direction of data flow from A to B or from B to A. B Gate Bias One shot T2T1 VCCA VCCB A Gate Bias One- shot 10k 10k One shot One- shot Figure 7-1. Architecture of a TXS01xx Cell Each A-port I/O has an internal 10k Ω pullup resistor to V CCA, and each B-port I/O has an internal 10k Ω pullup resistor to VCCB. The output one-shots detect rising edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1 and T2) for a short duration, which speeds up the low-to-high transition.

7.3.2 Input Driver Requirements

The fall time (t fA and t fB) of a signal depends on the output impedance of the external device driving the data I/Os of the TXS0101. Similarly, the t PHL and maximum data rates also depend on the output impedance of the external driver. The values for t fA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is less than 50Ω.

7.3.3 Power Up

During operation, ensure that V CCA ≤ VCCB at all times. During power-up sequencing, V CCA ≥ VCCB does not damage the device, so any power supply can be ramped up first.

7.3.4 Enable and Disable

The TXS0101 has an OE input that is used to disable the device by setting OE low, which places all I/Os in the Hi-Z state. The disable time (t dis) indicates the delay between the time when OE goes low and when the outputs actually get disabled (Hi-Z). The enable time (t en) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

7.3.5 Pullup or Pulldown Resistors on I/O Lines

Each A-port I/O has an internal 10k Ω pullup resistor to V CCA, and each B-port I/O has an internal 10k Ω pullup resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O to VCCA or VCCB (in parallel with the internal 10kΩ resistors).

7.4 Device Functional Modes

The TXS0101 device has two functional modes, enabled and disabled. To disable the device set the OE input low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device. TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TXS0101 can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The TXS0101 is an excellent choice for use in applications where an open-drain driver is connected to the data I/Os. The TXS0101 can also be used in applications where a push-pull driver is connected to the data I/Os, but the TXB0102 might be a better option for such push-pull applications.

8.2 Typical Application

3.3 V1.8 V 1.8-V System Controller A B 3.3-V System Figure 8-1. Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.65 to 3.6V Output voltage range 2.3 to 5.5V

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range: – Use the supply voltage of the device that is driving the TXS0101 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
• Output voltage range: – Use the supply voltage of the device that the TXS0101 device is driving to determine the output voltage range. – The TXS0101 device has 10kΩ internal pullup resistors. External pullup resistors can be added to reduce the total RC of a signal trace if necessary. www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TXS0101

• An external pull down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a result of an external pull down resistor. V O H = V C Cx × R P D / R P D + 10 k Ω (1) where
• VCCx is the supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor

8.2.3 Application Curve

2 V/div

VCCA = 1.8V VCCB = 5V Figure 8-2. Level-Translation of a 2.5MHz Signal

8.3 Power Supply Recommendations

The TXS0101 device uses two separate configurable power-supply rails, V CCA and V CCB. V CCB accepts any are designed to track V CCA and VCCB respectively allowing for low voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes. The TXS0101 device does not require power sequencing between V CCA and V CCB during power-up so the powersupply rails can be ramped in any order. A V CCA value greater than or equal to V CCB (VCCA ≥ VCCB) does not damage the device, but during operation, V CCA must be less than or equal to V CCB (VCCA ≤ V CCB) at all times. The output-enable (OE) input circuit is designed so that it is supplied by V CCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To put the outputs in the high-impedance state during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and V CCB are fully ramped and stable. The current-sourcing capability of the driver determines the minimum value of the pulldown resistor to ground. TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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8.4 Layout

8.4.1 Layout Guidelines

For device reliability, TI recommends following common printed-circuit board layout guidelines such as follows:

• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one shot duration, approximately 30ns, causing any reflection to encounter low impedance at the source driver.
• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements

8.4.2 Layout Example

B VCCB LEGEND VIA to Power Plane VIA to GND Plane (Inner Layer) Polygonal Copper Pour VCCA1 3 A Keep OE low until VCCA and VCCB are powered up Bypass CapacitorBypass Capacitor OETXS0101 V CCA To/From Controller/System To/From Controller/System Figure 8-3. Typical Layout of TXS0101 www.ti.com TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TXS0101

9 Device and Documentation Support

9.1 Device Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, A Guide to Voltage Translation With TXS-Type Translators
• Texas Instruments, Introduction to Logic

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

NanoFree™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (June 2017) to Revision E (October 2024) Page Changes from Revision C (December 2015) to Revision D (June 2017) Page

• Changed YZP package pinout diagram with new image and added YZP pin assignments in Pin Functions

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TXS0101 SCES638E – OCTOBER 2007 – REVISED DECEMBER 2024 www.ti.com

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www.ti.com 13-Feb-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TXS0101DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green Call TI | SN | NIPDAULevel-1-260C-UNLIM -40 to 85 (35WH, NFFF, NFFR) Samples TXS0101DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green Call TI Level-1-260C-UNLIM -40 to 85 (35WH, NFFF, NFFR) Samples TXS0101DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NFFR Samples TXS0101DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green Call TI | SN | NIPDAULevel-1-260C-UNLIM -40 to 85 (1PR, 2GO) Samples TXS0101DCKT ACTIVE SC70 DCK 6 250 RoHS & Green Call TI | SN | NIPDAULevel-1-260C-UNLIM -40 to 85 (1PR, 2GO) Samples TXS0101DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 2GR Samples TXS0101DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 Q9 Samples TXS0101YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 2GN Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

www.ti.com 13-Feb-2025 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXS0101 :

• Automotive : TXS0101-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXS0101DBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 TXS0101DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 TXS0101DBVT SOT-23 DBV 6 250 202.0 201.0 28.0 TXS0101DCKR SC70 DCK 6 3000 210.0 185.0 35.0 TXS0101DCKR SC70 DCK 6 3000 200.0 183.0 25.0 TXS0101DCKT SC70 DCK 6 250 200.0 183.0 25.0 TXS0101DRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0 TXS0101DRYR SON DRY 6 5000 210.0 185.0 35.0 TXS0101YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 1.7 1.5 4X 0.5 2X 1 6X 0.3 0.1

0.6 MAX

6X 0.18 0.08 6X 0.4 0.2 0.05

0.00 TYP

6X 0.27 0.15 2X 0 -10 2X 4 -15 1.3 1.1 1.7 1.5 NOTE 3 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/F 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-293 Variation UAAD 1 6 PIN 1 ID AREA 3 4 SEATING PLANE 0.05 C SCALE 8.000

0.1 C A B

0.05 C SYMM SYMM A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

6X (0.67) 6X (0.3) (1.48) 4X (0.5) (R0.05) TYP 4223266/F 11/2024 SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria. SYMM LAND PATTERN EXAMPLE SCALE:30X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDERMASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (1.48) 4X (0.5) 6X (0.67) 6X (0.3) (R0.05) TYP SOT - 0.6 mm max heightDRL0006A PLASTIC SMALL OUTLINE 4223266/F 11/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM SYMM 3 4

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.45 0.90 0.15 6X 0.50 0.25 0.6

0.3 TYP

0 TYP

1.9 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/G 08/2024 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C0.5 MAX 0.19 0.15 TYP

0.5 TYP

6X 0.25 0.21 0.5 TYP B E A D 4219524/A 06/2014 DSBGA - 0.5 mm max heightYZP0006 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration. NanoFree Is a trademark of Texas Instruments. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C B A 1 2

0.015 C A B

C SCALE 9.000 D: Max = E: Max = 1.418 mm, Min = 0.918 mm, Min = 1.358 mm 0.858 mm

www.ti.com EXAMPLE BOARD LAYOUT 6X ( ) 0.225 (0.5) TYP (0.5) TYP ( ) METAL 0.225 0.05 MAX SOLDER MASK OPENING METAL UNDER MASK SOLDER MASK OPENING 0.225 DSBGA - 0.5 mm max heightYZP0006 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). SYMM SYMM LAND PATTERN EXAMPLE SCALE:40X 1 2 A B C NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP 6X ( 0.25) (R ) TYP 0.05 METAL TYP 4219524/A 06/2014 DSBGA - 0.5 mm max heightYZP0006 DIE SIZE BALL GRID ARRAY NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 1 2 A B C

www.ti.com PACKAGE OUTLINE C 0.22 0.15 2.4 1.8 4X 0.65 1.1 0.8 0.1

0.0 TYP

6X 0.30 0.15 NOTE 5 0.46

0.26 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR 4214835/D 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Falls within JEDEC MO-203 variation AB. INDEX AREA PIN 1 NOTE 5 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT 6X (0.9) 6X (0.4) (2.2) 4X (0.65) (R0.05) TYP 4214835/D 11/2024 SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) 4X(0.65) 6X (0.9) 6X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0006A SMALL OUTLINE TRANSISTOR 4214835/D 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4207181/G

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