TXMC638 TEWS | Alldatasheet

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Technical content

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.4 2018-01-25 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com The Embedded I/O Company TXMC638 Reconfigurable FPGA with 24 x 16 bit Analog Input TXMC638-11R TXMC638-11R without heat sink

Application Information

The TXMC638 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable Kintex -7 FPGA with 24 ADC input channels. The TXMC638 ADC input channels are based on the Linear Dual 16-Bit 5Msps Differential LTC2323-16 ADC s. Each of the 24 channels has 16bit resolution and works with up to 5Msps. The analog input circuit is designed to allow input voltages up to ±2.5 V on each input -pin resulting in a ±5 V differential voltage range. For customer specific I/O extension or inter -board communication, the TXMC638 provides 64 I/Os on P14 and 4 Multi-Gigabit-Transceiver on P16. The P14 I /O lines are connected directly to the FPGA and can be used as 64 single ended LVCMOS24 or as 32 differential LVDS25 interfaces. Additionally the TXMC638 provides three

100 Ohm terminated ac -coupled, differential inputs

with wide Input voltage range. All front I/O lines such as the ADC interface and the three 100 Ohm inputs are connected to a 98- pin. Samtec ERF8-049 Rugged EdgeRate Connector. A 1GB, 32 bit wide DDR3 SDRAM is connected to the user FPGA. The SDRAM -Interface uses an internal Memory Controller of the Kintex-7. The user FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies “Tandem PROM” is the favored m ethodology. The SPI flash device is in -system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”). User applications for the TXMC638 with Kintex -7 FPGA can be developed using the design software Vivado Design Suite. A license for the Vivado Design Suite design tool is required. TEWS offe rs a well -documented FPGA Board Reference Design. It includes constrain t file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the TXMC638. The TXMC638 is delivered with the FPGA Board Reference Design. The user FPGA can be programmed via the on-board Board Configuration Controller (BCC) . Programming via the JTAG interface using an XILINX USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation. TA310

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.4 2018-01-25 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com The Embedded I/O Company Technical Information o Form Factor: Standard single width XMC o Board size: 149 mm x 74 mm o PCI Express x4 Link (Base Specification 1.1) compliant interface conforming to ANSI/VITA 42.3-2006 o IPMI resource: FRU hardware definition information stored in on-board EEPROM o TXMC638 FPGA options: o -10R Xilinx XC7K160T-2FBG676I Kintex-7 o -11R Xilinx XC7K325T-2FBG676I Kintex-7 o -12R Xilinx XC7K410T-2FBG676I Kintex-7 o Serial Flash for FPGA Configuration o FPGA clock options: o Local clock generator as source for the FPGA internal PLL o Free programmable Si514 Oscillator o DDR3 SDRAM bank, 256M x 32 Bit (1GB) o Front I/O lines o 24 differential analog inputs o 16 bit resolution o 5Msps o Factory calibration o Back I/O lines o 64 single ended or 32 differential back I/O lines on rear connector P14. o 4 FPGA Multi-Gigabit-Transceiver on rear connector P16 o Operating temperature -40°C to +85°C o MTBF (MIL-HDBK217F/FN2 GB 20°C): 269000 Block Diagram TXMC638

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice. All trademarks mentioned are property of their respective owners. Issue 1.0.4 2018-01-25 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com The Embedded I/O Company Order Information RoHS Compliant TXMC638-10R Kintex-7 FPGA XC7K160T -2 FBG676, 1GBDDR3 24 x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16 TXMC638-11R TXMC638-12R Kintex-7 FPGA XC7K325T -2 FBG676, 1GBDDR3 Kintex-7 FPGA XC7K410T -2 FBG676, 1GBDDR3 24 x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16 24 x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16 Documentation TXMC638-DOC User Manual Software TDRV018-SW-25 Integrity Software Support TDRV018-SW-42 VxWorks Software Support (Legacy and VxBus-Enabled Software Support) TDRV018-SW-65 Windows Software Support TDRV018-SW-82 Linux Software Support TDRV018-SW-95 QNX Software Support For other operating systems please contact TEWS.

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