TXG4042DBQR

TXG4041_V01 TI | Alldatasheet

Document overview

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Technical content

TXG404x 4-bit, ±40V Ground-Level Translator

1 Features

• Supports DC ground shifts up to 40V
• AC Noise Rejection of 80VPP up to 5MHz
• CMTI of 1kV/µs
• Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
• Greater than 250Mbps
• Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
• Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
• 4, 2, 1 channel devices available
• Two device variants: – TXG4041: 3 forward, 1 reverse – TXG4042: 2 forward, 2 reverse
• Supports VCC disconnect feature (I/Os are forced into high-Z)
• Schmitt-trigger inputs allows for slow and noisy signals
• Inputs with integrated static pull-down resistors prevent channels from floating
• Operating temperature from –40°C to +125°C
• Latch-up performance exceeds 100mA per JESD 78, class II
• ESD protection exceeds JESD 22 – 4000V human-body model – 500V charged-device model
• Package options provided: – RUC (X2QFN-14) – DYY (SOT-14) – DBQ (QSOP-16)

2 Applications

• Test and Measurement
• Industrial Automation
• Appliances
• Robotics
• Energy Storage Systems

3 Description

The TXG404x is a 4-bit, fixed direction, non-galvanic based voltage and ground-level translator that supports both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ± 40V. Compared to traditional level shifters, the TXG404x family solves the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance. VCCA is referenced to GNDA and V CCB is referenced to GNDB. Ax pins are referenced to V CCA logic level while Bx pins are referenced to V CCB logic levels. Both A port and B port accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to Table 7-1). The leakage between GNDA and GNDB is <45nA when VCC to GND is shorted. The TXG404x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency, and channel-to-channel skew. The device supresses noise levels of 80V PP up to 5MHz ( Figure 7-5). TXG404x can support multiple interfaces such as SPI, UART, GPIO, and I2S.

Package Information

NUMBER PACKAGE (1) BODY SIZE (NOM) TXG4041 TXG4042 DYY (SOT-14) 4.20mm × 2.00mm DBQ (QSOP-16) 4.90mm x 3.90mm RUC (X2QFN-14) 2.00mm × 2.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. System #1 System #2INx OUTx VccA GndA VccB GndB TXG VccA GndA VccB GndB Parasi c capacitance/ resistance <40V Simplified Diagram TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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4 Pin Configuration and Functions

OE_A VCCBVCCA B1Y B2Y B3Y OE_B GNDBGNDA Figure 4-1. TXG4041 RUC Package 14-Pin X2QFN Top View Table 4-1. TXG4041 RUC Pin Functions PIN I/O DESCRIPTION Name TXG4041 A1 1 I Input A1. Referenced to VCCA A2 2 I Input A2. Referenced to VCCA A3 3 I Input A3. Referenced to VCCA A4Y 4 O Output A4. Referenced to VCCA B1Y 12 O Output B1. Referenced to VCCB B2Y 11 O Output B2. Referenced to VCCB B3Y 10 O Output B3. Referenced to VCCB B4 9 I Input B4. Referenced to VCCB OE_A 5 I Active-High Output Enable (A side). Pull to GND to place all outputs in high- impedance mode. OE_B 8 I Active-High Output Enable (B side). Pull to GND to place all outputs in high- impedance mode. VCCA 14 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 13 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 6 — Ground reference for VCCA GNDB 7 — Ground reference for VCCB www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3

OE_A VCCBVCCA B1Y B2Y OE_B GNDBGNDA Figure 4-2. TXG4042 RUC Package 14-Pin X2QFN Top View Table 4-2. TXG4042 RUC Pin Functions PIN I/O DESCRIPTION Name TXG4042 A1 1 I Input A1. Referenced to VCCA A2 2 I Input A2. Referenced to VCCA A3Y 3 O Output A3. Referenced to VCCA A4Y 4 O Output A4. Referenced to VCCA B1Y 12 O Output B1. Referenced to VCCB B2Y 11 O Output B2. Referenced to VCCB B3 10 I Input B3. Referenced to VCCB B4 9 I Input B4. Referenced to VCCA OE_A 5 I Active-High Output Enable (A side). Pull to GND to place all outputs in high-impedance mode. OE_B 8 I Active-High Output Enable (B side). Pull to GND to place all outputs in high-impedance mode. VCCA 14 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 13 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 6 — Ground reference for VCCA GNDB 7 — Ground reference for VCCB TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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14 VCCB

6OE_A 9 OE_B 1VCCA 7GNDA 8 GNDB Figure 4-3. TXG4041 DYY 14-Pin SOT Top View Table 4-3. TXG4041 DYY Pin Functions PIN I/O DESCRIPTION Name TXG4041 A1 2 I Input A1. Referenced to VCCA A2 3 I Input A2. Referenced to VCCA A3 4 I Input A3. Referenced to VCCA A4Y 5 O Output A4. Referenced to VCCA B1Y 13 O Output B1. Referenced to VCCB B2Y 12 O Output B2. Referenced to VCCB B3Y 11 O Output B3. Referenced to VCCB B4 10 I Input B4. Referenced to VCCB OE_A 6 I Active-High Output Enable (A side). Pull to GND to place all outputs in high- impedance mode. OE_B 9 I Active-High Output Enable (B side). Pull to GND to place all outputs in high- impedance mode. VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 14 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 7 — Ground reference for VCCA GNDB 8 — Ground reference for VCCB www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5

6OE_A 9 OE_B 1VCCA 7GNDA 8 GNDB Figure 4-4. TXG4042 DYY 14-Pin SOT Top View Table 4-4. TXG4042 DYY Pin Functions PIN I/O DESCRIPTION Name TXG4042 A1 2 I Input A1. Referenced to VCCA A2 3 I Input A2. Referenced to VCCA A3Y 4 O Output A3. Referenced to VCCA A4Y 5 O Output A4. Referenced to VCCA B1Y 13 O Output B1. Referenced to VCCB B2Y 12 O Output B2. Referenced to VCCB B3 11 I Input B3. Referenced to VCCB B4 10 I Input B4. Referenced to VCCA OE_A 6 I Active-High Output Enable (A side). Pull to GND to place all outputs in high- impedance mode. OE_B 9 I Active-High Output Enable (B side). Pull to GND to place all outputs in high- impedance mode. VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 14 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 7 — Ground reference for VCCA GNDB 8 — Ground reference for VCCB TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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16 VCCB

7OE_A 10 OE_B 1VCCA 8GNDA 9 GNDB Figure 4-5. TXG4041 DBQ 16-Pin QSOP Top View Table 4-5. TXG4041 DBQ Pin Functions PIN I/O DESCRIPTION Name TXG4041 A1 3 I Input A1. Referenced to VCCA A2 4 I Input A2. Referenced to VCCA A3 5 I Input A3. Referenced to VCCA A4Y 6 O Output A4. Referenced to VCCA B1Y 14 O Output B1. Referenced to VCCB B2Y 13 O Output B2. Referenced to VCCB B3Y 12 O Output B3. Referenced to VCCB B4 11 I Input B4. Referenced to VCCB OE_A 7 I Active-High Output Enable (A side). Pull to GND to place all outputs in high- impedance mode. OE_B 10 I Active-High Output Enable (B side). Pull to GND to place all outputs in high- impedance mode. VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 16 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 2, 8 — Ground reference for VCCA GNDB 9, 15 — Ground reference for VCCB www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7

7OE_A 10 OE_B 1VCCA 8GNDA 9 GNDB Figure 4-6. TXG4042 DBQ 16-Pin QSOP Top View Table 4-6. TXG4042 DBQ Pin Functions PIN I/O DESCRIPTION Name TXG4042 A1 3 I Input A1. Referenced to VCCA A2 4 I Input A2. Referenced to VCCA A3Y 5 O Output A3. Referenced to VCCA A4Y 6 O Output A4. Referenced to VCCA B1Y 14 O Output B1. Referenced to VCCB B2Y 13 O Output B2. Referenced to VCCB B3 12 I Input B3. Referenced to VCCB B4 11 I Input B4. Referenced to VCCB OE_A 7 I Active-High Output Enable (A side). Pull to GND to place all outputs in high-impedance mode. OE_B 10 I Active-High Output Enable (B side). Pull to GND to place all outputs in high-impedance mode. VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 16 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 2, 8 — Ground reference for VCCA GNDB 9, 15 — Ground reference for VCCB TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA to VGNDA Supply voltage A to Ground voltage A –0.5 6.5 V VCCB to VGNDB Supply voltage B to Ground voltage B –0.5 6.5 V VGNDA to VGNDB Voltage between GNDA and GNDB -45 45 V VI Input Voltage(2) I/O Ports (A Port) to VGNDA –0.5 6.5 V I/O Ports (B Port) to VGNDB –0.5 6.5 OE –0.5 6.5 V VO Voltage applied to any output in the high-impedance or power-off state(2) A Port to VGNDA –0.5 6.5 V B Port to VGNDB –0.5 6.5 VO Voltage applied to any output in the high or low state(2) (3) A Port to VGNDA –0.5 6.5 V B Port to VGNDB –0.5 6.5 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IO Continuous output current –16 16 mA Continuous current through VCCx or GNDx –64 64 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Section 5.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 Exposure beyond the limits listed in Section 5.3 may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5V maximum if the output current rating is observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN TYP MAX UNIT VCCA Supply voltage A - Relative to GNDA 1.71 5.5 V VCCB Supply voltage B - Relative to GNDB 1.71 5.5 V VGNDA to VGNDB Voltage between GNDA and GNDB -40 40 V IOH High-level output current VCCO = 1.71V –4.5 mA VCCO = 2.3V –8 VCCO = 3V –10 VCCO = 4.5V –12 IOL Low-level output current VCCO = 1.71V 4.5 mA VCCO = 2.3V 8 VCCO = 3V 10 VCCO = 4.5V 12 VI Input voltage - Relative to GNDx 0 5.5 V VO Output voltage - Relative to GNDx 0 VCCO V TA Operating free-air temperature –40 125 °C (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the device. The input leakage from these weak pulldowns is defined by the II specification indicated under Section 5.5.

5.4 Thermal Information

THERMAL METRIC(1) TXGx041 and TXGx042 UNITDYY (SOT) RUC (X2QFN) DBQ (QSOP)

14 PINS 14 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 128.4 99.7 143.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.4 57.9 82.3 °C/W RθJB Junction-to-board thermal resistance 58.5 51.9 46.9 °C/W YJT Junction-to-top characterization parameter 2.7 8.1 1.2 °C/W YJB Junction-to-board characterization parameter 51.9 57.2 81.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX VOH High-level output voltage (3) IOH = –4.5mA 1.71V 1.71V 1.5 V IOH = –8mA 2.3V 2.3V 2.0 IOH = –10mA 3V 3V 2.6 IOH = –12mA 4.5V 4.5V 4.0 VOL Low-level output voltage (4) IOL = 4.5mA 1.71V 1.71V 0.18 V IOL = 8mA 2.3V 2.3V 0.33 IOL = 10mA 3V 3V 0.41 IOL = 12mA 4.5V 4.5V 0.49 VT+ Positive-going input-threshold voltage Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71V 1.71V 1.14 V 2.3V 2.3V 1.42 3V 3V 1.74 4.5V 4.5V 2.47 5.5V 5.5V 2.97 VT+ Positive-going input-threshold voltage OE (Referenced to VCCA or VCCB) 1.71V 1.71V 1.12 V 2.3V 2.3V 1.42 3V 3V 1.73 4.5V 4.5V 2.47 5.5V 5.5V 2.94 VT- Negative-going input-threshold voltage Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71V 1.71V 0.52 V 2.3V 2.3V 0.76 3V 3V 1.09 4.5V 4.5V 1.77 5.5V 5.5V 2.28 VT- Negative-going input-threshold voltage OE (Referenced to VCCA or VCCB) 1.71V 1.71V 0.46 V 2.3V 2.3V 0.76 3V 3V 1.04 4.5V 4.5V 1.86 5.5V 5.5V 2.5 ΔVT Input-threshold hysteresis (VT+ – VT-) Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71V 1.71V 0.24 0.54 V 2.3V 2.3V 0.29 0.60 3V 3V 0.33 0.54 4.5V 4.5V 0.38 0.82 5.5V 5.5V 0.37 0.96 ΔVT Input-threshold hysteresis (VT+ – VT-) OE (Referenced to VCCA or VCCB) 1.71V 1.71V 0.24 0.45 V 2.3V 2.3V 0.28 0.58 3V 3V 0.32 0.54 4.5V 4.5V 0.35 0.58 5.5V 5.5V 0.39 0.62 II Input leakage current Data Inputs (Ax, Bx) VI = VCCI or GND www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX Ioff-float Floating supply Partial power down current A Port or B Port VI = GND Floating(5) 0V - 5.5V –2.5 2.5 µA 0V - 5.5V Floating(5) –2.5 2.5 IO Tri-state output Output current A or B Port: VI = VCCA or VGNDA OE = GND 1.71V – 5.5V 1.1V – 5.5V –5 5 µA Ci Control Input Capacitance VI = 3.3V or VGNDA 3.3V 3.3V 2 pF Cio Data I/O Capacitance OE = GND, VO = 1.71V DC +1MHz -16dBm sine wave 3.3V 3.3V 5 pF CGND Cap between grounds All channels combined (VCC both sides are powered on) 49 pF All channels combined (VCC to GND shorted) 54 pF Leakage Current Leakage between GndA to GndB All channels combined (VCC to GND shorted) 1.71V – 5.5V 1.71V – 5.5V 45 nA All channels combined (VCC both sides are powered on and inputs are all low) 1.71V – 5.5V 1.71V – 5.5V 45 nA All channels combined (VCC both sides are powered on and inputs are all high) 1.71V – 5.5V 1.71V – 5.5V 33 µA CMTI Common Mode Transient Immunity Input toggling at 100Mbps Ground shift up to 40V 1.71V – 5.5V 1.71V – 5.5V 1 kV/µs VUVLO+ Positive-Going Undervoltage Lockout Voltage A Supply 1.71V – 5.5V 1.55 V B Supply 1.71V – 5.5V 1.55 VUVLO- Negative-Going Undervoltage Lockout Voltage A Supply 1.71V – 5.5V 1.36 V B Supply 1.71V – 5.5V 1.36 VUVLO_Hys Undervoltage Lockout Hysteresis A Supply 1.71V – 5.5V 36 147 mV B Supply 1.71V – 5.5V 36 147 (1) VCCI is the VCC associated with the input port and referenced to GNDA (2) VCCO is the VCC associated with the output port and referenced to GNDB (3) Tested at VI = VT+(MAX) (4) Tested at VI = VT-(MIN) (5) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.6 Supply Current

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX TXGx041 ICCA VCCA supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 546 1220 µA 0V 5.5V -3 13 5.5V 0V 509 1050 VI = GND IO = 0 5.5V Floating(3) 509 1050 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 750 1836 µA 0V 5.5V 654 1350 5.5V 0V -3 36 VI = GND IO = 0 Floating(3) 5.5V 656 1350 ICCA + ICCB Supply Current - Disable EN = 0 1.8V 1.8V 1.9 3.1 mA 2.5V 2.5V 1.9 3.1 3.3V 3.3V 2.0 3.1 5V 5V 2.1 3.3 ICCA + ICCB Supply Current - DC Signal VI = VCCI 1.8V 1.8V 1 2.65 mA 2.5V 2.5V 1.3 2.7 3.3V 3.3V 1.3 2.8 5V 5V 1.4 3.1 VI = GND 1.8V 1.8V 1.2 2.7 2.5V 2.5V 1.3 2.7 3.3V 3.3V 1.3 2.8 5V 5V 1.4 3.1 www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX ICCA + ICCB Supply Current - AC Signal All channels switching with square wave clock input; CL = 15pF, 1Mbps 1.8V 1.8V 1.5 2.6 mA 2.5V 2.5V 1.6 2.7 3.3V 3.3V 1.6 2.8 5V 5V 1.9 3.3 All channels switching with square wave clock input; CL = 15pF, 50Mbps 1.8V 1.8V 9.2 12.1 2.5V 2.5V 10.8 14 3.3V 3.3V 12.4 16.2 5V 5V 17.6 20.6 All channels switching with square wave clock input; CL = 15pF, 100Mbps 1.8V 1.8V 16.5 20.1 2.5V 2.5V 20.2 24.7 3.3V 3.3V 24.1 29 5V 5V 35 38 TXGx042 ICCA VCCA supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 547 1365 µA 0V 5.5V -2.6 25 5.5V 0V 625 1052 VI = GND IO = 0 5.5V Floating(3) 625 1052 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 753 1692 µA 0V 5.5V 819 1380 5.5V 0V -2.4 25 VI = GND IO = 0 Floating(3) 5.5V 823 1380 ICCA + ICCB Supply Current - Disable EN = 0 1.8V 1.8V 1.9 3.1 mA 2.5V 2.5V 1.9 3.1 3.3V 3.3V 2 3.1 5V 5V 2.1 3.3 TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX ICCA + ICCB Supply Current - DC Signal VI = VCCI 1.8V 1.8V 1.2 2.7 mA 2.5V 2.5V 1.3 2.6 3.3V 3.3V 1.3 2.7 5V 5V 1.4 3.1 VI = GND 1.8V 1.8V 1.2 2.7 2.5V 2.5V 1.3 2.6 3.3V 3.3V 1.3 2.7 5V 5V 1.4 3.1 ICCA + ICCB Supply Current - AC Signal All channels switching with square wave clock input; CL = 15pF, 1Mbps 1.8V 1.8V 1.5 2.6 mA 2.5V 2.5V 1.6 2.7 3.3V 3.3V 1.6 2.8 5V 5V 1.9 3.3 All channels switching with square wave clock input; CL = 15pF, 50Mbps 1.8V 1.8V 9.5 12.9 2.5V 2.5V 10.6 13.9 3.3V 3.3V 12.9 15.9 5V 5V 17.7 20.8 All channels switching with square wave clock input; CL = 15pF, 100Mbps 1.8V 1.8V 16.5 20 2.5V 2.5V 20.5 25.2 3.3V 3.3V 24.4 28.7 5V 5V 34.9 38.4 (1) VCCI is the VCC associated with the input port (2) VCCO is the VCC associated with the output port (3) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15

5.7 Switching Characteristics, VCCA = 1.8 ± 0.15V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time OE A -40°C to 85°C 16.1 35 16.1 35 16.1 35 16.1 35 ns ten Enable time ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.36V -40°C to 85°C 8.4 8.3 8.2 8 µs -40°C to 125°C 8.4 8.3 8.2 8 tPU Time from ULVO to valid output data -40°C to 85°C 66.8 66.8 66.8 66.9 µs -40°C to 125°C 66.8 66.8 66.8 66.9 TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.8 Switching Characteristics, VCCA = 2.5 ± 0.2V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns ten Enable time ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns B A -40°C to 85°C 0.5 1 0.5 1 0.5 1 0.5 1 tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.36V -40°C to 85°C 8.1 8.1 8 7.8 µs -40°C to 125°C 8.1 8.1 8 7.8 tPU Time from ULVO to valid output data -40°C to 85°C 71.3 71.3 71.3 71.3 µs -40°C to 125°C 71.3 71.3 71.3 71.3 www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17

5.9 Switching Characteristics, VCCA = 3.3 ± 0.3V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns ten Enable time OE A -40°C to 85°C 3 8 3.1 8 3.1 8 3 8 ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.36V -40°C to 85°C 8 7.9 7.9 7.7 µs -40°C to 125°C 8 7.9 7.9 7.7 µs tPU Time from ULVO to valid output data -40°C to 85°C 79.1 79.1 79.1 79.1 µs -40°C to 125°C 79.1 79.1 79.1 79.1 µs TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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5.10 Switching Characteristics, VCCA = 5.0 ± 0.5V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns tdis Disable time ns ten Enable time ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.36V -40°C to 85°C 7.9 7.8 7.7 7.6 µs -40°C to 125°C 7.9 7.8 7.7 7.6 tPU Time from ULVO to valid output data -40°C to 85°C 98.3 98.3 98.3 98.3 µs -40°C to 125°C 98.3 98.3 98.3 98.3 www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19

5.11 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO No Translation 1.65V - 1.95V 1.65V - 1.95V 264 Mbps 2.3V - 2.7V 2.3V - 2.7V 264 Mbps 3.0V - 3.6V 3.0V - 3.6V 176 Mbps 4.5V - 5.5V 4.5V - 5.5V 176 Mbps TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO Up Translation 1.65V - 1.95V 2.3V - 2.7V 264 Mbps 1.65V - 1.95V 3.0V - 3.6V 264 Mbps 1.65V - 1.95V 4.5V - 5.5V 264 Mbps 2.3V - 2.7V 3.0V - 3.6V 264 Mbps 2.3V - 2.7V 4.5V - 5.5V 220 Mbps 3.0V - 3.6V 4.5V - 5.5V 176 Mbps TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO Down Translation 2.3V - 2.7V 1.65V - 1.95V 285 Mbps 3.0V - 3.6V 2.3V - 2.7V 220 Mbps 3.0V - 3.6V 1.65V - 1.95V 220 Mbps 4.5V - 5.5V 3.0V - 3.6V 176 Mbps 4.5V - 5.5V 2.3V - 2.7V 220 Mbps 4.5V - 5.5V 1.65V - 1.95V 220 Mbps tsk - Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) No Translation tsk - Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) Up Translation TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX tsk - Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) Down Translation www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21

5.12 Typical Characteristics

I OH - Output High Current (mA) V OH - Output High Voltage (V) 0 3 6 9 12 15 18 21 24 1.5 1.75 2.25 2.5 2.75 3.25 3.5 3.75 4.25 4.5 4.75 V CC = 5.0V V CC = 3.3V V CC = 2.5V Figure 5-1. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) I OH - Output High Current (mA) V OH - Output High Voltage (V) 0.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95 V CC = 1.8V V CC = 1.5V V CC = 1.2V Figure 5-2. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) I OL - Output Low Current (mA) V OL - Output Low Voltage (V) 0 3 6 9 12 15 18 21 24 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 0.275 0.3 0.325 0.35 V CC = 2.5V V CC = 3.3V V CC = 5.0V Figure 5-3. Typical (TA=25°C) Output Low Voltage (VOL) vs Sink Current (IOL) I OL - Output Low Current (mA) V OL - Output Low Voltage (V) 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 0.275 0.3 0.325 0.35 V CC = 1.2V V CC = 1.5V V CC = 1.8V Figure 5-4. Typical (TA=25°C) Output Low Voltage (VOL) vs Sink Current (IOL) V IN - Input Voltage (V) I CC - Supply Current (mA) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 V CC = 2.5 V V CC = 3.3 V V CC = 5 V Figure 5-5. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage (VIN) V IN - Input Voltage (V) I CC - Supply Current (mA) 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 V CC = 1.2 V V CC = 1.5 V V CC = 1.8 V Figure 5-6. Typical (TA=25°C) Supply Current (ICC) vs Input Voltage (VIN) TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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6 Parameter Measurement Information

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, generators supply all input pulses that have the following characteristics:

• f = 1MHz
• ZO = 50Ω
• Δt/ΔV ≤ 1ns/V Output Pin Under Test CL (1) RL RL GND Open 2 x VCCO Measurement Point A. 1. CL includes probe and jig capacitance. Figure 6-1. Load Circuit Table 6-1. Load Circuit Conditions Parameter VCCO RL CL S1 VTP tpd Propagation (delay) time 1.71V – 5.5V 10kΩ 15pF Open N/A ten, tdis Enable time, disable time 1.71V – 2.7V 10kΩ 15pF 2 × VCCO 0.15V 3.0V – 5.5V 10kΩ 15pF 2 × VCCO 0.3V ten, tdis Enable time, disable time 1.71V – 2.7V 10kΩ 15pF GND 0.15V 3.0V – 5.5V 10kΩ 15pF GND 0.3V VO VI VOL VOH VCCI 0 V tr tf tPLH tPHL 50% 50% 50% 50% 90% 10% 1. VCCI is the supply pin associated with the input port. 2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1 Figure 6-2. Switching Characteristics Voltage Waveforms www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23

1.36 V 50% tDO default low VO VI VOH VCC 0 V 1.55 V tPU 1. VCCI is the supply pin associated with the input port. 2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1 Figure 6-3. Default Output Delay Time & Time from UVLO to Valid Output Voltage Waveform VCCA VCCA / 2 Output(1) tdis GND VCCA / 2 VCCO (3) VOL (4)VOL + VTP ten VCCO / 2 Output(2) VOH (4) GND VOH - VTP VCCO / 2 OE 1. Output waveform on the condition that input is driven to a valid Logic Low. 2. Output waveform on the condition that input is driven to a valid Logic High. 3. VCCO is the supply pin associated with the output port. 4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 6-4. Enable Time And Disable Time IN OUT VCCO CL See Note A GNDOGNDI + – VCM VOH or VOL VCCI Pass-fail criteria: The output must remain stable. IN 10ns 1. CL = 15pF and includes instrumentation and fixture capacitance within ±20%. Figure 6-5. Common-Mode Transient Immunity Test Circuit TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The TXG404x is a 4-bit ground-level translator that uses two individually configurable power-supply rails, which allows it to translate across two different power domains. The device is operational with V CCA and VCCB supplies as low as 1.71V and as high as 5.5V. The A port is designed to track V CCA and the B port is designed to track VCCB. In addition to I/O level shifting, this translator can support a difference of - 40V to + 40V between GNDA and GNDB. VCCA is referenced to GNDA and VCCB is referenced to GNDB. The TXG404x device is designed for asynchronous communication between data buses. The TXG404x transmits data with fixed direction from the A bus to the B bus on some channels and from the B bus to the A bus on the remaining channels. The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated. The OE_A pin is referenced to V CCA and OE_B pin is referenced to V CCB. The OE pin can be left floating or externally pulled down to ground to keep the translator outputs in a high-impedance state during power-up or power-down. The V CC disconnect feature ensures that if V CC is disconnected with the complementary supply within recommended operating conditions, outputs are disabled and set to the high-impedance state while the supply current is maintained. The Ioff-float circuitry is designed so that no excessive current is drawn from or sourced into an input or output while the supply is floating. Glitch-free power supply sequencing allows for the supply rail to be powered on or off in any order, while providing robust power sequencing performance.

7.2 Functional Block Diagram

OE_B VCCA VCCB B1Y B2Y B3Y GNDB OE_A Figure 7-1. TXG4041 Functional Block Diagram www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25

OE_B VCCA VCCB B1Y B2Y A3Y GNDB OE_A Figure 7-2. TXG4042 Functional Block Diagram TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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7.3 Feature Description

7.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in Section 5.5. The worst case resistance is calculated with the maximum input voltage, given in Section 5.1, and the maximum input leakage current, given in Section 5.5, using Ω's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the electrical characteristics, which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly increases dynamic current consumption of the device. See Understanding Schmitt Triggers for additional information regarding Schmitt-trigger inputs.

7.3.1.1 Inputs with Integrated Static Pull-Down Resistors

This device has 5M Ω typical integrated weak pull-downs for each input. This feature allows all inputs to be left floating without the concern for unstable outputs or increased current consumption. This also helps to reduce external component count for applications where not all channels are used or need to be fixed low. If an external pull-up is required, it must be no larger than 1MΩ to avoid contention with the 5MΩ internal pull-down.

7.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. Section 5.1 defines the electrical and thermal limits that must be followed at all times.

7.3.3 VCC Disconnect

The outputs for this device are disabled and enter a high-impedance state when either supply is left floating (disconnected), and with the complementary supply within recommended operating conditions. It is recommended that the inputs are kept low before floating (disconnecting) either supply. The ICCx(floating) in the Section 5.5 specifies the maximum supply current. The I off(float) in the Section 5.5 specifies the maximum leakage into or out of any input or output pin on the device. Hi-Z Hi-Z Io ( oat) Io ( oat) VCCA VCCA VCCB OE_B OE_A GNDA B1Y VCCB Disabled Supply disconnected ICCB maintained GNDB B4A4Y Disabled Figure 7-3. VCC Disconnect Feature

7.3.4 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Section 5.3. www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27

7.3.5 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the inputs or outputs (where the output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device configuration of the peripheral, or a false data initialization by the peripheral.

7.3.6 Negative Clamping Diodes

Figure 7-4 depicts the inputs and outputs to this device that have negative clamping diodes. CAUTION Voltages beyond the values specified in the Section 5.1 table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. GND Level Shifter Input or I/O configured as input VCCA Device -IIK -IOK VCCB I/O configured as output Figure 7-4. Electrical Placement of Clamping Diodes for Each Input and Output

7.3.7 Fully Configurable Dual-Rail Design

The V CCA and V CCB pins can be supplied at any voltage from 1.71V to 5.5V, making the device suitable for translating between any of the voltage nodes (1.8V, 3.3V, and 5.0V).

7.3.8 Supports High-Speed Translation

The TXG404x device can support high data-rate applications. The translated signal data rate can be up to 250Mbps when the signal is translated from 1.71V to 5.5V. TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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7.3.9 AC Noise Rejection

TXG404x supports I/O voltage translation in environments with noisy grounds. The plot below illustrates the amount of noise that GNDA and GNDB can reject in terms peak-to-peak voltage over frequency without disrupting communication between two systems. As an example, Figure 7-6 below shows GNDA with a ground bounce of 2VPP at 10kHz but still effectively translating 5V to 2.5V without any degradation. F r e q u e n c y ( H z ) Amplitude (VPP) 1 x 1 0 1 0 x 1 0 1 0 0 x 1 0 1 x 1 0 1 0 x 1 0 1 0 0 x 1 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 Figure 7-5. AC Noise Rejection Plot Figure 7-6. Waveform showing 5V to 2.5V I/O translation with AC Ground Noise of 2VPP at 10kHz www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29

7.4 Device Functional Modes

Table 7-1. Function Table Power Supply (1) Control Inputs Port Status VCCI VCCO OE Input Output PU PU H H H PU PU H L L PU PU L or Open X Hi-Z PU PU H Open L PD PU H X L X PU L or Open X High-Z X PU H X L X PD X X Undetermined (1) In the table above: PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level; Open = Floating TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TXG404x is used for level translation, enabling communication between devices or systems operating at different interface and ground voltages. The TXG404x device is ideal for use in applications where a push-pull driver is connected to the data inputs. Figure 8-1 is an example of two systems that translate from 1.8V to 3.3V across a SPI interface while also seeing a ground shift of -3V on GNDB while GNDA is at 0V. The ground shift of 3V is from the noisy power ground of the Digital-to-Analog Converter (DAC).

8.2 Typical Application

1.8 V 3.3 V 0.1 µF 0.1 µF TXGx041 CS CS OUT2IN2SCLK SCLK OE_A IN3 OUT4 OUT3 IN4 SDO SDI SDI SDO DAC 1.8 V GNDA GNDB OE_B 3.3 V Digital Ground Power Ground 0V -3V Figure 8-1. TXG404x in Test and Measurement

8.2.1 Design Requirements

Use the parameters listed in Table 8-1 for this design example. Table 8-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Input voltage range 1.71V to 5.5V Output voltage range 1.71V to 5.5V www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range – Use the supply voltage of the device that is driving the TXG404x device to determine the input voltage range. For a valid logic-high, the value must exceed the positive-going input-threshold voltage (VT+) of the input port. For a valid logic low the value must be less than the negative-going input-threshold voltage (VT-) of the input port.
• Output voltage range – Use the supply voltage of the device that the TXG404x device is driving to determine the output voltage range.

8.2.3 Application Curve

Figure 8-2. Waveform showing -40V (top) and +40V (bottom) Ground Shift with 2.25V to 5V I/O Translation TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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8.3 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing without any supply sequencing requirements such as ramp order or ramp rate. Please make sure the difference between VCC and GND remains at 6.5V max at all times.

8.4 Layout

8.4.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1µF capacitor is recommended, but transient performance can be improved by having 1µF and 0.1µF capacitors in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
• A 0.1µF capacitor can be added between GNDA and GNDB to improve performances of CMTI.

8.4.2 Layout Example

B G Legend TXGx041 (DBQ Package) GND IN1 IN2 IN3 OUT4 OE_A GNDA VCCA VCCB OUT1 OUT2 OUT3 IN4 OE_B GNDB GND A 1 116 115 114 113 512 511 510 G G B 0.1uF 0.1uF Power Domain A Power Domain B A G G B Figure 8-3. Layout Example www.ti.com TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Understanding Schmitt Triggers application report
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2025) to Revision A (September 2025) Page

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TXG4041, TXG4042 SCES987A – JUNE 2025 – REVISED SEPTEMBER 2025 www.ti.com

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www.ti.com 17-Dec-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TXG4041DBQR Active Production SSOP (DBQ) | 16 2500 | LARGE T&R - NIPDAU Level-2-260C-1 YEAR -40 to 125 TGX041 TXG4041DYYR Active Production SOT-23-THIN (DYY) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TGX041 TXG4042DBQR Active Production SSOP (DBQ) | 16 2500 | LARGE T&R - NIPDAU Level-2-260C-1 YEAR -40 to 125 TGX042 TXG4042DYYR Active Production SOT-23-THIN (DYY) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TGX042 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 17-Dec-2025 OTHER QUALIFIED VERSIONS OF TXG4041, TXG4042 :

• Automotive : TXG4041-Q1 , TXG4042-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TXG4041DYYR SOT-23- THIN TXG4042DYYR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXG4041DBQR SSOP DBQ 16 2500 353.0 353.0 32.0 TXG4041DYYR SOT-23-THIN DYY 14 2500 336.6 336.6 31.8 TXG4042DBQR SSOP DBQ 16 2500 353.0 353.0 32.0 TXG4042DYYR SOT-23-THIN DYY 14 2500 336.6 336.6 31.8 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP-.244.228 -6.195.80[ ] .069 MAX [1.75] 14X .0250 [0.635] 16X -.012.008 -0.300.21[ ] .175 [4.45] TYP-.010.005 -0.250.13[ ] - 8 -.010.004 -0.250.11[ ] (.041 ) [1.04] .010 [0.25] GAGE PLANE -.035.016 -0.880.41[ ] A NOTE 3 -.197.189 -5.004.81[ ] B NOTE 4 -.157.150 -3.983.81[ ] SSOP - 1.75 mm max heightDBQ0016A SHRINK SMALL-OUTLINE PACKAGE 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. 1 16 .007 [0.17] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .002 MAX [0.05] ALL AROUND .002 MIN [0.05] ALL AROUND (.213) [5.4] 14X (.0250 ) [0.635] 16X (.063) [1.6] 16X (.016 ) [0.41] SSOP - 1.75 mm max heightDBQ0016A SHRINK SMALL-OUTLINE PACKAGE 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:8X SYMM 8 9 SEE DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 16X (.063) [1.6] 16X (.016 ) [0.41] 14X (.0250 ) [0.635] (.213) [5.4] SSOP - 1.75 mm max heightDBQ0016A SHRINK SMALL-OUTLINE PACKAGE 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X SYMM SYMM 8 9

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11

0.1 C A B

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

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