TXG4021DDFR

TXG4020_V03 TI2 | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 47

Technical content

TXG402x 2-bit, ±40V Ground-Level Translator

1 Features

• Supports DC shifts up to ±40V
• AC Noise Rejection of 80VPP up to 5MHz
• CMTI of 1kV/µs
• Low Prop Delay (<5ns) and Ch-Ch Skew (<0.20ns)
• Greater than 250Mbps
• Low power consumption (0.8mA per channel at 1Mbps, 1.8V)
• Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
• 4, 2, 1 channel devices with multiple configurations will be available
• Two device variants: – TXG4020: 2 forward – TXG4021: 1 forward, 1 reverse
• Supports VCC disconnect feature (I/Os are forced into high-Z)
• Schmitt-trigger inputs allows for slow and noisy signals
• Inputs with integrated static pull-down resistors prevent channels from floating
• Operating temperature from –40°C to +125°C
• Latch-up performance exceeds 100mA per JESD 78, class II – ESD protection exceeds JESD 22 – 2500V human-body model – 500V charged-device model
• Package options provided: – DSG (WSON-8) – DDF (SOT-8) – D (SOIC-8) System #1 System #2INx OUTx VccA GndA VccB GndB TXG VccA GndA VccB GndB Parasi c capacitance/ resistance <40V Simplified Diagram

2 Applications

• Test and Measurement
• Industrial Automation
• Appliances
• Robotics
• Avionics

3 Description

The TXG402x is a 2-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ± 40V. Compared to traditional level shifters, the TXG402x family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance. VCCA is referenced to GNDA and V CCB is referenced to GNDB. Ax pins are referenced to V CCA logic level while Bx pins are referenced to V CCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. The leakage between GNDA and GNDB is <90nA when VCC to GND is shorted. The TXG402x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 80VPP up to 5MHz (Figure 7-5 ). This device can support multiple interfaces such as UART, GPIO, and JTAG.

Package Information

NUMBER PACKAGE (1) BODY SIZE (NOM) TXG4020 TXG4021 DSG (WSON-8) 2.0mm × 2.00mm DDF (SOT-8) 2.90mm × 1.60mm D (SOIC-8) 4.90mm × 3.90mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

2 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

4 Pin Configuration and Functions

Figure 4-1. TXGx021DSG Package 8-Pin WSON Top View Table 4-1. TXGx021 DSG Pin Functions PIN I/O DESCRIPTION Name TXGx021 A1 2 I Input A1. Referenced to VCCA A2Y 3 O Output A2. Referenced to VCCA B1Y 7 O Output B1. Referenced to VCCB B2 6 I Input B2. Referenced to VCCB VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 8 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 4 — Ground reference for VCCA GNDB 5 — Ground reference for VCCB — Thermal pad — Keep thermal pad floating. www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3

Figure 4-2. TXGx020DSG Package 8-Pin WSON Top View Table 4-2. TXGx020 DSG Pin Functions PIN I/O DESCRIPTION Name TXGx020 A1 2 I Input A1. Referenced to VCCA A2 3 I Input A2. Referenced to VCCA B1Y 7 O Output B1. Referenced to VCCB B2Y 6 O Output B2. Referenced to VCCB VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 8 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 4 — Ground reference for VCCA GNDB 5 — Ground reference for VCCB — Thermal pad — Keep thermal pad floating. TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

8 VCCB

Figure 4-3. TXGx021DDF 8-Pin SOT and TXGx021D 8-pin SOIC Top View Table 4-3. TXGx021 DDF and D Pin Functions PIN I/O DESCRIPTION Name TXGx021 A1 2 I Input A1. Referenced to VCCA A2Y 3 O Output A2. Referenced to VCCA B1Y 7 O Output B1. Referenced to VCCB B2 6 I Input B2. Referenced to VCCB VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 8 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 4 — Ground reference for VCCA GNDB 5 — Ground reference for VCCB www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5

Figure 4-4. TXGx020DDF 8-Pin SOT and TXGx020D 8-pin SOIC Top View Table 4-4. TXGx020 DDF and D Pin Functions PIN I/O DESCRIPTION Name TXGx020 A1 2 I Input A1. Referenced to VCCA A2 3 I Input A2. Referenced to VCCA B1Y 7 O Output B1. Referenced to VCCB B2Y 6 O Output B2. Referenced to VCCB VCCA 1 — A side supply voltage. 1.71V ≤ VCCA ≤ 5.5V VCCB 8 — B side supply voltage. 1.71V ≤ VCCB ≤ 5.5V GNDA 4 — Ground reference for VCCA GNDB 5 — Ground reference for VCCB TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA to VGNDA Supply voltage A to Ground voltage A –0.5 6.5 V VCCB to VGNDB Supply voltage B to Ground voltage B –0.5 6.5 V VGNDA to VGNDB Voltage between GNDA and GNDB Voltage between GNDA and GNDB -45 45 V VI Input Voltage(2) I/O Ports (A Port) to VGNDA –0.5 6.5 V I/O Ports (B Port) to VGNDB –0.5 6.5 VO Voltage applied to any output in the high-impedance or power-off state(2) A Port to VGNDA –0.5 6.5 V B Port to VGNDB –0.5 6.5 VO Voltage applied to any output in the high or low state(2) (3) A Port to VGNDA –0.5 VCCA + 0.5 V B Port to VGNDB –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IO Continuous output current –25 25 mA Continuous current through VCC or GND –100 100 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Section 5.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 Exposure beyond the limits listed in Section 5.3 may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5V maximum if the output current rating is observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN TYP MAX UNIT VCCA Supply voltage A - Relative to GNDA 1.71 5.5 V VCCB Supply voltage B - Relative to GNDB 1.71 5.5 V VGNDA to VGNDB Voltage between GNDA and GNDB Voltage between GNDA and GNDB Voltage between GNDA and GNDB -40 40 V IOH High-level output current VCCO = 1.71V –4.5 mA VCCO = 2.3V –8 VCCO = 3V –10 VCCO = 4.5V –12 IOL Low-level output current VCCO = 1.71V 4.5 mA VCCO = 2.3V 8 VCCO = 3V 10 VCCO = 4.5V 12 VI Input voltage - Relative to GNDA 0 5.5 V VO Output voltage - Relative to GNDB 0 VCCO V TA Operating free-air temperature –40 125 °C (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the device. The input leakage from these weak pulldowns is defined by the II specification indicated under Section 5.5.

5.4 Thermal Information

THERMAL METRIC(1) TXG802x UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 122.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 60.7 °C/W RθJB Junction-to-board thermal resistance 69.8 °C/W YJT Junction-to-top characterization parameter 11.5 °C/W YJB Junction-to-board characterization parameter 68.8 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX VOH High-level output voltage (3) IOH = –4.5mA 1.71V 1.71V 1.5 V IOH = –8mA 2.3V 2.3V 2.0 IOH = –10mA 3V 3V 2.7 IOH = –12mA 4.5V 4.5V 4.1 VOL Low-level output voltage (4) IOL = 4.5mA 1.71V 1.71V 0.16 V IOL = 8mA 2.3V 2.3V 0.27 IOL = 10mA 3V 3V 0.34 IOL = 12mA 4.5V 4.5V 0.41 VT+ Positive-going input- threshold voltage Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71V 1.71V 1.11 V 2.3V 2.3V 1.40 3V 3V 1.73 4.5V 4.5V 2.45 5.5V 5.5V 3.0 VT- Negative-going input- threshold voltage Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71V 1.71V 0.56 V 2.3V 2.3V 0.80 3V 3V 1.14 4.5V 4.5V 1.59 5.5V 5.5V 2.0 ΔVT Input-threshold hysteresis (VT+ – VT-) Data Inputs (Ax, Bx) (Referenced to VCCI) 1.71V 1.71V 0.3 0.55 V2.3V 2.3V 0.36 0.60 3V 3V 0.38 0.54 4.5V 4.5V 0.41 0.86 V ΔVT Input-threshold hysteresis (VT+ – VT-) Data Inputs (Ax, Bx) (Referenced to VCCI) 5.5V 5.5V 0.40 0.96 V II Input leakage current Data Inputs (Ax, Bx) VI = VCCI or GND Ioff-float Floating supply Partial power down current A Port or B Port VI = VCC Floating(5) 0V - 5.5V 0.26 1.55 µA 0V - 5.5V Floating(5) 0.26 1.55 www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX Ioff-float Floating supply Partial power down current A Port or B Port VI = GND Floating(5) 0V - 5.5V 0.06 nA Ioff-float Floating supply Partial power down current 0V - 5.5V Floating(5) 0.39 nA Ci Control Input Capacitance VI = 3.3V or VGNDA 3.3V 3.3V 2 pF Cio Data I/O Capacitance VO = 1.71V DC +1MHz -16dBm sine wave 3.3V 3.3V 1.3 2.6 pF CGND Cap between grounds All channels combined (VCC both sides are powered on) 46 pF All channels combined (VCC to GND shorted) 53 pF Leakage Current Leakage between GndA to GndB All channels combined (VCC both sides are powered on and inputs are all low) All channels combined (VCC both sides are powered on and inputs are all high) 1.71V – 5.5V 1.71V – 5.5V 32 µA All channels combined CMTI Common Mode Transient Immunity Input toggling at 100Mbps Ground shift up to 40V 1.71V – 5.5V 1.71V – 5.5V 1 kV/µs VUVLO+ Positive-Going Undervoltage Lockout Voltage A Supply 1.71V – 5.5V 1.64 V B Supply 1.71V – 5.5V 1.64 V VUVLO- Negative-Going Undervoltage Lockout Voltage A Supply 1.71V – 5.5V 1.2 V B Supply 1.71V – 5.5V 1.2 V VUVLO_Hys Undervoltage Lockout Hysteresis A Supply 1.71V – 5.5V 58 mV B Supply 1.71V – 5.5V 58 mV (1) VCCI is the VCC associated with the input port and referenced to GNDA (2) VCCO is the VCC associated with the output port and referenced to GNDB (3) Tested at VI = VT+(MAX) (4) Tested at VI = VT-(MIN) (5) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.6 Supply Current

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX TXGx021 ICCA VCCA supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 300 747 µA 0V 5.5V -2 12.5 5.5V 0V 349 589 VI = GND IO = 0 5.5V Floating(3) 347 577 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 497 1077 µA 0V 5.5V 546 919 5.5V 0V -2 24.5 VI = GND IO = 0 Floating(3) 5.5V 548 919 ICCA + ICCB Supply Current - DC Signal VI = VCCI 1.8V 1.8V 0.7 1.6 mA 2.5V 2.5V 0.8 1.6 3.3V 3.3V 0.8 1.7 5V 5V 0.8 1.9 VI = GND 1.8V 1.8V 0.7 1.6 mA 2.5V 2.5V 0.8 1.6 3.3V 3.3V 0.8 1.7 5V 5V 0.8 1.9 www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX ICCA + ICCB Supply Current - AC Signal All channels switching with square wave clock input; CL = 15pF, 1Mbps 1.8V 1.8V 0.9 1.6 mA 2.5V 2.5V 0.9 1.6 3.3V 3.3V 0.9 1.7 5V 5V 1.1 2 All channels switching with square wave clock input; CL = 15pF, 50Mbps 1.8V 1.8V 4.6 6.3 mA 2.5V 2.5V 5.5 7.3 3.3V 3.3V 6.8 8.2 5V 5V 8.7 10.7 All channels switching with square wave clock input; CL = 15pF, 100Mbps 1.8V 1.8V 8.5 10.6 mA 2.5V 2.5V 10 13 3.3V 3.3V 12 14.7 5V 5V 16.6 20.2 TXGx020 ICCA VCCA supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 299 602 µA 0V 5.5V -2.5 1.2 µA 5.5V 0V 302 602 µA VI = GND IO = 0 5.5V Floating(3) 299 577 µA ICCB VCCB supply current VI = VCCI or GND IO = 0 1.71V – 5.5V 1.71V – 5.5V 504 1225 µA 0V 5.5V 486 906 µA 5.5V 0V -2 24.5 µA VI = GND IO = 0 Floating(3) 5.5V 486 906 µA ICCA + ICCB Supply Current - DC Signal VI = VCCI 1.8V 1.8V 0.7 1.6 mA 2.5V 2.5V 0.8 1.6 mA 3.3V 3.3V 0.8 1.7 mA 5V 5V 0.8 1.9 mA VI = GND 1.8V 1.8V 0.7 1.6 mA 2.5V 2.5V 0.8 1.6 mA 3.3V 3.3V 0.8 1.7 mA 5V 5V 0.8 1.9 mA TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

over operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 125°C MIN TYP MAX ICCA + ICCB Supply Current - AC Signal All channels switching with square wave clock input; CL = 15pF, 1Mbps 1.8V 1.8V 0.9 1.6 mA 2.5V 2.5V 0.9 1.6 mA 3.3V 3.3V 0.9 1.7 mA 5V 5V 1.1 2 mA All channels switching with square wave clock input; CL = 15pF, 50Mbps 1.8V 1.8V 4.5 6.3 mA 2.5V 2.5V 5.5 7.3 mA 3.3V 3.3V 6.3 8 mA 5V 5V 8.4 10.7 mA All channels switching with square wave clock input; CL = 15pF, 100Mbps 1.8V 1.8V 8.5 10.7 mA 2.5V 2.5V 10 13 mA 3.3V 3.3V 12 14.7 mA 5V 5V 16.6 20.2 mA (1) VCCI is the VCC associated with the input port and referenced to GNDA (2) VCCO is the VCC associated with the output port and referenced to GNDB (3) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA 5.7 Switching Characteristics, VCCA = 1.8 ± 0.15V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns PWD Pulse width distortion |tphl - tplh| ns www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13

CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tr Output signal rise time ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.33V µs tPU Time from ULVO to valid output data µs 5.8 Switching Characteristics, VCCA = 2.5 ± 0.2V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

14 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.33V µs tPU Time from ULVO to valid output data µs 5.9 Switching Characteristics, VCCA = 3.3 ± 0.3V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns tf Output signal fall time ns www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15

CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tDO Default output delay time from input power loss Measured from the time VCC goes below 1.33V tPU Time from ULVO to valid output data 5.10 Switching Characteristics, VCCA = 5.0 ± 0.5V PARAMETER TEST CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay 1Mbps all 4 channels toggling ns PWD Pulse width distortion |tphl - tplh| ns tr Output signal rise time ns tf Output signal fall time ns tDO Default output delay time from input power loss Measured from the time VCC goes below 1.33V µs TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

16 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

CONDITIONS FROM TO TEMPERATURE B-Port Supply Voltage (VCCB) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tPU Time from ULVO to valid output data µs

5.11 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO No Translation 1.65V - 1.95V 1.65V - 1.95V 264 Mbps 2.3V - 2.7V 2.3V - 2.7V 220 3.0V - 3.6V 3.0V - 3.6V 220 4.5V - 5.5V 4.5V - 5.5V 176 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO Up Translation 1.65V - 1.95V 2.3V - 2.7V 264 Mbps 1.65V - 1.95V 3.0V - 3.6V 264 1.65V - 1.95V 4.5V - 5.5V 264 2.3V - 2.7V 3.0V - 3.6V 220 2.3V - 2.7V 4.5V - 5.5V 220 3.0V - 3.6V 4.5V - 5.5V 176 TMAX - Maximum Data Rate 50% Duty Cycle Input One channel switching 20% of pulse > 0.7*VCCO 20% of pulse < 0.3*VCCO Down Translation 2.3V - 2.7V 1.65V - 1.95V 264 Mbps 3.0V - 3.6V 2.3V - 2.7V 220 3.0V - 3.6V 1.65V - 1.95V 220 4.5V - 5.5V 3.0V - 3.6V 176 4.5V - 5.5V 1.65V - 1.95V 220 4.5V - 5.5V 1.65V - 1.95V 220 tsk - Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) No Translation ns www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCI VCCO Operating free-air temperature (TA) UNIT-40°C to 125°C MIN TYP MAX tsk - Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) Up Translation ns tsk - Output skew Timing skew between any switching outputs on the rising or falling edge (same direction channels) Down Translation ns TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

18 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

5.12 Typical Characteristics

TA = 25°C (unless otherwise noted) I O H - O u t p u t H i g h C u r r e n t ( m A ) VOH- Output High Voltage 0 2 4 6 8 1 0 1 2 1 4 1 6 1 . 5 2 . 5 3 . 5 4 . 5 V C C = 1 . 8 V V C C = 2 . 5 V V C C = 3 . 3 V V C C = 5 V Figure 5-1. Output High Voltage (VOH) vs Source Current (IOH) I O L - O u t p u t L o w C u r r e n t ( m A ) VOL- Output Low Voltage (V) 0 3 6 9 1 2 1 5 0 . 0 5 0 . 1 0 . 1 5 0 . 2 0 . 2 5 0 . 3 0 . 3 5 0 . 4 0 . 4 5 V C C = 1 . 8 V V C C = 2 . 5 V V C C = 3 . 3 V V C C = 5 V Figure 5-2. Output Low Voltage (VOL) vs Sink Current (IOL) I C C - S u p p l y C u r r e n t ( m A ) VIN- Input Voltage (V) 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 V C C = 1 . 8 V V C C = 2 . 5 V V C C = 3 . 3 V V C C = 5 V Figure 5-3. Supply Current (ICCA) vs Input Voltage (VIN) [TXG0x021] V I N - I n p u t V o l t a g e ( V ) ICC- Suppy Current (mA) 0 . 6 0 . 7 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 . 6 1 . 7 1 . 8 I C C = 1 . 8 V I C C = 2 . 5 V I C C = 3 . 3 V I C C = 5 V Figure 5-4. Supply Current (ICCB) vs Input Voltage (VIN) [TXG0x021] V I N - I n p u t V o l t a g e ( V ) ICC- Supply Current (mA) 0 . 4 0 . 6 0 . 8 1 . 2 1 . 4 1 . 6 V C C = 1 . 8 V V C C = 2 . 5 V V C C = 3 . 3 V V C C = 5 V Figure 5-5. Supply Current (ICCA) vs Input Voltage (VIN) [TXGx020] T e m p e r a t u r e ( C ) Propagation Delay (ns) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 4 . 3 4 . 6 4 . 9 5 . 2 5 . 5 5 . 8 V C C = 1 . 8 V V C C = 2 . 5 V V C C = 3 . 3 V V C C = 5 V Figure 5-6. Propagation Delay, TPLH, vs Temperature www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19

T e m p e r a t u r e ( C ) Propagation Delay (ns) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 4 . 5 5 . 5 6 . 5 V C C = 1 . 8 V V C C = 2 . 5 V V C C = 3 . 3 V V C C = 5 V Figure 5-7. Propagation Delay, TPHL, vs Temperature F r e e - A i r T e m p e r a t u r e ( C ) Power Supply UVLO Threshold (V) - 4 0 - 1 5 1 0 3 5 6 0 8 5 1 1 0 1 2 5 1 . 2 1 . 2 5 1 . 3 1 . 3 5 1 . 4 1 . 4 5 1 . 5 1 . 5 5 1 . 6 V C C A + V C C A - V C C B + V C C B - Figure 5-8. Power Supply Undervoltage Threshold vs Free-Air Temperature TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

20 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

6 Parameter Measurement Information

6.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, generators supply all input pulses that have the following characteristics:

• f = 1MHz
• ZO = 50Ω
• Δt/ΔV ≤ 1ns/V Output Pin Under Test CL (1) RL RL GND Open 2 x VCCO Measurement Point A. CL includes probe and jig capacitance. Figure 6-1. Load Circuit Table 6-1. Load Circuit Conditions Parameter VCCO RL CL S1 VTP tpd Propagation (delay) time 1.71V – 5.5V 10kΩ 15pF Open N/A VO VI VOL VOH VCCI 0 V tr tf tPLH tPHL 50% 50% 50% 50% 90% 10% 1. VCCI is the supply pin associated with the input port. 2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1 Figure 6-2. Switching Characteristics Voltage Waveforms www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21

1.2 V 50% tDO default low VO VI VOH VCC 0 V 1.64 V tPU 1. VCCI is the supply pin associated with the input port. 2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1 Figure 6-3. Default Output Delay Time & Time from UVLO to Valid Output Voltage Waveform IN OUT VCCO CL See Note A GNDOGNDI + – VCM VOH or VOL VCCI Pass-fail criteria: The output must remain stable. IN 10ns 1. CL = 15pF and includes instrumentation and fixture capacitance within ±20%. Figure 6-4. Common-Mode Transient Immunity Test Circuit TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

22 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TXG402x is a 2-bit ground-level translator that uses two individually configurable power-supply rails which allows it to translate across two different power domains. The device is operational with V CCA and VCCB supplies as low as 1.71V and as high as 5.5V. The A port is designed to track V CCA and the B port is designed to track VCCB. In addition to I/O level shifting, this translator can support a difference of - 40V to + 40V between GNDA and GNDB. VCCA is referenced to GNDA and VCCB is referenced to GNDB. The TXG402x device is designed for asynchronous communication between data buses, and transmits data with fixed direction from the A bus to the B bus on some channels and from the B bus to the A bus on the remaining channels. The V CC disconnect feature ensures that if V CC is disconnected with the complementary supply within recommended operating conditions, outputs are disabled and set to the high-impedance state while the supply current is maintained. The I off-float circuitry ensures that no excessive current is drawn from or sourced into an input or output while the supply is floating. Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.

7.2 Functional Block Diagram

Figure 7-1. TXG4021 Functional Block Diagram VCCA GNDA B1Y GNDB B2YA2 VCCB Figure 7-2. TXG4020 Functional Block Diagram www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23

7.3 Feature Description

7.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Section 5.5. The worst case resistance is calculated with the maximum input voltage, given in the Section 5.1, and the maximum input leakage current, given in the Section 5.5, using ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Section 5.5, which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase dynamic current consumption of the device. See Understanding Schmitt Triggers for additional information regarding Schmitt- trigger inputs.

7.3.1.1 Inputs with Integrated Static Pull-Down Resistors

This device has 5M Ω typical integrated weak pull-downs for each input. This feature allows all inputs to be left floating without the concern for unstable outputs or increased current consumption. This also helps to reduce external component count for applications where not all channels are used or need to be fixed low. If an external pull-up is required, it should be no larger than 1MΩ to avoid contention with the 5MΩ internal pull-down.

7.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. Section 5.1 defines the electrical and thermal limits that must be followed at all times.

7.3.3 VCC Disconnect

The outputs for this device are disabled and enter a high-impedance state when either supply is left floating (disconnected), and with the complementary supply within recommended operating conditions. It is recommended that the inputs are kept low before floating (disconnecting) either supply. The ICCx(floating) in the Section 5.5 specifies the maximum supply current. The I off(float) in the Section 5.5 specifies the maximum leakage into or out of any input or output pin on the device. Hi-Z Hi-Z Ioff(float) Ioff(float) VCCA GNDA B1YDisabled Supply disconnected ICCB maintained GNDB B2A2Y Disabled VCCB VCCA VCCB Figure 7-3. VCC Disconnect Feature

7.3.4 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Section 5.3.

7.3.5 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the inputs or outputs (that is, where the output erroneously transitions to V CC when it should be held low or vice versa). Glitches of this TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

24 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

nature can be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device configuration of the peripheral, or even a false data initialization by the peripheral.

7.3.6 Negative Clamping Diodes

Figure 7-4 depicts the inputs and outputs to this device that have negative clamping diodes. CAUTION Voltages beyond the values specified in the Section 5.1 table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. GND Level Shifter Input or I/O configured as input VCCA Device -IIK -IOK VCCB I/O configured as output Figure 7-4. Electrical Placement of Clamping Diodes for Each Input and Output

7.3.7 Fully Configurable Dual-Rail Design

The V CCA and V CCB pins can be supplied at any voltage from 1.71V to 5.5V, making the device suitable for

7.3.8 Supports High-Speed Translation

The TXG402x device can support high data-rate applications. The translated signal data rate can be greater than 250Mbps when the signal is translated from 1.71V to 5.5V. www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25

7.3.9 AC Noise Rejection

TXG402x supports I/O voltage translation in environments with noisy grounds. The plot below illustrates the amount of noise that GNDA and GNDB can reject in terms peak-to-peak voltage over frequency without disrupting communication between two systems. As an example, Figure 7-6 below shows GNDA with a ground bounce of 2VPP at 10kHz but still effectively translating 5V to 2.5V without any degradation. F r e q u e n c y ( H z ) Amplitude (VPP) 1 x 1 0 1 0 x 1 0 1 0 0 x 1 0 1 x 1 0 1 0 x 1 0 1 0 0 x 1 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 Figure 7-5. AC Noise Rejection Plot Figure 7-6. Waveform showing 5V to 2.5V I/O translation with AC Ground Noise of 2VPP at 10kHz TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

7.4 Device Functional Modes

Table 7-1. Function Table Power Supply Port Status VCCI VCCO Input Output PU PU H H PU PU L L PU PU Open L PD PU X L 1. In the table above: PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level; Open = Floating www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TXG402x is used for level translation, enabling communication between devices or systems operating at different interface and ground voltages. The TXG402x device is ideal for use in applications where a push-pull driver is connected to the data inputs. Figure 8-1 is an example of two systems that translate from 1.8V to 3.3V across an UART interface while also seeing a ground shift of -3V on GNDB while GNDA is at 0V. The ground shift of 3V is from the noisy power ground of the Digital-to-Analog Converter (DAC).

8.2 Typical Application

1.8 V 3.3 V 0.1 µF 0.1 µF TXGx021 TX RX IN2OUT2RX TX DAC GNDA GNDB Digital Ground Power Ground 0V -3V Figure 8-1. TXG4021 in Test and Measurement

8.2.1 Design Requirements

Use the parameters listed in Table 8-1 for this design example. Table 8-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Input voltage range 1.71V to 5.5V Output voltage range 1.71V to 5.5V

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range – Use the supply voltage of the device that is driving the TXG402x device to determine the input voltage range. For a valid logic-high, the value must exceed the positive-going input-threshold voltage (VT+) of the TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

28 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

input port. For a valid logic low the value must be less than the negative-going input-threshold voltage (VT-) of the input port.

• Output voltage range – Use the supply voltage of the device that the TXG402x device is driving to determine the output voltage range.

8.2.3 Application Curves

Figure 8-2. Waveform showing -40V (top) and +40V (bottom) Ground Shift with 5V to 2.5V I/O Translation www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29

8.3 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing without any supply sequencing requirements such as ramp order or ramp rate. Please make sure the difference between VCC and GND remains at 6.5V max at all times.

8.4 Layout

8.4.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1µF capacitor is recommended, but transient performance can be improved by having 1µF and 0.1µF capacitors in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
• A 0.1µF capacitor can be added between GNDA and GNDB to improve performances of CMTI.

8.4.2 Layout Example

B G Legend TXGx020 (D Package) IN1 IN2 GNDA VCCA VCCB OUT2 GNDB OUT1 A 1 G B 0.1uF 0.1uF Power Domain A Power Domain B G G G Figure 8-3. D Layout Example TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

30 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

9 Device and Documentation Support

9.1 Device Support

9.1.1 Regulatory Requirements

No statutory or regulatory requirements apply to this device. There are no special characteristics for this product.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Understanding Schmitt Triggers application report
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (June 2025) to Revision A (July 2025) Page DATE REVISION NOTES June 2025 * Initial Release www.ti.com TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TXG4020, TXG4021 SCES995A – JUNE 2025 – REVISED JULY 2025 www.ti.com

32 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

www.ti.com 29-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PTXG4021DR Active Preproduction SOIC (D) | 8 3000 | LARGE T&R - Call TI Call TI -40 to 125 TXG4020DDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T4020 TXG4020DR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TGX020 TXG4020DSGR Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes Call TI Level-1-260C-UNLIM -40 to 125 41JH TXG4021DDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T4021 TXG4021DR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TGX021 TXG4021DSGR Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes Call TI Level-1-260C-UNLIM -40 to 125 41KH (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 29-Jul-2026 OTHER QUALIFIED VERSIONS OF TXG4020, TXG4021 :

• Automotive : TXG4020-Q1 , TXG4021-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TXG4020DDFR SOT-23- THIN TXG4021DDFR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXG4020DDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TXG4020DR SOIC D 8 3000 340.5 336.1 32.0 TXG4020DSGR WSON DSG 8 3000 210.0 185.0 35.0 TXG4021DDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TXG4021DR SOIC D 8 3000 340.5 336.1 32.0 TXG4021DSGR WSON DSG 8 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6)

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WSON - 0.8 mm max heightDSG 8 PLASTIC SMALL OUTLINE - NO LEAD2 x 2, 0.5 mm pitch 4224783/A

www.ti.com PACKAGE OUTLINE C 8X 0.3 0.2 1.6 0.1 1.5 0.9 0.1 6X 0.5 8X 0.4 0.2 0.05 0.00

0.8 MAX

0.08 MAX

A 2.1 1.9 B 2.1 1.9

0.1 MIN

(0.2) TYP WSON - 0.8 mm max heightDSG0008D PLASTIC SMALL OUTLINE - NO LEAD 4231093/B 06/2026 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 PIN 1 ID 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only. SCALE 5.500 SCALE 30.000 SECTION A-A SECTION A-A OPTIONAL: SIDE WALL PIN DETAIL TYPICAL SCALE 40.000 OPTIONAL: SIDE WALL PIN DETAIL NOTE 4

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.25) (1.6) (1.9) 6X (0.5) (0.9) ( 0.2) VIA TYP (0.55) 8X (0.5) (R0.05) TYP WSON - 0.8 mm max heightDSG0008D PLASTIC SMALL OUTLINE - NO LEAD 4231093/B 06/2026 SYMM 4 5 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X SYMM 9 NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.25) 8X (0.5) (0.9) (0.7) (1.9) (0.45) 6X (0.5) WSON - 0.8 mm max heightDSG0008D PLASTIC SMALL OUTLINE - NO LEAD 4231093/B 06/2026 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM METAL SYMM

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025