TXB0104_V01 TI | Alldatasheet

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Technical content

TXB0104 4-Bit Bidirectional Voltage-level Translator With Automatic Direction Sensing and ±15-kV ESD Protection

1 Features

  • 1.2-V to 3.6-V on A Port and 1.65-V to 5.5-V on B Port (VCCA ≤ VCCB)
  • V CC Isolation Feature: If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • Output Enable (OE) Input Circuit Referenced to VCCA
  • Low Power Consumption, 5-μA Maximum I CC
  • I OFF Supports Partial Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22 – A Port:
  • 2500-V Human-Body Model (A114-B)
  • 1500-V Charged-Device Model (C101) – B Port:
  • ±15-kV Human-Body Model (A114-B)
  • 1500-V Charged-Device Model (C101)

2 Applications

  • Headsets
  • Smartphones
  • Tablets
  • Desktop PC

3 Description

This TXB0104 4-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V CCB. V CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5- V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. V CCA must not exceed VCCB. When the OE input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor The current sourcing capability of the driver determines the minimum value of the resistor. The TXB0104 device is designed so the OE input circuit is supplied by VCCA. This device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the outputs, which prevents damaging current backflow through the device when the device is powered down. Device Information (1)PART NUMBER PACKAGE BODY SIZE (NOM) TXB0104RUT UQFN (12) 2.00 mm × 1.70 mm TXB0104D SOIC (14) 8.65 mm × 3.91 mm TXB0104ZXU/GXU BGA MICROSTAR JUNIOR ™ (12) 2.00 mm × 2.50 mm TXB0104PW TSSOP (14) 5.00 mm × 4.40 mm TXB0104RGY VQFN (14) 3.50 mm × 3.50 mm TXB0104YZT DSBGA (12) 1.40 mm × 1.90 mm TXB0104NMN NFBGA (12) 2.00 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Processor Peripheral VCCA VCCB Typical Application Block Diagram for TXB010X www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: TXB0104 TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.16 Operating Characteristics: VCCA = 1.2 V to 1.5 6.17 Operating Characteristics: VCCA = 1.8 V to 3.3 12.1 Receiving Notification of Documentation Updates..23

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (March 2018) to Revision J (October 2020) Page Changes from Revision H (January 2018) to Revision I (March 2018) Page Changes from Revision G (November 2014) to Revision H (January 2018) Page Changes from Revision F (May 2012) to Revision G (November 2014) Page

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. GXU and ZXU Package 12-Pin BGA Microstar Junior Top View A B C Figure 5-2. NMN Package 12-Pin NFBGA Top View PLACEHOLDER D C B A 3 2 1 Figure 5-3. YZT Package 12-Pin DSBGA Top View 1 1 OEGND NC VCCA NC VCCB NC − No internal connection Figure 5-4. D or PW Package 14-Pin SOIC or TSSOP Top View Exposed Center Pad 1 14 7 8 1 1 NC NC OE V CCB GND V CCA NC − No internal connection Figure 5-5. RGY Package 14-Pin VQFN With Exposed Thermal Pad Top View VCCB 4 8 1 112 VCCA OE GND B45 7A4 Figure 5-6. RUT Package 12-Pin UQFN Top View www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TXB0104

Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME D, PW RGY RUT GXU, ZXU, NMN YZT A1 2 2 2 A1 A3 I/O Input/output 1. Referenced to VCCA. A2 3 3 3 A2 B3 I/O Input/output 2. Referenced to VCCA. A3 4 4 4 A3 C3 I/O Input/output 3. Referenced to VCCA. A4 5 5 5 A4 D3 I/O Input/output 4. Referenced to VCCA. B1 13 13 10 C1 A1 I/O Input/output 1. Referenced to VCCB. B2 12 12 9 C2 B1 I/O Input/output 2. Referenced to VCCB. B3 11 11 8 C3 C1 I/O Input/output 3. Referenced to VCCB. B4 10 10 7 C4 D1 I/O Input/output 4. Referenced to VCCB. GND 7 7 6 B4 D2 — Ground NC 6, 9 6,9 — – – — No connection. Not internally connected. OE 8 8 12 B3 C2 I Tri-state output-mode enable. Pull OE low to place all outputs in tri-state mode. Referenced to VCCA. VCCA 1 1 1 B2 B2 — A-port supply voltage 1.2 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB. VCCB 14 14 11 B1 A2 — B-port supply voltage 1.65 V ≤ VCCB ≤ 5.5 V. Therma l pad — — – – — For the RGY package, the exposed center thermal pad must either be connected to Ground or left electrically open. Pin Assignments: NMN, GXU and ZXU Package A B C

4 A4 GND B4

3 A3 OE B3

2 A2 VCCA B2

1 A1 VCCB B1

Pin Assignments: YZT Package 3 2 1 D A4 GND B4 C A3 OE B3 B A2 VCCA B2 A A1 VCCB B1 TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VCCA –0.5 4.6 V Supply voltage, VCCB –0.5 6.5 Input voltage, VI A port –0.5 4.6 V B port –0.5 6.5 Voltage applied to any output in the high-impedance or power-off state, VO A port –0.5 4.6 V B port -0.5 6.5 Voltage applied to any output in the high or low state, VO (2) A port –0.5 VCCA + 0.5 V B port –0.5 VCCB + 0.5 Input clamp current, IIK VI < 0 –50 mA Output clamp current, IOK VO < 0 –50 mA Continuous output current, IO –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA Junction temperature range, TJ 150 °C Storage temperature range, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The value of V CCA and VCCB are provided in the recommended operating conditions table.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) A port ±2.5 kV Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) B port ±15 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) A port ±1.5 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) B port ±1.5 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TXB0104

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB Supply voltage 1.65 5.5 VIH High-level input voltage Data inputs VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V VCCI × 0.65(3) VCCI V OE VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V VCCA × 0.65 5.5 VIL Low-level input voltage Data inputs VCCA = 1.2 V to 5.5 V VCCB = 1.65 V to 5.5 V 0 VCCI × 0.35(3) V OE VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 0 VCCA × 0.35 VO Voltage applied to any output in the high-impedance or power-off state A-port VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 0 3.6 V B-port VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 0 5.5 Δt/Δv Input transition rise or fall rate A-port inputs VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 40 ns/V B-port inputs VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 3.6 V 40 VCCB = 4.5 V to 5.5 V 30 TA Operating free-air temperature –40 85 °C (1) The A and B sides of an unused data I/O pair must be held in the same state, that is, both at V CCI or both at GND. (2) V CCA must be less than or equal to VCCB and must not exceed 3.6 V. (3) V CCI is the supply voltage associated with the input port.

6.4 Thermal Information

THERMAL METRIC(1) TXB0104 UNITD GXU/ZXU PW RGY RUT YZT NMN

14 PINS 12 PINS 14 PINS 14 PINS 12 PINS 12 PINS 12 PINS

RθJA Junction-to-ambient thermal °C/W Rθ JC(top) Junction-to-case (top) thermal RθJB Junction-to-board thermal ψJT Junction-to-top characterization ψJB Junction-to-board Rθ JC(bot) Junction-to-case (bottom) (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report. TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER(1) (2) TEST CONDITIONS VCCA VCCB TA = 25°C –40°C to 85°C UNIT MIN TYP MAX MIN MAX VOHA Port A output high voltage IOH = –20 μA 1.2 V 1.1 V 1.4 V to 3.6 V VCCA – 0.4 VOLA Port A output low voltage IOL = 20 μA 1.2 V 0.3 V 1.4 V to 3.6 V 0.4 VOHB Port B output high voltage IOH = –20 μA 1.65 V to 5.5 V VCCB – 0.4 V VOLB Port B output low voltage IOL = 20 μA 1.65 V to 5.5 V 0.4 V II Inflection-point current OE: VI = VCCI or GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA Ioff Off-state current A port: VI or VO = 0 to 3.6 V 0 V 0 V to 5.5 V –1 1 –2 2 μA B port: VI or VO = 0 to 5.5 V 0 V to 3.6 V 0 V –1 1 –2 2 IOZ High- impedance- state output current A or B port: OE = GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA ICCA VCCA supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 0.06 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5

3.6 V 0 V 2

0 V 5.5 V –2 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 3.4 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5

3.6 V 0 V –2

0 V 5.5 V 2 ICCA + ICCB Combined supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 3.5 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 10 ICCZA High- impedance state, VCCA supply current VI = VCCI or GND IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 0.05 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 ICCZB High- impedance state, VCCB supply current VI = VCCI or GND IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 3.3 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 Ci Input capacitance OE 1.2 V to 3.6 V 1.65 V to 5.5 V 3 4 pF Cio Input-to-output internal capacitance A port 1.2 V to 3.6 V 1.65 V to 5.5 V 5 6 pF B port 1.2 V to 3.6 V 1.65 V to 5.5 V 11 14 (1) V CCI is the supply voltage associated with the input port. (2) V CCO is the supply voltage associated with the output port. www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TXB0104

6.6 Timing Requirements: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Data rate 20 20 20 20 Mbps tw Pulse duration Data inputs 50 50 50 50 ns 6.7 Timing Requirements: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate 40 40 40 40 Mbps tw Pulse duration Data inputs 25 25 25 25 ns 6.8 Timing Requirements: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate 60 60 60 60 Mbps tw Pulse duration Data inputs 17 17 17 17 ns 6.9 Timing Requirements: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX Data rate 100 100 100 Mbps tw Pulse duration Data inputs 10 10 10 ns 6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX Data rate 100 100 Mbps tw Pulse duration Data inputs 10 10 ns TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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6.11 Switching Characteristics: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V PARAMETER TEST CONDITIONS VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay time ns B-to-A 7.4 6.4 6 5.8 ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time OE-to-A 18 15 14 14 ns OE-to-B 20 17 16 16 trA, tfA Input rise time, input fall time A-port rise and fall times 4.2 4.2 4.2 4.2 ns trB, tfB Input rise time, input fall time B-port rise and fall times 2.1 1.5 1.2 1.1 ns tSK(O) Skew (time), output Channel-to- channel skew 0.4 0.5 0.5 1.4 ns Maximum data rate 20 20 20 20 Mbps 6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay time ns ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time ns trA, tfA Input rise time, input fall time A-port rise and fall times trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 0.5 ns Maximum data rate 40 40 40 40 Mbps www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TXB0104

6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay time ns ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time ns trA, tfA Input rise time, input fall time A-port rise and fall times trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 0.5 ns Maximum data rate 60 60 60 60 Mbps 6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX MIN MAX tpd Propagatio n delay time ns ten Enable time OE-to-A 1 1 1 μs OE-to-B 1 1 1 tdis Disable time ns trA, tfA Input rise time, input fall time A-port rise and fall times 0.8 3 0.8 3 0.8 3 ns trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 ns Maximum data rate 100 100 100 Mbps TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX tpd Propagation delay time A-to-B 0.9 4.7 0.8 4 ns B-to-A 1 4.9 0.9 3.8 ten Enable time OE-to-A 1 1 μs OE-to-B 1 1 tdis Disable time OE-to-A 4.6 15.2 4.3 12.1 ns OE-to-B 3.8 16 3.4 13.2 trA, tfA Input rise time, input fall time A-port rise and fall times 0.7 2.5 0.7 2.5 ns trB, tfB Input rise time, input fall time B-port rise and fall times 0.5 2.1 0.4 2.7 ns tSK(O) Skew (time), output Channel-to-channel skew 0.5 0.5 ns Maximum data rate 100 100 Mbps www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TXB0104

TA = 25°C PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = VCCA (outputs enabled) A-port input, B-port output 7.8 10 9 pF B-port input, A-port output 12 11 11 CpdB Power dissipation capacitance A-port input, B-port output 38.1 28 28 B-port input, A-port output 25.4 19 18 CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = GND (outputs disabled) A-port input, B-port output 0.01 0.01 0.01 pF B-port input, A-port output 0.01 0.01 0.01 CpdB Power dissipation capacitance A-port input, B-port output 0.01 0.01 0.01 B-port input, A-port output 0.01 0.01 0.01 6.17 Operating Characteristics: VCCA = 1.8 V to 3.3 V, VCCB = 1.8 V to 5 V TA = 25°C PARAMETER TEST CONDITIONS VCCA = 1.8 V, VCCB =1.8 V VCCA = 2.5 V, VCCB = 2.5 V VCCA = 2.5 V, VCCB = 5 V VCCA = 3.3 V, VCCB = 3.3 V to 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = VCCA (outputs enabled) A-port input, B-port output 8 8 8 9 pF B-port input, A-port output 11 11 11 11 CpdB Power dissipation capacitance A-port input, B-port output 28 29 29 29 B-port input, A-port output 18 19 21 22 CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = GND (outputs disabled) A-port input, B-port output 0.01 0.01 0.01 0.01 pF B-port input, A-port output 0.01 0.01 0.01 0.01 CpdB Power dissipation capacitance A-port input, B-port output 0.01 0.01 0.01 0.03 B-port input, A-port output 0.01 0.01 0.01 0.04 TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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6.18 Typical Characteristics

VCCA (V) OE Pin Input Capacitance (pF) 0 0.5 1 1.5 2 2.5 3 3.5 4 D001 25qC (Room Temperature) 85qC VCCB= 3.3 V Figure 6-1. Input Capacitance for OE Pin (CI) vs Power Supply (VCCA) VCCA (V) A Port I/O Capacitance (pF) 0 0.5 1 1.5 2 2.5 3 3.5 4 D002 25qC (Room Temperature) 85qC VCCB= 3.3 V Figure 6-2. Capacitance for A port I/O Pins (CiO) vs Power Supply (VCCA) VCCB (V) B Port I/O Capacitance (pF) D003 25qC (Room Temperature) 85qC VCCA= 1.8 V Figure 6-3. Capacitance for B Port I/O Pins (CiO) vs Power Supply (VCCB) www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TXB0104

7 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators that have the following characteristics:

  • PRR 10 MHz
  • Z O = 50 W
  • dv/dt ≥ 1 V/ns Note All parameters and waveforms are not applicable to all devices. 15 pF From Output Under Test 1 M A. The outputs are measured one at a time, with one transition per measurement. Figure 7-1. Load Circuit For Maximum Data Rate: Pulse Duration, Propagation Delay Output Rise, And Fall Time Measurement From Output Under Test 15 pF 50 k Open 2 x VCCO 50 k A. The outputs are measured one at a time, with one transition per measurement. Figure 7-2. Load Circuit For Enable and Disable Time Measurement Table 7-1. Switch Position For Enable and Disable Time Measurement (See Figure 7-2 ) TEST S1 tPZL, tPLZ 2 × VCCO tPHZ, tPZH Open TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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0.9 V CCO

0.1 V CCO

A. V CCI is the VCC associated with the input port. B. V CCO is theVCC associated with the output port. C. t PLH and tPHL are the same as tpd. D. The outputs are measured one at a time, with one transition per measurement. Figure 7-3. Voltage Waveforms Propagation Delay Times VCCI 0 V Input tw VCCI / 2 V CCI / 2 Figure 7-4. Voltage Waveforms Pulse Duration www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TXB0104

8 Detailed Description

8.1 Overview

The TXB0104 device is a 4-bit, directionless voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots) to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open-drain signal translation, please refer to TI’s TXS010X products.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Architecture

The TXB0104 device architecture (see Figure 8-1 ) does not require a direction-control signal to control the direction of data flow from A to B or from B to A. In a DC state, the output drivers of the device maintain a high or low, but are designed to be weak, so the output drivers can be overdriven by an external driver when data on the bus flows the opposite direction. The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V. A B VCCA VCCB One Shot One Shot One Shot One Shot Figure 8-1. Architecture of TXB0104 Device I/O Cell www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TXB0104

8.3.2 Input Driver Requirements

Typical IIN vs VIN characteristics of the device are shown in Figure 8-2. For proper operation, the device driving the data I/Os of the TXB0104 device must have drive strength of at least ±2 mA. IIN VIN VT /4 k ±(VD ± VT)/4 k A. V T is the input threshold of the TXB0104 device, (typically VCC / 2). B. V D is the supply voltage of the external driver. Figure 8-2. Typical IIN vs VIN Curve

8.3.3 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths must be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the device output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects. TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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Product Folder Links: TXB0104

8.3.4 Enable and Disable

The TXB0104 device has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the high-impedance (Hi-Z) state. The disable time (t dis) indicates the delay between when OE goes low and when the outputs acutally get disabled (Hi-Z). The enable time (t en) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

8.3.5 Pullup or Pulldown Resistors on I/O Lines

The device is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0104 device have low dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0104 device. For the same reason, the TXB0104 device must not be used in applications such as I 2C or 1-Wire where an open-drain driver is connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx series of level translators.

8.4 Device Functional Modes

The device has two functional modes, enabled and disabled. To disable the device, set the OE input to low, which places all I/Os in a high impedance state. Setting the OE input to high will enable the device. www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TXB0104

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TXB0104 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. It can only translate push-pull CMOS logic outputs. If for open-drain signal translation, please refer to TI TXS010X products. Any external pulldown or pullup resistors are recommended larger than 50 kΩ.

9.2 Typical Application

1.8 V System Controller TXB0104 3.3 V System 0.1 F 3.3 V 0.1 F 1.8 V VCCA VCCB OE GND Data Data

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. And make sure the VCCA ≤ VCCB. Table 9-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUE Input voltage range 1.2 V to 3.6 V Output voltage range 1.65 V to 5.5 V TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range - Use the supply voltage of the device that is driving the TXB0104 device to determine the input voltage range. For a valid logic high, the value must exceed the V IH of the input port. For a valid logic low, the value must be less than the VIL of the input port.
  • Output voltage range - Use the supply voltage of the device that the device is driving to determine the output voltage range. - External pullup or pulldown resistors are not recommended. If mandatory, it is recommended that the value must be larger than 50 kΩ.
  • An external pulldown or pullup resistor decreases the output V OH and V OL. Use the below equations to draft estimate the VOH and VOL as a result of an external pulldown and pullup resistor. VOH = VCCx × RPD / (RPD + 4.5 kΩ) VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ) Where
  • VCCx is the output port supply voltage on either VCCA or VCCB
  • RPD is the value of the external pull down resistor
  • RPU is the value of the external pull up resistor
  • 4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line.

9.2.3 Application Curves

Figure 9-1. Level-Translation of a 2.5-MHz Signal www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TXB0104

10 Power Supply Recommendations

During operation, ensure that V CCA ≤ VCCB at all times. During power-up sequencing, V CCA ≥ VCCB does not damage the device, so any power supply can be ramped up first. The device has circuitry that disables all output ports when either VCC is switched off (VCCA/B = 0 V). The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until V CCA and V CCB are fully ramped and stable. The minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.

  • Bypass capacitors must be used on power supplies, and must be placed as close as possible to the V CCA, VCCB pin and GND pin.
  • Short trace-lengths must be used to avoid excessive loading.
  • PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the source driver.

11.2 Layout Example

0.1 F 0.1 F To Controller To Controller To Controller To Controller Bypass Capacitor Bypass Capacitor TXB0104PWR VCCA VCCB NC GND NC OE To System To System To System To System LEGEND Polygonal Copper Pour VIA to Power Plane VIA to GND Plane (Inner Layer) Keep OE low until VCCA and VCCB are powered up TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

™ is a trademark of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TXB0104 SCES650J – APRIL 2006 – REVISED OCTOBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TXB0104

SCES650J – APRIL 2006 – REVISED OCTOBER 2020 www.ti.com

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Product Folder Links: TXB0104

www.ti.com 15-Oct-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples HPA01164RUTR ACTIVE UQFN RUT 12 3000 Green (RoHS & no Sb/Br) NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR, 2KV) TXB0104D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104NMNR ACTIVE NFBGA NMN 12 2500 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR -40 to 85 2AQW TXB0104PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RUTR ACTIVE UQFN RUT 12 3000 Green (RoHS & no Sb/Br) NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR, 2KV) TXB0104YZTR ACTIVE DSBGA YZT 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (2K, 2K7) TXB0104ZXUR ACTIVE BGA MICROSTAR JUNIOR ZXU 12 2500 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 YE04 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 15-Oct-2020 Addendum-Page 2 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXB0104 :

  • Automotive: TXB0104-Q1 NOTE: Qualified Version Definitions:
  • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TXB0104ZXUR BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 17-Oct-2020 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXB0104DR SOIC D 14 2500 367.0 367.0 38.0 TXB0104PWR TSSOP PW 14 2000 367.0 367.0 35.0 TXB0104RGYR VQFN RGY 14 3000 367.0 367.0 35.0 TXB0104RUTR UQFN RUT 12 3000 189.0 185.0 36.0 TXB0104RUTR UQFN RUT 12 3000 202.0 201.0 28.0 TXB0104YZTR DSBGA YZT 12 3000 182.0 182.0 20.0 TXB0104ZXUR BGA MICROSTAR JUNIOR ZXU 12 2500 350.0 350.0 43.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Oct-2020 Pack Materials-Page 2

D: Max = E: Max = 1.89 mm, Min = 1.39 mm, Min = 1.83 mm 1.33 mm

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. NanoFree is a trademark of Texas Instruments. PACKAGE OUTLINE 4225768/A 03/2020 www.ti.com NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY NMN0012A A 0.08 C

0.15 C A B

0.05 C B SYMM SYMM BALL A1 CORNER

1 MAX

0.25 0.19 SEATING PLANE 2.6 2.4 2.1 1.9

1.5 TYP

(0.5 ) TYP (0.5 ) TYP

0.5 TYP

A B C 1 2 3 4 12X Ø 0.35 0.25 C

NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature number SNVA009 (www.ti.com/lit/snva009). EXAMPLE BOARD LAYOUT 4225768/A 03/2020 www.ti.com NFBGA - 1 mm max heightNMN0012A PLASTIC BALL GRID ARRAY SYMM SYMM LAND PATTERN EXAMPLE SCALE: 20X (0.5) TYP (0.5) TYP SOLDER MASK DETAILS NOT TO SCALE

0.05 MAX

0.05 MIN

(PREFERRED) SOLDER MASK DEFINED (Ø 0.25) METAL EXPOSED METAL METAL UNDER SOLDER MASK (Ø 0.25) SOLDER MASK OPENING A B C 1 2 3 4 12X (Ø0.25)

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. EXAMPLE STENCIL DESIGN 4225768/A 03/2020 www.ti.com NFBGA - 1 mm max heightNMN0012A PLASTIC BALL GRID ARRAY SOLDER PASTE EXAMPLE BASED ON 0.100 mm THICK STENCIL SCALE: 20X SYMM SYMM (0.5) TYP (0.5) TYP A B C 1 2 3 4 12X ( 0.25) (R0.05) TYP

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