TXB0104DR

TXB0104_17 TI1 | Alldatasheet

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Sample & Buy T echnical Documents Tools & Software Support & Community TXB0104 SCES650G –APRIL 2006–REVISED NOVEMBER 2014 TXB01044-BitBidirectionalVoltage-levelTranslatorWithAutomaticDirectionSensing and±15-kVESDProtection

1 Features 3 Description

This 4-bit non-inverting translator uses two separate 1• 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B GND, All Outputs Are in the High-Impedance track VCCB. VCCB accepts any supply voltage from State 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V,• OE Input Circuit Referenced to VCCA When the output-enable (OE) input is low, all outputs• Latch-Up Performance Exceeds 100 mA Per are placed in the high-impedance state. To ensureJESD 78, Class II the high-impedance state during power up or power

• ESD Protection Exceeds JESD 22 down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is– A Port determined by the current-sourcing capability of the– 2500-V Human-Body Model (A114-B) driver. – 1500-V Charged-Device Model (C101) The TXB0104 is designed so that the OE input circuit– B Port is supplied by VCCA. – ±15-kV Human-Body Model (A114-B) This device is fully specified for partial-power-down– 1500-V Charged-Device Model (C101) applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow 2 Applications through the device when it is powered down.
• Headset Device Information(1)
• Smartphone PART NUMBER PACKAGE BODY SIZE (NOM)
• Tablet UQFN (12) 2.00 mm x 1.70 mm
• Desktop PC SOIC (14) 8.65 mm x 3.91 mm BGA MICROSTAR 2.00 mm x 2.50 mm TXB0104 JUNIOR (12) TSSOP (14) 5.00 mm x 4.40 mm VQFN (14) 3.50 mm x 3.50 mm DSBGA (12) 1.40 mm x 1.90 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Block Diagram for TXB010X An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SCES650G –APRIL 2006–REVISED NOVEMBER 2014 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2012) to Revision G Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information Changes from Revision E (February 2010) to Revision F Page

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Product Folder Links: TXB0104

(TOP VIEW) GND NC VCCA NC VCCB RGY PACKAGE Exposed Center Pad (TOP VIEW) 1 14 7 8 NC NC OE V CCB GND V CCA VCCB RUT PACKAGE (TOP VIEW) 4 8 1112 VCCA OE GND B45 7A4 GXU/ZXU PACKAGE (TOP VIEW) A B C YZT PACKAGE (TOP VIEW) D C B A 3 2 1 TXB0104 www.ti.com SCES650G –APRIL 2006–REVISED NOVEMBER 2014

5 Pin Configuration and Functions

A. N.C. − No internal connection B. For RGY, if the exposed center pad is used, it must only be connected as a secondary ground or left electrically open. C. Pullup resistors are not required on both sides for Logic I/O. D. If pull up or pull down resistors are needed, the resistor value must be over 50 kΩ. E. 50 kΩ is a safe recommended value, if the customer can accept higher VOL or lower VOH, smaller pullup or pulldown resistor is allowed, the draft estimation is VOL = VCCOUT × 4.5 k/(4.5 k + RPU) and VOH = VCCOUT × RDW/(4.5 k + RDW). F. If pullup resistors are needed, please refer to the TXS0104 or contact TI. G. For detailed information, please refer to application note SCEA043. Pin Functions PIN BALL FUNCTIOND, PW, OR GXU/NAME RUT NO. YZT NO.RGY NO. ZXU NO. VCCA 1 1 B2 B2 A-port supply voltage 1.2 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB. A1 2 2 A1 A3 Input/output 1. Referenced to VCCA. A2 3 3 A2 B3 Input/output 2. Referenced to VCCA. A3 4 4 A3 C3 Input/output 3. Referenced to VCCA. A4 5 5 A4 D3 Input/output 4. Referenced to VCCA. NC 6 – – – No connection. Not internally connected. GND 7 6 B4 D2 Ground 3-state output-mode enable. Pull OE low to place all outputs in 3-stateOE 8 12 B3 C2 mode. Referenced to VCCA. Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TXB0104

SCES650G –APRIL 2006–REVISED NOVEMBER 2014 www.ti.com Pin Functions (continued) PIN BALL FUNCTIOND, PW, OR GXU/NAME RUT NO. YZT NO.RGY NO. ZXU NO. NC 9 – – – No connection. Not internally connected. B4 10 7 C4 D1 Input/output 4. Referenced to VCCB. B3 11 8 C3 C1 Input/output 3. Referenced to VCCB. B2 12 9 C2 B1 Input/output 2. Referenced to VCCB. B1 13 10 C1 A1 Input/output 1. Referenced to VCCB. VCCB 14 11 B1 A2 B-port supply voltage 1.65 V ≤ VCCB ≤ 5.5 V. Pin Assignments (GXU / ZXU Package) A B C

4 A4 GND B4

3 A3 OE B3

2 A2 VCCA B2

1 A1 VCCB B1

Pin Assignments (YZT Package) 3 2 1 D A4 GND B4 C A3 OE B3 B A2 VCCA B2 A A1 VCCB B1

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Product Folder Links: TXB0104

www.ti.com SCES650G –APRIL 2006–REVISED NOVEMBER 2014

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCA –0.5 4.6 Supply voltage range V VCCB –0.5 6.5 A port –0.5 4.6 VI Input voltage range V B port –0.5 6.5 A port –0.5 4.6Voltage range applied to any output in the high-impedance orVO Vpower-off state B port -0.5 6.5 A port –0.5 VCCA + 0.5Voltage range applied to any output in the high or lowVO Vstate(2) B port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The value of VCCA and VCCB are provided in the recommended operating conditions table.

6.2 Handling Ratings

Tstg Storage temperature range –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2.5pins(1), A Port Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –15 15pins(1), B Port V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification 1.5JESD22-C101, all pins(2), A Port Charged device model (CDM), per JEDEC specification 1.5JESD22-C101, all pins(2), B Port (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2) VCCA VCCB MIN MAX UNIT VCCA 1.2 3.6 Supply voltage V VCCB 1.65 5.5 VIH High-level input voltage V VIL Low-level input voltage V Voltage range applied to any A-port 0 3.6 VO output in the high-impedance 1.2 V to 3.6 V 1.65 V to 5.5 V V B-port 0 5.5or power-off state (1) The A and B sides of an unused data I/O pair must be held in the same state, i.e., both at VCCI or both at GND. (2) VCCA must be less than or equal to VCCB and must not exceed 3.6 V. (3) VCCI is the supply voltage associated with the input port. Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TXB0104

SCES650G –APRIL 2006–REVISED NOVEMBER 2014 www.ti.com Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted)(1)(2) VCCA VCCB MIN MAX UNIT A-port inputs 1.2 V to 3.6 V 1.65 V to 5.5 V 40 Input transitionΔt/Δv 1.65 V to 3.6 V 40 ns/Vrise or fall rate B-port inputs 1.2 V to 3.6 V 4.5 V to 5.5 V 30 TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) D GXU/ZXU PW RGY RUT YZT UNIT

14 PINS 12 PINS 14 PINS 14 PINS 12 PINS 12 PINS

°C/W RθJC(bot) Junction-to-case (bottom) thermal ─ ─ ─ ─ ─ ─resistance (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics(1)(2)

over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C –40°C to 85°C PARAMETER TEST CONDITIONS VCCA VCCB UNIT MIN TYP MAX MIN MAX 1.2 V 1.1 VOHA IOH = –20 μA VVCCA1.4 V to 3.6 V – 0.4 1.2 V 0.3 VOLA IOL = 20 μA V 1.4 V to 3.6 V 0.4 VCCBVOHB IOH = –20 μA 1.65 V to 5.5 V V– 0.4 VOLB IOL = 20 μA 1.65 V to 5.5 V 0.4 V II OE VI = VCCI or GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA A port VI or VO = 0 to 3.6 V 0 V 0 V to 5.5 V –1 1 –2 2 Ioff μA B port VI or VO = 0 to 5.5 V 0 V to 3.6 V 0 V –1 1 –2 2 IOZ A or B port OE = GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA 1.2 V 1.65 V to 5.5 V 0.06 0 V 5.5 V –2 1.2 V 1.65 V to 5.5 V 3.4 0 V 5.5 V 2 (1) VCCI is the supply voltage associated with the input port. (2) VCCO is the supply voltage associated with the output port.

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www.ti.com SCES650G –APRIL 2006–REVISED NOVEMBER 2014 Electrical Characteristics(1)(2) (continued) over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C –40°C to 85°C PARAMETER TEST CONDITIONS VCCA VCCB UNIT MIN TYP MAX MIN MAX VI = VCCI or GND, 1.2 V 1.65 V to 5.5 V 0.05 ICCZA IO = 0, μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5OE = GND VI = VCCI or GND, 1.2 V 1.65 V to 5.5 V 3.3 ICCZB IO = 0, μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5OE = GND Ci OE 1.2 V to 3.6 V 1.65 V to 5.5 V 3 4 pF A port 5 6 Cio 1.2 V to 3.6 V 1.65 V to 5.5 V pF B port 11 14 6.6 Timing Requirements: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT TYP TYP TYP TYP Data rate 20 20 20 20 Mbps tw Pulse duration Data inputs 50 50 50 50 ns 6.7 Timing Requirements: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate 40 40 40 40 Mbps tw Pulse duration Data inputs 25 25 25 25 ns 6.8 Timing Requirements: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate 60 60 60 60 Mbps tw Pulse duration Data inputs 17 17 17 17 ns 6.9 Timing Requirements: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX Data rate 100 100 100 Mbps tw Pulse duration Data inputs 10 10 10 ns Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TXB0104

SCES650G –APRIL 2006–REVISED NOVEMBER 2014 www.ti.com 6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) VCCB = 3.3 V VCCB = 5 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX Data rate 100 100 Mbps tw Pulse duration Data inputs 10 10 ns 6.11 Switching Characteristics: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 VFROM TOPARAMETER UNIT(INPUT) (OUTPUT) TYP TYP TYP TYP A B 6.9 5.7 5.3 5.5 tpd ns B A 7.4 6.4 6 5.8 A 1 1 1 1 ten OE μs B 1 1 1 1 A 18 15 14 14 tdis OE ns B 20 17 16 16 trA, tfA A-port rise and fall times 4.2 4.2 4.2 4.2 ns trB, tfB B-port rise and fall times 2.1 1.5 1.2 1.1 ns tSK(O) Channel-to-channel skew 0.4 0.5 0.5 1.4 ns Max data rate 20 20 20 20 Mbps 6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tpd ns A 1 1 1 1 ten OE μs B 1 1 1 1 tdis OE ns tSK(O) Channel-to-channel skew 0.5 0.5 0.5 0.5 ns Max data rate 40 40 40 40 Mbps 6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tpd ns A 1 1 1 1 ten OE μs B 1 1 1 1

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Product Folder Links: TXB0104

www.ti.com SCES650G –APRIL 2006–REVISED NOVEMBER 2014 Switching Characteristics: VCCA = 1.8 V ± 0.15 V (continued) over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX tdis OE ns tSK(O) Channel-to-channel skew 0.5 0.5 0.5 0.5 ns Max data rate 60 60 60 60 Mbps 6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V FROM TO ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX tpd ns A 1 1 1 ten OE μs B 1 1 1 tdis OE ns trA, tfA A-port rise and fall times 0.8 3 0.8 3 0.8 3 ns tSK(O) Channel-to-channel skew 0.5 0.5 0.5 ns Max data rate 100 100 100 Mbps 6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) VCCB = 3.3 V VCCB = 5 V FROM TO ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX A B 0.9 4.7 0.8 4 tpd ns B A 1 4.9 0.9 3.8 A 1 1 ten OE μs B 1 1 A 4.6 15.2 4.3 12.1 tdis OE ns B 3.8 16 3.4 13.2 trA, tfA A-port rise and fall times 0.7 2.5 0.7 2.5 ns trB, tfB B-port rise and fall times 0.5 2.1 0.4 2.7 ns tSK(O) Channel-to-channel skew 0.5 0.5 ns Max data rate 100 100 Mbps Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TXB0104

SCES650G –APRIL 2006–REVISED NOVEMBER 2014 www.ti.com

6.16 Operating Characteristics

TA = 25°C VCCA VCCB PARAMETER TEST CONDITIONS UNIT3.3 V 5 V 1.8 V 1.8 V 1.8 V 2.5 V 5 V to 5 V TYP TYP TYP TYP TYP TYP TYP A-port input, B-port output 7.8 10 9 8 8 8 9CL = 0, f = 10 MHz,CpdA B-port input, A-port output 12 11 11 11 11 11 11tr = tf = 1 ns, pFOE = VCCAA-port input, B-port output 38.1 28 28 28 29 29 29 CpdB (outputs enabled)B-port input, A-port output 25.4 19 18 18 19 21 22

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Product Folder Links: TXB0104

6.17 Typical Characteristics

Figure 1. Input capacitance for OE pin (CI) vs Power Supply Figure 2. Capacitance for A port I/O pins (CiO) vs Power Figure 3. Capacitance for B port I/O pins (CiO) vs Power Supply (VCCB)

A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR/C011810 MHz, ZO = 50 W , dv/dt ≥/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr1 V/ns. C. The outputs are measured one at a time, with one transition per measurement. D. tPLH and tPHL are the same as tpd. E. V CCI is the VCC associated with the input port. F. VCCO is the VCC associated with the output port. G. All parameters and waveforms are not applicable to all devices.

1 M/C008715 pF 15 pF

7 Parameter Measurement Information

Figure 4. Load Circuits and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The TXB0104 device is a 4-bit, directionless voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots) to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open-drain signal translation, please refer to TI’s TXS010X products.

8.2 Functional Block Diagram

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A. V T is the input threshold voltage of the TXB0104 (typically VCCI/2). B. V D is the supply voltage of the external driver.

8.3 Feature Description

8.3.1 Architecture

flowing the opposite direction. Figure 5. Architecture of TXB0104 I/O Cell

8.3.2 Input Driver Requirements

the data I/Os of the TXB0104 must have drive strength of at least ±2 mA. Figure 6. Typical IIN vs VIN Curve

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www.ti.com SCES650G –APRIL 2006–REVISED NOVEMBER 2014 Feature Description (continued)

8.3.3 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXB0104 output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.

8.3.4 Enable and Disable

The TXB0104 has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the high-impedance (Hi-Z) state. The disable time (tdis) indicates the delay between when OE goes low and when the outputs acutally get disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

8.3.5 Pullup or Pulldown Resistors on I/O Lines

The TXB0104 is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0104 have low dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0104. For the same reason, the TXB0104 should not be used in applications such as I2C or 1-Wire where an open- drain driver is connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx series of level translators.

8.4 Device Functional Modes

The TXB0104 device has two functional modes, enabled and disabled. To disable the device, set the OE input to low, which places all I/Os in a high impedance state. Setting the OE input to high will enable the device. Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TXB0104

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

recommended larger than 50 kΩ.

9.2 Typical Application

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 1. And make sure the VCCA ≤VCCB. Table 1. Design Parameters

9.2.2 Detailed Design Procedure

• Input voltage range - Use the supply voltage of the device that is driving the TXB0104 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
• Output voltage range - Use the supply voltage of the device that the TXB0104 device is driving to determine the output voltage range. - Don’t recommend to have the external pullup or pulldown resistors. If mandatory, it is recommended the value should be larger than 50 kΩ.
• An external pulldown or pullup resistor decreases the output VOH and VOL. Use the below equations to draft estimate the VOH and VOL as a result of an external pulldown and pullup resistor. VOH = VCCx × RPD / (RPD + 4.5 kΩ) VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ)

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• VCCx is the output port supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor
• RPU is the value of the external pull up resistor
• 4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line.

9.2.3 Application Curves

Figure 7. Level-Translation of a 2.5-MHz Signal

SCES650G –APRIL 2006–REVISED NOVEMBER 2014 www.ti.com

10 Power Supply Recommendations

During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not damage the device, so any power supply can be ramped up first. The TXB0104 has circuitry that disables all output ports when either VCC is switched off (VCCA/B = 0 V). The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.

• Bypass capacitors should be used on power supplies. And should be placed as close as possible to the VCCA, VCCB pin and GND pin
• Short trace-lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the source driver.

11.2 Layout Example

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12 Device and Documentation Support

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TXB0104

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples HPA01164RUTR ACTIVE UQFN RUT 12 3000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR ~ 2KV) TXB0104D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RUTR ACTIVE UQFN RUT 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR ~ 2KV) TXB0104YZTR ACTIVE DSBGA YZT 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (2K ~ 2K7) TXB0104ZXUR ACTIVE BGA MICROSTAR JUNIOR ZXU 12 2500 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 YE04 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.

www.ti.com 15-Apr-2017 Addendum-Page 2 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXB0104 :

• Automotive: TXB0104-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TXB0104ZXUR BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXB0104DR SOIC D 14 2500 367.0 367.0 38.0 TXB0104PWR TSSOP PW 14 2000 367.0 367.0 35.0 TXB0104RGYR VQFN RGY 14 3000 367.0 367.0 35.0 TXB0104RUTR UQFN RUT 12 3000 189.0 185.0 36.0 TXB0104YZTR DSBGA YZT 12 3000 182.0 182.0 20.0 TXB0104ZXUR BGA MICROSTAR JUNIOR ZXU 12 2500 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 Pack Materials-Page 2

D: Max = E: Max = 1.89 mm, Min = 1.39 mm, Min = 1.83 mm 1.33 mm

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