TXB0104BQAR.A

TXB0104 TI2 | Alldatasheet

Document overview

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Technical content

TXB0104 4-Bit Bidirectional Voltage-Level Translator With Automatic Direction Sensing and ±15kV ESD Protection

1 Features

• 1.2V to 3.6V on A port and 1.65V to 5.5V on B port (VCCA ≤ VCCB)
• VCC isolation feature: if either VCC input ss at GND, all outputs are in the high-impedance state
• Output enable (OE) input circuit referenced to VCCA
• Low power consumption, 5μA maximum ICC
• I OFF supports partial power-down mode operation
• Latch-up Performance Exceeds 100mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 – A Port:
• 2500V Human-Body Model (A114-B)
• 1500V Charged-Device Model (C101) – B Port:
• ±15kV Human-Body Model (A114-B)
• 1500V Charged-Device Model (C101)

2 Applications

• Headsets
• Smartphones
• Tablets
• Desktop PC Processor Peripheral VCCA VCCB Typical Application Block Diagram for TXB010X

3 Description

This TXB0104 4-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track V CCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5V voltage nodes. V CCA must not exceed VCCB. When the OE input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor The current sourcing capability of the driver determines the minimum value of the resistor. The TXB0104 device is designed so the OE input circuit is supplied by VCCA. This device is fully specified for partial power- down applications using I OFF. The I OFF circuitry disables the outputs, which prevents damaging current backflow through the device when the device is powered down.

Package Information

PART NUMBER (1) PACKAGE BODY SIZE (NOM) TXB0104RUT UQFN (12) 2.00mm × 1.70mm TXB0104D SOIC (14) 8.65mm × 3.91mm TXB0104ZXU/GXU BGA MICROSTAR JUNIOR™ (12) 2.00mm × 2.50mm TXB0104PW TSSOP (14) 5.00mm × 4.40mm TXB0104RGY VQFN (14) 3.50mm × 3.50mm TXB0104YZT DSBGA (12) 1.40mm × 1.90mm TXB0104NMN NFBGA (12) 2.00mm × 2.50mm TXB0104BQA WQFN (14) 3.00mm × 2.50mm TXB0104DYY SOT (14) 4.20mm × 2.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

5.12 Switching Characteristics: VCCA = 1.2 V (BQA/ 5.13 Switching Characteristics: VCCA = 1.2 V (Other 5.14 Switching Characteristics: VCCA = 1.5 V ± 0.1 V 5.15 Switching Characteristics: VCCA = 1.5 V ± 0.1 V 5.16 Switching Characteristics: VCCA = 1.8 V ± 0.15 5.17 Switching Characteristics: VCCA = 1.8 V ± 0.15 5.18 Switching Characteristics: VCCA = 2.5 V ± 0.2 V 5.19 Switching Characteristics: VCCA = 2.5 V ± 0.2 V 5.20 Switching Characteristics: VCCA = 3.3 V ± 0.3 V 5.21 Switching Characteristics: VCCA = 3.3 V ± 0.3 V 5.22 Operating Characteristics: VCCA = 1.2 V to 1.5 5.23 Operating Characteristics: VCCA = 1.8 V to 3.3 11.1 Receiving Notification of Documentation Updates.. 26

13 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

Figure 4-1. GXU and ZXU Package, 12-Pin BGA Microstar Junior (Top View) A B C Figure 4-2. NMN Package, 12-Pin NFBGA (Top View) PLACEHOLDER D C B A 3 2 1 Figure 4-3. YZT Package, 12-Pin DSBGA (Top View) 1 1 OEGND NC VCCA NC VCCB NC − No internal connection Figure 4-4. D/PW/DYY Package, 14-Pin SOIC/ TSSOP/SOT (Top View) Thermal Pad 2A1 3A2 4A3 5A4 6NC

7 GND

Figure 4-5. BQA Package, 14-Pin WQFN With Exposed Thermal Pad (Top View) Exposed Center Pad 1 14 7 8 1 1 NC NC OE V CCB GND V CCA NC − No internal connection Figure 4-6. RGY Package, 14-Pin VQFN With Exposed Thermal Pad (Top View) www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TXB0104

Figure 4-7. RUT Package, 12-Pin UQFN (Top View) Table 4-1. Pin Functions PIN I/O DESCRIPTION NAME D, PW BQA, RGY RUT GXU, ZXU, NMN YZT A1 2 2 2 A1 A3 I/O Input/output 1. Referenced to VCCA. A2 3 3 3 A2 B3 I/O Input/output 2. Referenced to VCCA. A3 4 4 4 A3 C3 I/O Input/output 3. Referenced to VCCA. A4 5 5 5 A4 D3 I/O Input/output 4. Referenced to VCCA. B1 13 13 10 C1 A1 I/O Input/output 1. Referenced to VCCB. B2 12 12 9 C2 B1 I/O Input/output 2. Referenced to VCCB. B3 11 11 8 C3 C1 I/O Input/output 3. Referenced to VCCB. B4 10 10 7 C4 D1 I/O Input/output 4. Referenced to VCCB. GND 7 7 6 B4 D2 — Ground NC 6, 9 6,9 — — — — No connection. Not internally connected. OE 8 8 12 B3 C2 I Tri-state output-mode enable. Pull OE low to place all outputs in tri-state mode. Referenced to VCCA. VCCA 1 1 1 B2 B2 — A-port supply voltage 1.2V ≤ VCCA ≤ 3.6V and VCCA ≤ VCCB. VCCB 14 14 11 B1 A2 — B-port supply voltage 1.65V ≤ VCCB ≤ 5.5V. Thermal pad — — — — — For the BQA, RGY package, the exposed center thermal pad must either be connected to Ground or left electrically open. Table 4-2. Pin Assignments: NMN, GXU and ZXU Package A B C

4 A4 GND B4

3 A3 OE B3

2 A2 VCCA B2

1 A1 VCCB B1

Table 4-3. Pin Assignments: YZT Package 3 2 1 D A4 GND B4 C A3 OE B3 B A2 VCCA B2 A A1 VCCB B1 TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VCCA –0.5 4.6 V Supply voltage, VCCB –0.5 6.5 Input voltage, VI A port –0.5 4.6 V B port –0.5 6.5 Voltage applied to any output in the high-impedance or power-off state, VO A port –0.5 4.6 V B port -0.5 6.5 Voltage applied to any output in the high or low state, VO (2) A port –0.5 VCCA + 0.5 V B port –0.5 VCCB + 0.5 Input clamp current, IIK VI < 0 –50 mA Output clamp current, IOK VO < 0 –50 mA Continuous output current, IO –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA Junction temperature range, TJ 150 °C Storage temperature range, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The value of VCCA and VCCB are provided in the recommended operating conditions table.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) A port ±2.5 kV Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) B port ±15 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) A port ±1.5 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) B port ±1.5 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TXB0104

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB Supply voltage 1.65 5.5 VIH High-level input voltage Data inputs VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V VCCI × 0.65(3) VCCI V OE VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V VCCA × 0.65 5.5 VIL Low-level input voltage Data inputs VCCA = 1.2 V to 5.5 V VCCB = 1.65 V to 5.5 V 0 VCCI × 0.35(3) V OE VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 0 VCCA × 0.35 VO Voltage applied to any output in the high-impedance or power-off state A-port VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 0 3.6 V B-port VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 0 5.5 Δt/Δv Input transition rise or fall rate A-port inputs VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 5.5 V 40 ns/V B-port inputs VCCA = 1.2 V to 3.6 V VCCB = 1.65 V to 3.6 V 40 VCCB = 4.5 V to 5.5 V 30 TA Operating free-air temperature –40 85 °C (1) The A and B sides of an unused data I/O pair must be held in the same state, that is, both at VCCI or both at GND. (2) VCCA must be less than or equal to VCCB and must not exceed 3.6 V. (3) VCCI is the supply voltage associated with the input port.

5.4 Thermal Information

THERMAL METRIC(1) TXB0104 UNI T D GXU/ZX U PW RGY RUT YZT NMN BQA DYY

14 PINS 12 PINS 14 PINS 14 PINS 12 PINS 12 PINS 12 PINS 14 PINS 14 PINS

RθJA Junction-to-ambient thermal °C/ W Rθ JC(top) Junction-to-case (top) RθJB Junction-to-board thermal ψJT Junction-to-top ψJB Junction-to-board Rθ JC(bot) Junction-to-case (bottom) thermal resistance ─ ─ ─ ─ ─ ─ ─ 23.3 - (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report. TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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5.5 Electrical Characteristics (BQA/DYY)

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER(1) (2) TEST CONDITIONS VCCA VCCB TA = 25°C –40°C to 85°C UNIT MIN TYP MAX MIN MAX VOHA Port A output high voltage IOH = –20 μA 1.2 V 1.1 V 1.4 V to 3.6 V VCCA – 0.4 VOLA Port A output low voltage IOL = 20 μA 1.2 V 0.3 V 1.4 V to 3.6 V 0.4 VOHB Port B output high voltage IOH = –20 μA 1.65 V to 5.5 V VCCB – 0.4 V VOLB Port B output low voltage IOL = 20 μA 1.65 V to 5.5 V 0.4 V II Inflection-point current OE: VI = VCCI or GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA Ioff Off-state current A port: VI or VO = 0 to 3.6 V 0 V 0 V to 5.5 V –1 1 –2 2 μA B port: VI or VO = 0 to 5.5 V 0 V to 3.6 V 0 V –1 1 –2 2 IOZ High- impedance- state output current A or B port: OE = GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA ICCA VCCA supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 0.4 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 3.6 V 0 V 2.5 0 V 5.5 V –2 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 3.4 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5

3.6 V 0 V –2

0 V 5.5 V 2 ICCA + ICCB Combined supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 3.5 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 10 ICCZA High- impedance state, VCCA supply current VI = VCCI or GND IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 0.4 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 ICCZB High- impedance state, VCCB supply current VI = VCCI or GND IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 3.3 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 Ci Input Cio Input-to-output internal capacitance A port 1.2 V to 3.6 V 1.65 V to 5.5 V 5 6 pF B port 1.2 V to 3.6 V 1.65 V to 5.5 V 11 14 (1) VCCI is the supply voltage associated with the input port. (2) VCCO is the supply voltage associated with the output port. www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TXB0104

5.6 Electrical Characteristics (Other Packages)

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER(1) (2) TEST CONDITIONS VCCA VCCB TA = 25°C –40°C to 85°C UNIT MIN TYP MAX MIN MAX VOHA Port A output high voltage IOH = –20 μA 1.2 V 1.1 V 1.4 V to 3.6 V VCCA – 0.4 VOLA Port A output low voltage IOL = 20 μA 1.2 V 0.3 V 1.4 V to 3.6 V 0.4 VOHB Port B output high voltage IOH = –20 μA 1.65 V to 5.5 V VCCB – 0.4 V VOLB Port B output low voltage IOL = 20 μA 1.65 V to 5.5 V 0.4 V II Inflection-point current OE: VI = VCCI or GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA Ioff Off-state current A port: VI or VO = 0 to 3.6 V 0 V 0 V to 5.5 V –1 1 –2 2 μA B port: VI or VO = 0 to 5.5 V 0 V to 3.6 V 0 V –1 1 –2 2 IOZ High- impedance- state output current A or B port: OE = GND 1.2 V to 3.6 V 1.65 V to 5.5 V –1 1 –2 2 μA ICCA VCCA supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 0.06 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5

3.6 V 0 V 2

0 V 5.5 V –2 ICCB VCCB supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 3.4 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 0 V 5.5 V 2 ICCA + ICCB Combined supply current VI = VCCI or GND IO = 0 1.2 V 1.65 V to 5.5 V 3.5 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 10 ICCZA High- impedance state, VCCA supply current VI = VCCI or GND IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 0.05 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 ICCZB High- impedance state, VCCB supply current VI = VCCI or GND IO = 0, OE = GND 1.2 V 1.65 V to 5.5 V 3.3 μA 1.4 V to 3.6 V 1.65 V to 5.5 V 5 Ci Input capacitance OE 1.2 V to 3.6 V 1.65 V to 5.5 V 3 4 pF Cio Input-to-output internal capacitance A port 1.2 V to 3.6 V 1.65 V to 5.5 V 5 6 pF B port 1.2 V to 3.6 V 1.65 V to 5.5 V 11 14 TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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5.7 Timing Requirements: VCCA = 1.2 V TA = 25°C, VCCA = 1.2 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Data rate 20 20 20 20 Mbps tw Pulse duration Data inputs 50 50 50 50 ns 5.8 Timing Requirements: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate 40 40 40 40 Mbps tw Pulse duration Data inputs 25 25 25 25 ns 5.9 Timing Requirements: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Data rate 60 60 60 60 Mbps tw Pulse duration Data inputs 17 17 17 17 ns 5.10 Timing Requirements: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX Data rate 100 100 100 Mbps tw Pulse duration Data inputs 10 10 10 ns 5.11 Timing Requirements: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX Data rate 100 100 Mbps tw Pulse duration Data inputs 10 10 ns www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TXB0104

5.12 Switching Characteristics: VCCA = 1.2 V (BQA/DYY) TA = 25°C, VCCA = 1.2 V PARAMETER TEST CONDITIONS VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay time ns B-to-A 7.4 6.4 6 5.8 ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time OE-to-A 392 392 392 392 ns OE-to-B 392 392 392 392 trA, tfA Input rise time, input fall time A-port rise and fall times 4.2 4.2 4.2 4.2 ns trB, tfB Input rise time, input fall time B-port rise and fall times 2.1 1.5 1.2 1.1 ns tSK(O) Skew (time), output Channel-to- channel skew 0.4 0.5 0.5 1.4 ns Maximum data rate 20 20 20 20 Mbps 5.13 Switching Characteristics: VCCA = 1.2 V (Other Packages) TA = 25°C, VCCA = 1.2 V PARAMETER TEST CONDITIONS VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX tpd Propagation delay time ns B-to-A 7.4 6.4 6 5.8 ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time OE-to-A 18 15 14 14 ns OE-to-B 20 17 16 16 trA, tfA Input rise time, input fall time A-port rise and fall times 4.2 4.2 4.2 4.2 ns trB, tfB Input rise time, input fall time B-port rise and fall times 2.1 1.5 1.2 1.1 ns tSK(O) Skew (time), output Channel-to- channel skew 0.4 0.5 0.5 1.4 ns Maximum data rate 20 20 20 20 Mbps TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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5.14 Switching Characteristics: VCCA = 1.5 V ± 0.1 V (BQA/DYY) over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay time ns ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time OE-to-A 278 390 236 305 236 305 236 305 ns OE-to-B 278 390 236 305 236 305 236 305 trA, tfA Input rise time, input fall time A-port rise and fall times trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 0.5 ns Maximum data rate 40 40 40 40 Mbps 5.15 Switching Characteristics: VCCA = 1.5 V ± 0.1 V (Other Packages) over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay time ns ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time ns trA, tfA Input rise time, input fall time A-port rise and fall times trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 0.5 ns Maximum data rate 40 40 40 40 Mbps www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TXB0104

5.16 Switching Characteristics: VCCA = 1.8 V ± 0.15 V (BQA/DYY) over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay time ns ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time OE-to-A 278 389 191 253 190 248 189 248 ns OE-to-B 278 389 191 253 190 248 189 248 trA, tfA Input rise time, input fall time A-port rise and fall times trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 0.5 ns Maximum data rate 60 60 60 60 Mbps 5.17 Switching Characteristics: VCCA = 1.8 V ± 0.15 V (Other Packages) over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay time ns ten Enable time OE-to-A 1 1 1 1 µs OE-to-B 1 1 1 1 tdis Disable time ns trA, tfA Input rise time, input fall time A-port rise and fall times trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 0.5 ns Maximum data rate 60 60 60 60 Mbps TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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5.18 Switching Characteristics: VCCA = 2.5 V ± 0.2 V (BQA/DYY) over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX MIN MAX tpd Propagatio n delay time ns ten Enable time OE-to-A 1 1 1 μs OE-to-B 1 1 1 tdis Disable time OE-to-A 190 252 137 184 133 169 ns OE-to-B 190 252 137 184 133 169 trA, tfA Input rise time, input fall time A-port rise and fall times 0.8 3 0.8 3 0.8 3 ns trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 ns Maximum data rate 100 100 100 Mbps 5.19 Switching Characteristics: VCCA = 2.5 V ± 0.2 V (Other Packages) over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX MIN MAX tpd Propagatio n delay time ns ten Enable time OE-to-A 1 1 1 μs OE-to-B 1 1 1 tdis Disable time ns trA, tfA Input rise time, input fall time A-port rise and fall times 0.8 3 0.8 3 0.8 3 ns trB, tfB Input rise time, input fall time B-port rise and fall times tSK(O) Skew (time), output Channel-to- channel skew 0.5 0.5 0.5 ns Maximum data rate 100 100 100 Mbps www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TXB0104

5.20 Switching Characteristics: VCCA = 3.3 V ± 0.3 V (BQA/DYY) over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX tpd Propagation delay time A-to-B 0.9 4.7 0.8 4 ns B-to-A 1 4.9 0.9 3.8 ten Enable time OE-to-A 1 1 μs OE-to-B 1 1 tdis Disable time OE-to-A 137 183 97.6 127 ns OE-to-B 137 183 97.6 127 trA, tfA Input rise time, input fall time A-port rise and fall times 0.7 2.5 0.7 2.5 ns trB, tfB Input rise time, input fall time B-port rise and fall times 0.5 2.1 0.4 2.7 ns tSK(O) Skew (time), output Channel-to-channel skew 0.5 0.5 ns Maximum data rate 100 100 Mbps 5.21 Switching Characteristics: VCCA = 3.3 V ± 0.3 V (Other Packages) over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX tpd Propagation delay time A-to-B 0.9 4.7 0.8 4 ns B-to-A 1 4.9 0.9 3.8 ten Enable time OE-to-A 1 1 μs OE-to-B 1 1 tdis Disable time OE-to-A 4.6 15.2 4.3 12.1 ns OE-to-B 3.8 16 3.4 13.2 trA, tfA Input rise time, input fall time A-port rise and fall times 0.7 2.5 0.7 2.5 ns trB, tfB Input rise time, input fall time B-port rise and fall times 0.5 2.1 0.4 2.7 ns tSK(O) Skew (time), output Channel-to-channel skew 0.5 0.5 ns Maximum data rate 100 100 Mbps TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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Product Folder Links: TXB0104

TA = 25°C PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = VCCA (outputs enabled) A-port input, B-port output 7.8 10 9 pF B-port input, A-port output 12 11 11 CpdB Power dissipation capacitance A-port input, B-port output 38.1 28 28 B-port input, A-port output 25.4 19 18 CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = GND (outputs disabled) A-port input, B-port output 0.01 0.01 0.01 pF B-port input, A-port output 0.01 0.01 0.01 CpdB Power dissipation capacitance A-port input, B-port output 0.01 0.01 0.01 B-port input, A-port output 0.01 0.01 0.01 5.23 Operating Characteristics: VCCA = 1.8 V to 3.3 V, VCCB = 1.8 V to 5 V TA = 25°C PARAMETER TEST CONDITIONS VCCA = 1.8 V, VCCB =1.8 V VCCA = 2.5 V, VCCB = 2.5 V VCCA = 2.5 V, VCCB = 5 V VCCA = 3.3 V, VCCB = 3.3 V to 5 V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = VCCA (outputs enabled) A-port input, B-port output 8 8 8 9 pF B-port input, A-port output 11 11 11 11 CpdB Power dissipation capacitance A-port input, B-port output 28 29 29 29 B-port input, A-port output 18 19 21 22 CpdA Power dissipation capacitance CL = 0 f = 10 MHz tr = tf = 1 ns OE = GND (outputs disabled) A-port input, B-port output 0.01 0.01 0.01 0.01 pF B-port input, A-port output 0.01 0.01 0.01 0.01 CpdB Power dissipation capacitance A-port input, B-port output 0.01 0.01 0.01 0.03 B-port input, A-port output 0.01 0.01 0.01 0.04 www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TXB0104

5.24 Typical Characteristics

VCCA (V) OE Pin Input Capacitance (pF) 0 0.5 1 1.5 2 2.5 3 3.5 4 D001 25qC (Room Temperature) 85qC VCCB= 3.3 V Figure 5-1. Input Capacitance for OE Pin (CI) vs Power Supply (VCCA) VCCA (V) A Port I/O Capacitance (pF) 0 0.5 1 1.5 2 2.5 3 3.5 4 D002 25qC (Room Temperature) 85qC VCCB= 3.3 V Figure 5-2. Capacitance for A port I/O Pins (CiO) vs Power Supply (VCCA) VCCB (V) B Port I/O Capacitance (pF) D003 25qC (Room Temperature) 85qC VCCA= 1.8 V Figure 5-3. Capacitance for B Port I/O Pins (CiO) vs Power Supply (VCCB) TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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6 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators that have the following characteristics:

• PRR 10 MHz
• ZO = 50 W
• dv/dt ≥ 1 V/ns Note All parameters and waveforms are not applicable to all devices. 15 pF From Output Under Test 1 M A. The outputs are measured one at a time, with one transition per measurement. Figure 6-1. Load Circuit For Maximum Data Rate: Pulse Duration, Propagation Delay Output Rise, And Fall Time Measurement From Output Under Test 15 pF 50 k Open 2 x VCCO 50 k A. The outputs are measured one at a time, with one transition per measurement. Figure 6-2. Load Circuit For Enable and Disable Time Measurement Table 6-1. Switch Position For Enable and Disable Time Measurement (See Figure 6-2 ) TEST S1 tPZL, tPLZ 2 × VCCO tPHZ, tPZH Open www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TXB0104

0.9 V CCO

0.1 V CCO

A. VCCI is the VCC associated with the input port. B. VCCO is theVCC associated with the output port. C. tPLH and tPHL are the same as tpd. D. The outputs are measured one at a time, with one transition per measurement. Figure 6-3. Voltage Waveforms Propagation Delay Times VCCI 0 V Input tw VCCI / 2 V CCI / 2 Figure 6-4. Voltage Waveforms Pulse Duration TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The TXB0104 device is a 4-bit, directionless voltage-level translator specifically designed for translating logic voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots) to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open-drain signal translation, please refer to TI’s TXS010X products.

7.2 Functional Block Diagram

www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TXB0104

7.3 Feature Description

7.3.1 Architecture

The TXB0104 device architecture (see Figure 7-1 ) does not require a direction-control signal to control the direction of data flow from A to B or from B to A. In a DC state, the output drivers of the device maintain a high or low, but are designed to be weak, so the output drivers can be overdriven by an external driver when data on the bus flows the opposite direction. The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V. A B VCCA VCCB One Shot One Shot One Shot One Shot Figure 7-1. Architecture of TXB0104 Device I/O Cell TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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Product Folder Links: TXB0104

7.3.2 Input Driver Requirements

Typical IIN vs VIN characteristics of the device are shown in Figure 7-2. For proper operation, the device driving the data I/Os of the TXB0104 device must have drive strength of at least ±2 mA. IIN VIN VT /4 k ±(VD ± VT)/4 k A. VT is the input threshold of the TXB0104 device, (typically VCC / 2). B. VD is the supply voltage of the external driver. Figure 7-2. Typical IIN vs VIN Curve

7.3.3 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths must be kept short enough such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the device output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects. www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TXB0104

7.3.4 Enable and Disable

The TXB0104 device has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the high-impedance (Hi-Z) state. The disable time (t dis) indicates the delay between when OE goes low and when the outputs acutally get disabled (Hi-Z). The enable time (t en) indicates the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.

7.3.5 Pullup or Pulldown Resistors on I/O Lines

The device is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0104 device have low dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0104 device. For the same reason, the TXB0104 device must not be used in applications such as I 2C or 1-Wire where an open-drain driver is connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx series of level translators.

7.4 Device Functional Modes

The device has two functional modes, enabled and disabled. To disable the device, set the OE input to low, which places all I/Os in a high impedance state. Setting the OE input to high will enable the device. TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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Product Folder Links: TXB0104

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TXB0104 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. It can only translate push-pull CMOS logic outputs. If for open-drain signal translation, please refer to TI TXS010X products. Any external pulldown or pullup resistors are recommended larger than 50 kΩ.

8.2 Typical Application

1.8 V System Controller TXB0104 3.3 V System 0.1 F 3.3 V 0.1 F 1.8 V VCCA VCCB OE GND Data Data

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1. And make sure the VCCA ≤ VCCB. Table 8-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUE Input voltage range 1.2 V to 3.6 V Output voltage range 1.65 V to 5.5 V www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TXB0104

8.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range - Use the supply voltage of the device that is driving the TXB0104 device to determine the input voltage range. For a valid logic high, the value must exceed the V IH of the input port. For a valid logic low, the value must be less than the VIL of the input port.
• Output voltage range - Use the supply voltage of the device that the device is driving to determine the output voltage range. - External pullup or pulldown resistors are not recommended. If mandatory, it is recommended that the value must be larger than 50 kΩ.
• An external pulldown or pullup resistor decreases the output V OH and V OL. Use the below equations to draft estimate the VOH and VOL as a result of an external pulldown and pullup resistor. VOH = VCCx × RPD / (RPD + 4.5 kΩ) VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ) Where
• VCCx is the output port supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor
• RPU is the value of the external pull up resistor
• 4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line.

8.2.3 Application Curves

Figure 8-1. Level-Translation of a 2.5-MHz Signal TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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Product Folder Links: TXB0104

9 Power Supply Recommendations

During operation, ensure that V CCA ≤ VCCB at all times. During power-up sequencing, V CCA ≥ VCCB does not damage the device, so any power supply can be ramped up first. The device has circuitry that disables all output ports when either V CC is switched off (V CCA/B = 0 V). The output-enable (OE) input circuit is designed so that it is supplied by V CCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until V CCA and VCCB are fully ramped and stable. The minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver.

10 Layout

10.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.

• Bypass capacitors must be used on power supplies, and must be placed as close as possible to the VCCA, VCCB pin and GND pin.
• Short trace-lengths must be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than the one-shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the source driver.

10.2 Layout Example

0.1 F 0.1 F To Controller To Controller To Controller To Controller Bypass Capacitor Bypass Capacitor TXB0104PWR VCCA VCCB NC GND NC OE To System To System To System To System LEGEND Polygonal Copper Pour VIA to Power Plane VIA to GND Plane (Inner Layer) Keep OE low until VCCA and VCCB are powered up www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TXB0104

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

BGA MICROSTAR JUNIOR™ is a trademark of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (October 2020) to Revision K (March 2025) Page Changes from Revision I (March 2018) to Revision J (October 2020) Page Changes from Revision H (January 2018) to Revision I (March 2018) Page Changes from Revision G (November 2014) to Revision H (January 2018) Page Changes from Revision F (May 2012) to Revision G (November 2014) Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TXB0104 SCES650K – APRIL 2006 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TXB0104

SCES650K – APRIL 2006 – REVISED MARCH 2025 www.ti.com

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www.ti.com 28-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TXB0104BQAR Active Production WQFN (BQA) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104BQAR.A Active Production WQFN (BQA) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104D Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104D.B Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DG4 Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DR.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104DYYR Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 TXB0104 TXB0104NMNR Active Production NFBGA (NMN) | 12 2500 | LARGE T&R Yes SNAGCU Level-2-260C-1 YEAR -40 to 85 2AQW TXB0104NMNR.B Active Production NFBGA (NMN) | 12 2500 | LARGE T&R Yes SNAGCU Level-2-260C-1 YEAR -40 to 85 2AQW TXB0104PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104PWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104PWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104PWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 YE04 TXB0104RGYR Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RGYR.A Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RGYR.B Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RGYRG4 Active Production VQFN (RGY) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 YE04 TXB0104RUTR Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR, 2KV) TXB0104RUTR.A Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR, 2KV) TXB0104RUTR.B Active Production UQFN (RUT) | 12 3000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 (2KR, 2KV) TXB0104YZTR Active Production DSBGA (YZT) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 2K TXB0104YZTR.B Active Production DSBGA (YZT) | 12 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 2K (1) Status: For more details on status, see our product life cycle. Addendum-Page 1

www.ti.com 28-Jul-2026 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TXB0104 :

• Automotive : TXB0104-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TXB0104DYYR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXB0104BQAR WQFN BQA 14 3000 210.0 185.0 35.0 TXB0104DR SOIC D 14 2500 353.0 353.0 32.0 TXB0104DYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 TXB0104NMNR NFBGA NMN 12 2500 210.0 185.0 35.0 TXB0104PWR TSSOP PW 14 2000 353.0 353.0 32.0 TXB0104RGYR VQFN RGY 14 3000 353.0 353.0 32.0 TXB0104RUTR UQFN RUT 12 3000 189.0 185.0 36.0 TXB0104YZTR DSBGA YZT 12 3000 182.0 182.0 20.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQA 14 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3, 0.5 mm pitch 4227145/A

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max height PLASTIC QUAD FLAT PACK-NO LEAD BQA0014A A 0.08 C

0.1 C A B

0.05 C B SYMM SYMM 2.6 2.4 3.1 2.9PIN 1 INDEX AREA 0.8 0.7 0.05 0.00 SEATING PLANE C 1.1 0.9 1.6 1.4 2X 0.5 8X 0.5 14X 0.3 0.2 14X 0.5 0.3 (0.2) TYP 7 8 141 PIN 1 ID (OPTIONAL)

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQA0014A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X (1) (1.5)2X (0.5) 8X (0.5) (2) 2X (0.5) 14X (0.25) 14X (0.6) (2.3) (2.8) (Ø0.2) VIA TYP (R0.05) TYP 7 8 (PREFERRED) SOLDER MASK DEFINED

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQA0014A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 88% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (0.95) (1.38) 8X (0.5) (2) 2X (0.5) 14X (0.25) 14X (0.6) (2.3) (2.8) (R0.05) TYP 7 8

www.ti.com PACKAGE OUTLINE C 12X 0.25 0.15 12X 0.6 0.4 1.6 10X 0.4

0.55 MAX

0.05 0.00 B 1.8 1.6 A 2.1 1.9 0.6 0.4 0.25 0.15 (0.15) (0.15) TYP 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C (OPTIONAL) PIN 1 ID

0.1 C B A

0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 6.800 OPTIONAL TERMINAL & PIN 1 ID PIN 1 ID

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

0.05 MAX

12X (0.2) (1.4) 8X (0.4) (1.7) 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE:30X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 12X (0.7) 12X (0.2) 8X (0.4) (1.7) (1.4) (R0.05) TYP 4220310/A 11/2016 UQFN - 0.55 mm max heightRUT0012A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 30X

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. NanoFree is a trademark of Texas Instruments. PACKAGE OUTLINE 4225768/A 03/2020 www.ti.com NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY NMN0012A A 0.08 C

0.15 C A B

0.05 C B SYMM SYMM BALL A1 CORNER

1 MAX

0.25 0.19 SEATING PLANE 2.6 2.4 2.1 1.9

1.5 TYP

(0.5 ) TYP (0.5 ) TYP

0.5 TYP

A B C 1 2 3 4 12X Ø 0.35 0.25 C

NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature number SNVA009 (www.ti.com/lit/snva009). EXAMPLE BOARD LAYOUT 4225768/A 03/2020 www.ti.com NFBGA - 1 mm max heightNMN0012A PLASTIC BALL GRID ARRAY SYMM SYMM LAND PATTERN EXAMPLE SCALE: 20X (0.5) TYP (0.5) TYP SOLDER MASK DETAILS NOT TO SCALE (PREFERRED) SOLDER MASK DEFINED (Ø 0.25) METAL EXPOSED METAL METAL UNDER SOLDER MASK (Ø 0.25) SOLDER MASK OPENING A B C 1 2 3 4 12X (Ø0.25)

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. EXAMPLE STENCIL DESIGN 4225768/A 03/2020 www.ti.com NFBGA - 1 mm max heightNMN0012A PLASTIC BALL GRID ARRAY SOLDER PASTE EXAMPLE BASED ON 0.100 mm THICK STENCIL SCALE: 20X SYMM SYMM (0.5) TYP (0.5) TYP A B C 1 2 3 4 12X ( 0.25) (R0.05) TYP

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGY 14 PLASTIC QUAD FLATPACK - NO LEAD3.5 x 3.5, 0.5 mm pitch 4231541/A

www.ti.com PACKAGE OUTLINE C 14X 0.30 0.18 14X 0.5 0.3 0.05 0.00 8X 0.5 2.05 0.1 2X 1.5 A 3.65 3.35 B 3.65 3.35 (0.2) TYP VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 PIN 1 INDEX AREA 0.08 SEATING PLANE 1 14 (OPTIONAL) PIN 1 ID 0.05 7 8 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (3.3) (3.3) 8X (0.5) 14X (0.6) 14X (0.24) ( 2.05) (0.775) (0.775) 2X (1.5) ( ) VIA TYP 0.2 (R ) TYP0.05 VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 SYMM1 14 SYMM LAND PATTERN EXAMPLE SCALE:20X 7 8 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.24) 14X (0.6) (3.3) (3.3) 8X (0.5) 4X ( 0.92) (0.56) (0.56) 2X (1.5) (R ) TYP0.05 VQFN - 1 mm max heightRGY0014A PLASTIC QUAD FLATPACK - NO LEAD 4219040/A 09/2015 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 1 14 7 8

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

D: Max = E: Max = 1.89 mm, Min = 1.39 mm, Min = 1.83 mm 1.33 mm

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