TX98-4

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Wireless Sense & Control Data Sheet Revision 1.0, 2010-04-23 TX 98-4 ASK Transmitter

81726 Munich, Germany

© 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet 3 Revision 1.0, 2010-04-23 Trademarks of Infineon Technologies AG A-GOLD™, BlueMoon™, COMNEO N™, CONVERGATE™, COSIC™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CONVERPATH™, CORECONTROL™ , DAVE™, DUALFALC™, DUSLIC™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, Econo PACK™, EconoPIM™, E- GOLD™, EiceDRIVER™, EUPEC™, ELIC™, EPIC™, FALC ™, FCOS™, FLEXISLIC™, GE MINAX™, GOLDMO S™, HITFET™, HybridPACK™, INCA™, ISAC™, ISOFACE™, Iso PACK™, IWORX™, M-GOLD™, MIPAQ™, ModSTACK™, MUSLIC™, my-d™, NovalithIC™, OCTALFALC™, OCTAT™, OmniTune™, OmniVia™, OptiMOS™, OPTIVERSE™, ORIGA™, PROFET™, PRO-SIL™, PrimePACK™, QUAD FALC™, RASIC™, ReverSave™, SatRIC™, SCEPTRE™, SCOUT™, S-GOLD™, Se nsoNor™, SEROCCO™, SICOFI™, SIEGET™, SINDRION™, SLIC™, SMARTi™, SmartLEWIS™, SMINT™, SOCR ATES™, TEMPFET™, thinQ!™, TrueNTRY™, TriCore™, TRENCHSTOP™, VINAX™, VI NETIC™, VIONTIC™, WildPass™, X-GOLD™, XMM™, X-PMU™, XPOSYS™, XWAY™. Other Trademarks AMBA™, ARM™, MULTI- ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetoot h™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Mi crosoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorpor ated. IEC™ of Commission Electrot echnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim In tegrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO. Om niVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Micros ystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Ta iyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISH A TA. UNIX™ of X/Open Co mpany Limited. VERILOG™, PALLADIUM™ of Cadence Design Syst ems, Inc. VLYNQ™ of Texas In struments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, I NC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2009-10-19 TX 98-4 ASK Transmitter Revision History: 2010-04-23, Revision 1.0 Previous Revision: none Page Subjects (major cha nges since last revision)

Data Sheet 4 Revision 1.0, 2010-04-23 Table of Contents

Data Sheet 5 Revision 1.0, 2010-04-23

1 Product Description

1.1 Overview

The TX 98-4 is a single chip ASK tran smitter for operation in the frequency band from 433 to 435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features are a power down mode and a divided clock output.

1.2 Features

• Frequency range 433 ... 435 MHz
• Low supply current
• Power down mode
• High efficiency power amplifier (typically 10 dBm)
• Fully integrated frequency synthesizer
• VCO without external components
• ASK modulation
• Voltage supply range 2.1... 4 V
• Low external component count
• Divided clock output for µC
• Temperature range -40... +85°C
• Crystal oscillator 13.56 MHz

1.3 Application

TX 98-4 is suitable for any kind of remote control system, especially for low data rate wireless applications where low current consumption is important and where the li ne-of-sight limitation is dr iving the infra-red to RF replacement. Main applications:

• Home Automation - Lighting Control - Curtain, Roller Blind Control - Air Condition Control
• Garage Door Openers
• Wireless Toys
• Remote Keyless Entry Systems TX 98-4 is defined and qualified to meet low-cost consumer product requirements.

Data Sheet 6 Revision 1.0, 2010-04-23

1.4 Ordering Information

Type Ordering Code Package 1) 1) Available on tape and reel TX 98-4 SP000743714 PG-TSSOP-10

Data Sheet 6 Revision 1.0, 2010-04-23

2 Functional Description

2.1 Pin Configuration

Figure 1 IC Pin Configuration

2.2 Pin Definition and Functions

Table 2 Pin Definition and Functions - Overview Pin No. Symbol Function 1 CLKOUT Clock Driver Output (847.5 kHz)

2 VS Voltage Supply

3 GND Ground

4 N.U.1 Not used 1 5 COSC Crystal Oscillator Input (13.56 MHz)

6 ASKDTA Amplitude Shift Keying Data Input

7 N.U.2 Not used 2

8 PAGND Power Am plifier Ground

9 PAOUT Power Amplifie r Output (434 MHz)

10 PDWN Power Down Mode Control

N.U.2 ASKDTA CLKOUT VS GND N.U.1 COSC TX 98-4

Data Sheet 7 Revision 1.0, 2010-04-23 Table 3 Pin Definition and Function Ball No. Name Pin Type Buffer Type Function 1C L K O U T Clock output to supply an external device An external pull-up resistor has to be added in accordance to the driving requirements of the external device. The clock frequency is 847.5 kHz. 2V S This pin is the positive supply of the transmitter electronics An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 3) as short as possible. 3G N D General ground connection 4N . U . 1 This pin must be left open 5C O S C This pin is connected to the reference oscillator circuit The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin.

6 ASKDTA Digital amplitude modulation can be

imparted to the Power Amplifier through this pin A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier. A logic low (ASKDTA < 0.5 V) disables the Power Amplifier. 7N . U . 2 This pin must be left open 300 Ω VS 6 kΩ 100 μA VS VS +1.2 V 90 kΩ 2.3 pF 30 μA 60 kΩ +1.1 V VS

Data Sheet 8 Revision 1.0, 2010-04-23

8 PAGND Ground connection of the power amplifier

The RF ground return path of the power amplifier output PAOUT (pin 9) has to be concentrated to this pin.

9 PAOUT RF output pin of the transmitter

A DC path to the positive supply VS has to be supplied by the antenna matching network.

10 PDWN Disable pin for the complete transmitter

A logic low (PDWN < 0.7 V) turns off all transmitter functions. A logic high (PDWN > 1.5 V) gives access to all transmitter functions. Table 3 Pin Definition and Function (cont’d) Ball No. Name Pin Type Buffer Type Function VS 150 kΩ 5 kΩ 250 kΩ "ON" 40 μA ∗ (ASKDT)

Data Sheet 9 Revision 1.0, 2010-04-23

2.3 Functional Block Diagram

Figure 2 Functional Block Diagram Crystal

13.56 MHz

:16 PFD :64 VCO :2 Power AMP LF Power Supply 7 10 2 N.U.2 Power Down Control Power Supply VS Power Amplifier Output Power Amplifier Ground On Cl oc k Output AS K Data Input Ground N. U. 1

Data Sheet 10 Revision 1.0, 2010-04-23

2.4 Functional Block Description

2.4.1 PLL Synthesizer

The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diode s is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 868 MHz. The oscillator signal is fed both, to the synthesizer divider chain and (v ia 1:2 divider) to the power amplifie r. The overall division ratio of the asynchronous divider chain is 64. The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip.

2.4.2 Crystal Oscillator

The crystal oscillator operates at 13.56 MHz. The crystal frequency is divided by 16. The resulting 84 7.5 kHz are available at the clock output CLKOUT (pin1) to drive the clock input of a micro controller.

2.4.3 Power Amplifier

The VCO frequency is divided by 2 and fed to the Power Amplifier. The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6). The Power Amplifier has an Open Collector output at PAOUT (pin 9) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 9) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 8) in order to reduce the amount of coupling to the other circuits.

2.4.4 Power Modes

The IC provides three power modes, the POWER DO WN MODE, the PLL ENABLE MODE and the TRANSMIT MODE.

2.4.4.1 Power Down Mode

In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.3 nA @ 3 V and 25°C. This current doubles every 8°C. The values for higher temperatures is typically 14 nA @ 85°C. Table 4 ASKDTA - Power Amplifier ASKDTA (pin6) Power Amplifier Low1) 1) Low: Voltage at pin < 0.5 V OFF Open2), High3) 2) Open: Pin open 3) High: Voltage at pin > 1.5 V ON

Data Sheet 11 Revision 1.0, 2010-04-23

2.4.4.2 PLL Enable Mode

In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is less than 1 msec when the specified crystal is used. The current consumption is typically 4mA.

2.4.4.3 Transmit Mode

In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 14.2 mA when using a proper transforming network at PAOUT, see Figure 3.

2.4.4.4 Power mode control

The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin10). When the bias circuitry is powered up, the pin ASKDTA is pulled up internally. Forcing the voltage at the pins low overrides the internally set state. The principle schematic of the power mode control circuitry is shown in Figure 3 Figure 3 Power mode control circuitry Table 5 provides a listing of how to get into the different power modes Table 5 Power Modes PDWN ASKDTA MODE Low 1) Low: Voltage at pin < 0.7 V (PDWN), Voltage at pin < 0.5 V (ASKDTA) Low, Open POWER DOWN Open2) 2) Open: Pin open Low POWER DOWN High3) 3) High: Voltage at pin > 1.5 V Low PLL ENABLE Open High TRANSMIT High Open, High TRANSMIT Bias Source ASKDTA PDWN PAOUT IC On Bias Voltage PA On 120 kΩ PLL 434 MHz

Data Sheet 12 Revision 1.0, 2010-04-23 Other combinations of the control pins PDWN and ASKDTA are not recommended. To avoid spurious radiation it is strongly recommended to switch not di rectly from PDWN-mode to TRANSMIT- mode, but to PLL-ENABLE-mode first!

2.4.5 Recommended Timing Di agrams for ASK-Modulation

min. 1 msec. t t DATA Open, High Low Modes: Transmit PLL EnablePower Down

Data Sheet 13 Revision 1.0, 2010-04-23

3 Application

3.1 Application Hints on the Crystal Oscillator

The crystal oscillator achieves a turn on time less than 1 msec when the specified crystal is used. To achieve this, a NIC oscillator type is implemented in the TX 98-4. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv. Figure 5 Application Hints (1) Example The inductance L at 13.56 MHz is about 4.6 μH. Assuming a crystal frequency of 13.56 MHz and a crystal load capacitance of CL = 12 pF, the value of Cv is calculated to ~ 8,6 pF. (2)

3.2 Design Hints on the Clock Output (CLKOUT)

The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the micro controller). RL can be calculated to: (3) CL Crystal load capacitance for nominal frequency ω Angular frequency L Inductance of the crystal oscillator IC -R L f, CL Cv LCL Cv LCL Cv CLDfCLKOUTRL *8*

Data Sheet 14 Revision 1.0, 2010-04-23 Note: To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen. Even harmonics of the signal at CLKOUT can interact with the crystal oscillator input COSC preventing the start- up of oscillation. Care must be taken in layout by sufficient separation of the signal lines to ensure sufficiently small coupling.

3.3 Application Hints on the Power-Amplifier

The power amplifier operates in a high efficient class C mo de. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of Θ<<π. A frequency selective network at the amplifier output passes the fundamental frequenc y component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collect or of the power amplifier can be generalized by the equivalent circuit of Figure 6. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter. Figure 6 Equivalent power amplifier tank circuit The optimum load at the collector of the power amplifie r for “critical” operation under idealized conditions at resonance is: (4) The theoretical value of RLC for an RF output power of Po= 10 dBm (10 mW) is: (5) “Critical” operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high degree of efficiency under “critical” operating conditions can be explained by the low power losses at the transistor. During the conducting phase of the transistor, its collector voltage is very small. This way the power loss of the transistor, equal to iC*uCE is minimized. This is particularly true for small current flow angles of Θ<<π. In practice the RF-saturation voltage of the PA transistor and other parasitic’s reduce the “critical” RLC. Table 6 Clock Output fCLKOUT=847.5 kHz CL[pF] RL[kOhm] 52 7 10 12 20 6.8 VS RLCL O S LC P VR *2 Ω== 45001.0*2 LCR

Data Sheet 15 Revision 1.0, 2010-04-23 The output power Po is reduced by operating in an “overcritical” mode characterized by RL > RLC. The power efficiency (and the bandwidth) increase when operating at a slightly higher RL, as shown in Figure 7. The collector efficiency E is defined as: (6) The diagram of Figure 7 was measured directly at the PA-output at V S = 3 V. Losses in the matching circuitry decrease the output power by about 1.5 dB. As can be seen from the diagram, 250 Ω is the optimum impedance for operation at 3 V. For an approximation of R OPT and POUT at other supply voltages those two formulas can be used: (7) and (8) Figure 7 Output power P o (mW) and collector efficiency E vs. load resistor RL The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of “overcritical” operation. The depth of this dip will increase with higher values of RL. CS O IV PE = SOPT VR ~ OPTOUT RP ~ 0 100 200 300 400 500 RL [Ohm] Pout [mW] 10*Ec

Data Sheet 16 Revision 1.0, 2010-04-23

4 Reference

4.1 Electrical Data

4.1.1 Absolute Maximum Ratings

Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irrevisible damage to the integrated circuit. Note: All voltages referred to ground (pins) unless stated otherwise. Pins 3 and 8 are grounded.

4.2 Operating Ratings

Within the operational range the IC operates as described in the circuit description. Table 7 Absolute Maximum Ratings, Tamb = -40°C … +85 °C Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Junction Temperature T J -40 +125 °C Storage Temperature T s -40 +150 °C Thermal Resistance R thJA 220 K/W Supply voltage V S -0.3 +4.0 V Voltage at any pin excluding pin 9 V pins -0.3 V S + 0.3 V Voltage at pin 9 V pin9 -0.3 2 * V S V No ESD-Diode to V S ESD integrity, all pins V ESD -1 +1 kV JEDEC Standard JESD22-A114-B ESD integrity, all pins excluding pin VESD -2.5 +2.5 kV JEDEC Standard JESD22-A114-B Table 8 Operating Ratings Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply voltage V S 2.1 4.0 V Ambient temperature T A -40 85 °C

Data Sheet 17 Revision 1.0, 2010-04-23

4.3 AC/DC Characteristics

AC/DC characteristics involve the spread of values guar anteed within the specified supply voltage and ambient temperature. Typical characteristics are the median of the production. The device para meters are either verified by design and/or characterization or by production test.

4.3.1 AC/DC Characteristic at 3 V, 25°C

Table 9 Supply Voltage VS=3V, Ambient temperature Tamb=25°C Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Current consumption Power Down mode I S PDWN 0.3 100 nA V (Pins 10, 6 and 7) < 0.2 V PLL Enable mode I S PLL_EN 45 . 5 m A Transmit mode 434 MHz I S TRANSM 14.2 18 mA Output frequency Output frequency f OUT 427 434.5 442 MHz f OUT = 32 * fCOSC Clock Driver Output (Pin 1) Output current (High) I CLKOUT 5 μAV CLKOUT = VS Saturation Voltage (Low)1) 1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA VSATL 0.56 V I CLKOUT = 1 mA Crystal Oscillator Input (Pin 5) Load capacitance C COSCmax 5p F Serial Resistance of the crystal 100 Ω f = 13.56 MHz Input inductance of the COSC pin 4.6 μH f = 13.56 MHz ASK Modulation Data Input (Pin 6) ASK Transmit disabled V ASKDTA 00 . 5 V ASK Transmit enabled V ASKDTA 1.5 VS V Input bias current ASKDTA I ASKDTA 30 μAV ASKDTA = VS Input bias current ASKDTA I ASKDTA -20 μAV ASKDTA = 0 V ASK data rate f ASKDTA 20 kHz Power Amplifier Output (Pin 9) Output Power 2) at

434 MHz transformed to 50 Ohm

2) Power amplifier in overcritical C-operation. Matching circuitr y as used in the 50 Ohm-Output Test board at the specified frequency. Tolerances of the passive elements not taken into account. POUT434 71 0 1 3 d B m Power Down Mode Control (Pin 10) Power Down mode V PDWN 00 . 7 V V ASKDTA < 0.2 V PLL Enable mode V PDWN 1.5 VS V V ASKDTA < 0.5 V Transmit mode V PDWN 1.5 VS V V ASKDTA > 1.5 V Input bias current PDWN I PDWN 30 μAV PDWN = VS

Data Sheet 18 Revision 1.0, 2010-04-23

5 Package Outlines

1. You can find all of our packages, sorts of packing an d others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 2. SMD = Surface Mounted Devic 0.09 ±0.13 0.42 -0.1 +0.15 +0.08-0.05 0.125 6 max.H A0.1 4.9 M0.25 A B C 3±0.1 CBA0.08 M0.22±0.05 0.15 max. ±0.10.85 1.1 max. A C B 0.5 Index Marking

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