TX5416PGE

TMS320VC5416_17 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 98

Technical content

Datasheet sections

date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS095P March 1999 Revised October 2008

www.ti.com NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data sheet revision history highlights the technical changes made to the SPRS095O device-specific data sheet to make it an SPRS095P revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following corrections. ADDITIONS/CHANGES/DELETIONS Table 2-2 Signal Descriptions: Updated

DESCRIPTION

www.ti.com 4.1 Documentation Support 4.2 Device and Development-Support Tool Nomenclature Electrical Specifications 5.1 Absolute Maximum Ratings 5.2 Recommended Operating Conditions 5.3 Electrical Characteristics 5.3.1 Test Loading 5.3.2 Timing Parameter Symbology 5.3.3 Internal Oscillator With External Crystal 5.4 Clock Options 5.4.1 Divide-By-Two and Divide-By-Four Clock Options 5.4.2 Multiply-By-N Clock Option (PLL Enabled) 5.5 Memory and Parallel I/O Interface Timing 5.5.1 Memory Read 5.5.2 Memory Write 5.5.3 I/O Read 5.5.4 I/O Write 5.5.5 Ready Timing for Externally Generated Wait States 5.5.6 HOLD and HOLDA Timings 5.5.7 Reset, BIO Interrupt, and MP/ MC Timings 5.5.8 Instruction Acquisition IAQ and Interrupt Acknowledge IACK Timings 5.5.9 External Flag (XF) and TOUT Timings 5.5.10 Multichannel Buffered Serial Port (McBSP) Timing 5.5.10.1 McBSP Transmit and Receive Timings 5.5.10.2 McBSP General-Purpose I/O Timing 5.5.10.3 McBSP as SPI Master or Slave Timing 5.5.11 Host-Port Interface Timing 5.5.11.1 HPI8 Mode 5.5.11.2 HPI16 Mode Mechanical Data 6.1 Package Thermal Resistance Characteristics

Contents

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 List of Figures 2-1 144-Ball GGU MicroStar BGA (Bottom View) 2-2 144-Pin PGE Low-Profile Quad Flatpack (Top View) 3-1 TMS320VC5416 Functional Block Diagram 3-2 Program and Data Memory Map 3-3 Extended Program Memory Map 3-4 Process Mode Status Register 3-5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 3-6 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 3-7 Bank-Switching Control Register BSCR)[MMR Address 0029h] 3-8 Host-Port Interface Nonmulltiplexed Mode 3-9 HPI Memory Map 3-10 Multichannel Control Register (MCR1) 3-11 Multichannel Control Register (MCR2) 3-12 Pin Control Register (PCR) 3-13 Nonconsecutive Memory Read and I/O Read Bus Sequence 3-14 Consecutive Memory Read Bus Sequence reads) 3-15 Memory Write and I/O Write Bus Sequence 3-16 DMA Transfer Mode Control Register (DMMCRn) 3-17 On-Chip DMA Memory Map for Program Space (DLAXS and SLAXS 3-18 On-Chip DMA Memory Map for Data and IO Space (DLAXS and SLAXS 3-19 DMPREC Register 3-20 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] 3-21 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] 3-22 Device ID Register (CSIDR) [MMR Address 003Eh] 3-23 IFR and IMR Registers 5-1 Tester Pin Electronics 5-2 Internal Divide-By-Two Clock Option With External Crystal 5-3 External Divide-By-Two Clock Timing 5-4 Multiply-By-One Clock Timing 5-5 Nonconsecutive Mode Memory Reads 5-6 Consecutive Mode Memory Reads 5-7 Memory Write MSTRB 5-8 Parallel I/O Port Read IOSTRB 5-9 Parallel I/O Port Write IOSTRB 5-10 Memory Read With Externally Generated Wait States 5-11 Memory Write With Externally Generated Wait States 5-12 I/O Read With Externally Generated Wait States 5-13 I/O Write With Externally Generated Wait States 5-14 HOLD and HOLDA Timings (HM List of Figures

www.ti.com 5-15 Reset and BIO Timings 5-16 Interrupt Timing 5-17 MP/ MC Timing 5-18 Instruction Acquisition IAQ and Interrupt Acknowledge IACK Timings 5-19 External Flag (XF) Timing 5-20 TOUT Timing 5-21 McBSP Receive Timings 5-22 McBSP Transmit Timings 5-23 McBSP General-Purpose I/O Timings 5-24 McBSP Timing as SPI Master or Slave: CLKSTP 10b, CLKXP 5-25 McBSP Timing as SPI Master or Slave: CLKSTP 11b, CLKXP 5-26 McBSP Timing as SPI Master or Slave: CLKSTP 10b, CLKXP 5-27 McBSP Timing as SPI Master or Slave: CLKSTP 11b, CLKXP 5-28 Using HDS to Control Accesses HCS Always Low) 5-29 Using HCS to Control Accesses 5-30 HINT Timing 5-31 GPIOx Timings 5-32 Nonmultiplexed Read Timings 5-33 Nonmultiplexed Write Timings 5-34 HRDY Relative to CLKOUT List of Figures Submit Documentation Feedback

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 List of Tables 2-1 Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package) 2-2 Signal Descriptions 3-1 Standard On-Chip ROM Layout 3-2 Processor Mode Status (PMST) Register Bit Fields 3-3 Software Wait-State Register (SWWSR) Bit Fields 3-4 Software Wait-State Control Register (SWCR) Bit Fields 3-5 Bank-Switching Control Register (BSCR) Fields 3-6 Bus Holder Control Bits 3-7 Sample Rate Input Clock Selection 3-8 Clock Mode Settings at Reset 3-9 DMD Section of the DMMCRn Register 3-10 DMA Reload Register Selection 3-11 DMA Interrupts 3-12 DMA Synchronization Events 3-13 DMA Channel Interrupt Selection 3-14 Device ID Register (CSIDR) Bits 3-15 CPU Memory-Mapped Registers 3-16 Peripheral Memory-Mapped Registers for Each DSP Subsystem 3-17 McBSP Control Registers and Subaddresses 3-18 DMA Subbank Addressed Registers 3-19 Interrupt Locations and Priorities 5-1 Input Clock Frequency Characteristics 5-2 Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options 5-3 Divide-By-2 and Divide-By-4 Clock Options Timing Requirements 5-4 Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics 5-5 Multiply-By-N Clock Option Timing Requirements 5-6 Multiply-By-N Clock Option Switching Characteristics 5-7 Memory Read Timing Requirements 5-8 Memory Read Switching Characteristics 5-9 Memory Write Switching Characteristics 5-10 I/O Read Timing Requirements 5-11 I/O Read Switching Characteristics 5-12 I/O Write Switching Characteristics 5-13 Ready Timing Requirements for Externally Generated Wait States 5-14 Ready Switching Characteristics for Externally Generated Wait States 5-15 HOLD and HOLDA Timing Requirements 5-16 HOLD and HOLDA Switching Characteristics 5-17 Reset, BIO Interrupt, and MP/ MC Timing Requirements 5-18 Instruction Acquisition IAQ and Interrupt Acknowledge IACK Switching Characteristics List of Tables

www.ti.com 5-19 External Flag (XF) and TOUT Switching Characteristics 5-20 McBSP Transmit and Receive Timing Requirements 5-21 McBSP Transmit and Receive Switching Characteristics 5-22 McBSP General-Purpose I/O Timing Requirements 5-23 McBSP General-Purpose I/O Switching Characteristics 5-24 McBSP as SPI Master or Slave Timing Requirements (CLKSTP 10b, CLKXP 5-25 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 10b, CLKXP 5-26 McBSP as SPI Master or Slave Timing Requirements (CLKSTP 11b, CLKXP 5-27 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 11b, CLKXP 5-28 McBSP as SPI Master or Slave Timing Requirements (CLKSTP 10b, CLKXP 5-29 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 10b, CLKXP 5-30 McBSP as SPI Master or Slave Timing Requirements (CLKSTP 11b, CLKXP 5-31 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 11b, CLKXP 5-32 HPI8 Mode Timing Requirements 5-33 HPI8 Mode Switching Characteristics 5-34 HPI16 Mode Timing Requirements 5-35 HPI16 Mode Switching Characteristics 6-1 Thermal Resistance Characteristics List of Tables Submit Documentation Feedback

Features

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Reads Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Arithmetic Instructions With Parallel Store and Program Memory Bus Parallel Load 40-Bit Arithmetic Logic Unit (ALU) Including a Conditional Store Instructions 40-Bit Barrel Shifter and Two Independent Fast Return From Interrupt 40-Bit Accumulators On-Chip Peripherals 17- 17-Bit Parallel Multiplier Coupled to a Software-Programmable Wait-State 40-Bit Dedicated Adder for Non-Pipelined Generator and Programmable Single-Cycle Multiply/Accumulate (MAC) Bank-Switching Operation On-Chip Programmable Phase-Locked Compare, Select, and Store Unit (CSSU) for the Loop (PLL) Clock Generator With External Add/Compare Selection of the Viterbi Operator Clock Source One 16-Bit Timer Exponent Encoder to Compute an Exponent Six-Channel Direct Memory Access (DMA) Value of a 40-Bit Accumulator Value in a Controller Single Cycle Three Multichannel Buffered Serial Ports Two Address Generators With Eight Auxiliary (McBSPs) Registers and Two Auxiliary Register 8/16-Bit Enhanced Parallel Host-Port Arithmetic Units (ARAUs) Interface (HPI8/16) Data Bus With a Bus Holder Feature Power Consumption Control With IDLE1, Extended Addressing Mode for 16-Bit IDLE2, and IDLE3 Instructions With Maximum Addressable External Program Power-Down Modes Space CLKOUT Off Control to Disable CLKOUT 128K 16-Bit On-Chip RAM Composed of: On-Chip Scan-Based Emulation Logic, IEEE Eight Blocks of 16-Bit On-Chip Std 1149.1 (JTAG) Boundary Scan Logic (1) Dual-Access Program/Data RAM 144-Pin Ball Grid Array (BGA)(GGU Suffix) Eight Blocks of 16-Bit On-Chip Single-Access Program RAM 144-Pin Low-Profile Quad Flatpack (LQFP)(PGE Suffix) 16K 16-Bit On-Chip ROM Configured for Program Memory 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS) Enhanced External Parallel Interface (XIO2) 8.33-ns Single-Cycle Fixed-Point Instruction Single-Instruction-Repeat and Block-Repeat Execution Time (120 MIPS) Operations for Program Code 3.3-V I/O Supply Voltage (160 and 120 MIPS) Block-Memory-Move Instructions for Better Program and Data Management 1.6-V Core Supply Voltage (160 MIPS) Instructions With a 32-Bit Long Word Operand 1.5-V Core Supply Voltage (120 MIPS) (1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Instructions With Two- or Three-Operand Boundary Scan Architecture TMS320C54x, TMS320 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 1999 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

2.1 2.2 Pin Assignments 2.2.1 Terminal Assignments for the GGU Package A B D C E F H J L M K N G 123456781012 1113 9 TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com This section describes the main TMS320VC5416, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. NOTE This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307). The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the device unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls. Figure 2-1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2-1 to locate signal names and ball grid numbers. Figure 2-2 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package. Figure 2-1. 144-Ball GGU MicroStar BGA (Bottom View) Introduction Submit Documentation Feedback

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 2-1 lists each signal name and BGA ball number for the 144-pin TMS320VC5416GGU package. Table 2-2 lists each terminal name, terminal function, and operating modes for the TMS320VC5416. In Table 2-1 DV DD is the power supply for the I/O pins while CV DD is the power supply for the core CPU. Table 2-1. Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package) SIGNAL SIGNAL SIGNAL SIGNAL BGA BALL BGA BALL BGA BALL BGA BALL QUADRANT QUADRANT QUADRANT QUADRANT CV SS BFSX1 N13 CV SS A19 A13 A22 BDX1 M13 BCLKR1 A20 A12 CV SS DV DD L12 HCNTL0 CV SS B11 DV DD DV SS L13 DV SS DV DD A11 A10 CLKMD1 K10 BCLKR0 D10 HD7 CLKMD2 K11 BCLKR2 C10 A11 CLKMD3 K12 BFSR0 B10 A12 HPI16 K13 BFSR2 A10 A13 HD2 J10 BDR0 D10 A14 TOUT J11 HCNTL1 D11 A15 EMU0 J12 BDR2 D12 CV DD EMU1/ OFF J13 BCLKX0 HD4 HAS TDO H10 BCLKX2 D13 DV SS TDI H11 CV SS D14 CV SS TRST H12 HINT D15 CV DD TCK H13 CV DD HD5 HCS TMS G12 BFSX0 CV DD HR/ W CV SS G13 BFSX2 CV SS READY CV DD G11 HRDY HDS1 PS HPIENA G10 DV DD DV SS DS DV SS F13 DV SS HDS2 IS CLKOUT F12 HD0 DV DD W HD3 F11 BDX0 MSTRB F10 BDX2 IOSTRB X2/CLKIN E13 IACK MSC RS E12 HBIL XF E11 NMI HD6 HOLDA E10 INT0 IAQ D13 INT1 N10 HOLD D12 INT2 M10 BIO D11 INT3 L10 MP/ MC C13 CV DD N11 DV DD A16 C12 HD1 M11 CV SS DV SS C11 CV SS L11 CV DD BDR1 A17 B13 BCLKX1 N12 A21 BFSR1 A18 B12 DV SS M12 DV SS Submit Documentation Feedback Introduction

2.2.2 Pin Assignments for the PGE Package CV HDS1 A18 A17 DV SS A16 RS X2/CLKIN HD3 CLKOUT DV SS HPIENA CV DD CV SS TMS TCK TRST TDI TDO EMU1/OFF EMU0 TOUT HD2 HPI16 CLKMD3 CLKMD2 CLKMD1 DV SS DV DD BDX1 BFSX1 CV SS A22 CV SS DV DD A10 HD7 A11 A12 A13 A14 A15 CV DD HAS DV SS CV SS CV DD HCS HR/W READY PS DS IS R/W MSTRB IOSTRB MSC XF HOLDA IAQ HOLD BIO MP/MC DV DD CV SS BDR1 BFSR1 SSDV144 A21 CV 143 142 141 A8140 A7139 A6138 A5137 A4136 HD6135 A3134 A2133 A1132 A0131 DV130 129 128 127 CV126 125 HD5124 D15123 D14122 D13121 HD4120 D12119 D11118 117 D9116 D8115 D7114 D6113 112 108 107 106 105 104 103 102 101 100 SSCV BCLKR1 HCNTL0 SS BCLKR0 BCLKR2 BFSR0 BFSR2 BDR0 HCNTL1 BDR2 BCLKX0 BCLKX2 SS DD SS HD0 BDX0 BDX2 IACK HBIL NMI INT0 INT1 INT2 INT3 DD HD1 SS HRDY HINT 111 CV 110 A19109 BCLKX1 SSDV D10 BFSX2 SS A20 DV DDCV HDS2 SSDV DV CV DV DV CV CV DD DD DD DD SS BFSX0 TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The TMS320VC5416PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-2 DV DD is the power supply for the I/O pins while CV DD is the power supply for the core CPU. V SS is the ground for both the I/O pins and the core CPU. Figure 2-2. 144-Pin PGE Low-Profile Quad Flatpack (Top View) Introduction Submit Documentation Feedback

2.2.3 Signal Descriptions TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 2-2 lists each signal, function, and operating mode(s) grouped by function. Table 2-2. Signal Descriptions TERMINAL I/O (1) (MSB), I/O/Z (2) (3) Parallel address bus A22 [most significant bit (MSB)] through [least significant bit (LSB)]. The sixteen LSB A21, A20, lines, to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16 A19, A18, to A22, address external program space memory. A22-A0 is placed in the high-impedance state in the hold A17, A16, mode. A22-A0 also goes into the high-impedance state when OFF is low.A17-A0 are inputs in HPI16 mode. A15, A14, These pins can be used to address internal memory via the host-port interface (HPI) when the HPI16 pin is high. A13, A12, These pins also have Schmitt trigger inputs.The address bus has a bus holder feature that eliminates passive A11, A10, A9, components and the power dissipation associated with them. The bus holder keeps the address bus at the A8, A7, A6, previous logic level when the bus goes into a high-impedance state. A5, A4, A3, A2, A1, (LSB) D15 (MSB), I/O/Z (2) (3) Parallel data bus D15 (MSB) through (LSB). D15-D0 is multiplexed to transfer data between the core CPU D14, D13, and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15-D0 is D12, D11, placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15-D0 also D10, D9, D8, goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs.The data bus D7, D6, D5, has a bus holder feature that eliminates passive components and the power dissipation associated with them. D4, D3, D2, The bus holder keeps the data bus at the previous logic level when the bus goes into the high-impedance state. D1, (LSB) The bus holders on the data bus can be enabled/disabled under software control. INITIALIZATION, INTERRUPT AND RESET OPERATIONS Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the IACK O/Z interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state when OFF is low. INT0 (2) INT1 (2) External user interrupt inputs. INT0 INT3 are maskable and are prioritized by the interrupt mask register (IMR) I INT2 (2) and the interrupt mode bit. INT0 INT3 can be polled and reset by way of the interrupt flag register (IFR). INT3 (2) Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. NMI (2) I When NMI is activated, the processor traps to the appropriate vector location. Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to RS (2) I 0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits. Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high MP/ MC I during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/ MC bit of the processor mode status (PMST) register can override the mode that is selected at reset. MULTIPROCESSING SIGNALS Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the BIO (2) I conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC instruction, and all other instructions sample BIO during the read phase of the pipeline. External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor XF O/Z configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset. MEMORY CONTROL SIGNALS Data, program, and I/O space select signals. DS PS and IS are always high unless driven low for DS communicating to a particular external space. Active period corresponds to valid address information. DS PS PS O/Z and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance IS state when OFF is low. Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to MSTRB O/Z data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. (1) I Input, O Output, Z High-impedance, S Supply (2) These pins have Schmitt trigger inputs. (3) This pin has an internal bus holder controlled by way of the BSCR register. Submit Documentation Feedback Introduction

www.ti.com Table 2-2. Signal Descriptions (continued) TERMINAL I/O (1) ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the READY I processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states. Read/write signal. W indicates transfer direction during communication to an external device. W is normally W O/Z in the read mode (high), unless it is asserted low when the DSP performs a write operation. W is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low. I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O IOSTRB O/Z device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low. Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by HOLD I the device, these lines go into the high-impedance state. Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing them to be available to the external HOLDA O/Z circuitry. HOLDA also goes into the high-impedance state when OFF is low. Figure 2-2 This pin is driven high during reset. Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive MSC O/Z high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low. Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address IAQ O/Z bus and goes into the high-impedance state when OFF is low. TIMER SIGNALS Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by or as CLKOUT O/Z configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the machine-cycle rate divided by Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes CLKMD1 (2) such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled to determine CLKMD2 (2) I the desired clock generation mode while RS is low. Following reset, the clock generation mode can be CLKMD3 (2) reconfigured by writing to the internal clock mode register in software. Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is X2/CLKIN (2) I revision-dependent, see Section 3.10 for additional information.) Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, should be left O unconnected. does not go into the high-impedance state when OFF is low. (This is revision-dependent, see Section 3.10 for additional information.) Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT TOUT O/Z cycle wide. TOUT also goes into the high-impedance state when OFF is low. MULTICHANNEL BUFFERED SERIAL PORT (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT (McBSP #1), AND MULTICHANNEL BUFFERED SERIAL PORT (McBSP #2) SIGNALS BCLKR0 (2) Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following BCLKR1 (2) I/O/Z reset. BCLKR serves as the serial shift clock for the buffered serial port receiver. BCLKR2 (2) BDR0, BDR1, I Serial data receive input BDR2 BFSR0, Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured BFSR1, I/O/Z as an input following reset. The BFSR pulse initiates the receive data process over BDR. BFSR2 BCLKX0 (2) Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as BCLKX1 (2) I/O/Z an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state BCLKX2 (2) when OFF goes low. BDX0, BDX1, Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is O/Z BDX2 asserted, or when OFF is low. BFSX0, Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over BFSX1, I/O/Z BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX BFSX2 goes into the high-impedance state when OFF is low. Introduction Submit Documentation Feedback

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 2-2. Signal Descriptions (continued) TERMINAL I/O (1) bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the HD0- high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to I/O/Z HD7 (2) (3) reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the device, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs. HCNTL0 (4) Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs I HCNTL1 (4) have internal pullups that are only enabled when HPIENA These pins are not used when HPI16 Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup HBIL (4) I resistor that is only enabled when HPIENA This pin is not used when HPI16 Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input HCS (2) (4) I has an internal pullup resistor that is only enabled when HPIENA HDS1 (2) (4) Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe I HDS2 (2) (4) inputs have internal pullup resistors that are only enabled when HPIENA Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA HAS (2) (4) I register. HAS input has an internal pullup resistor that is only enabled when HPIENA Read/write. HR/ W controls the direction of the HPI transfer. HR/ W has an internal pullup resistor that is only HR/ W (4) I enabled when HPIENA Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host HRDY O/Z when the HPI is ready for the next transfer. This pin is driven high during reset. Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT HINT O/Z goes into the high-impedance state when OFF is low. This pin is not used when HPI16 HPI module select. HPIENA must be tied to DV DD to have HPI selected. If HPIENA is left open or connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus HPIENA (5) I has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled when RS goes high and is ignored until RS goes low again. This pin should never be changed while reset is high. HPI16 mode selection. This pin must be tied to DVDD to enable HPI16 mode. The pin has an internal pulldown HPI16 (5) I resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled. SUPPLY PINS CV SS S Ground. Dedicated ground for the core CPU CV DD S DD Dedicated power supply for the core CPU DV SS S Ground. Dedicated ground for I/O pins DV DD S DD Dedicated power supply for I/O pins TEST PINS IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction TCK (2) (4) I register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register TDI (4) I (instruction or data) on a rising edge of TCK. IEEE standard 1149.1 test data output. The (instruction or data) are shifted out TDO O/Z of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low. IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into TMS (4) I the TAP controller on the rising edge of TCK. IEEE standard 1149.1 test reset. TRST when high, gives the IEEE standard 1149.1 scan system control of the TRST (5) (6) I operations of the device. If TRST is driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. (4) This pin has an internal pullup resistor. (5) This pin has an internal pulldown resistor. (6) Although this pin includes an internal pulldown resistor, a 470- Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the V IL and V IH specifications are met. Submit Documentation Feedback Introduction

www.ti.com Table 2-2. Signal Descriptions (continued) TERMINAL I/O (1) pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST EMU0 (7) I/O/Z is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. Emulator pin/disable all outputs. When TRST is driven high, EMU1/ OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/ OFF is configured as OFF The EMU1/ OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for EMU1/ OFF (7) I/O/Z multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST low, EMU0 high EMU1/ OFF low (7) This pin must be pulled up with a 4.7-k Ω resistor to ensure the device is operable in functional mode or emulation mode. Introduction Submit Documentation Feedback

P, C, D, E Buses and Control Signals XIO 16HPI 54X cLEAD

16 HPI

3.1 Memory 3.1.1 Data Memory TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The following functional overview is based on the block diagram in Figure 3-1 Figure 3-1. TMS320VC5416 Functional Block Diagram The device provides both on-chip ROM and RAM memories to aid in system performance and integration. The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: Higher performance because no wait states are required Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU) Lower cost than external memory Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. Submit Documentation Feedback Functional Overview

3.1.2 Program Memory 3.1.3 Extended Program Memory 3.2 On-Chip ROM With Bootloader TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows: Higher performance because no wait states are required Lower cost than external memory Lower power than external memory The advantage of operating from off-chip memory is the ability to access a larger address space. The device uses a paged extended memory scheme in program space to allow access of up to 8192K of program memory. In order to implement this scheme, the device includes several C548/549/5410: Twenty-three address lines, instead of sixteen An extra memory-mapped register, the XPC Six extra instructions for addressing extended program space Program memory in the device is organized into 128 pages that are each 64K in length. The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to The device a 16K-word 16-bit on-chip maskable ROM that can only be mapped into program memory space. Customers can arrange to have the ROM of the device programmed with application. A bootloader is available in the standard on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/ MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard devices provide different ways to download the code to accommodate various system requirements: Parallel from 8-bit or 16-bit-wide EPROM Parallel from I/O space, 8-bit or 16-bit mode Serial boot from serial ports, 8-bit or 16-bit mode Host-port interface boot Warm boot Functional Overview Submit Documentation Feedback

3.3 On-Chip RAM 3.4 On-Chip Memory Security TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The standard on-chip ROM layout is shown in Table 3-1 Table 3-1. Standard On-Chip ROM Layout ADDRESS RANGE µ -Law expansion table FD00h-FDFFh A-Law expansion table FE00h-FEFFh Sine look-up table FF00h-FF7Fh Reserved (1) FF80h-FFFFh Interrupt vector table (1) In the ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h-FF7Fh in program space. The device contains 64K-word 16-bit of on-chip dual-access RAM (DARAM) and 64K-word 16-bit of on-chip single-access RAM (SARAM). The DARAM is composed of eight blocks of words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. The other four blocks of DARAM are located in the address range 18000h-1FFFFh in program space. The DARAM located in the address range 18000h-1FFFFh in program space can be mapped into data space by setting the DROM bit to one. The SARAM is composed of eight blocks of words each. Each of these eight blocks is a single-access memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data word is written to another SARAM block. The SARAM is located in the address range 28000h-2FFFFh, and 38000h-3FFFFh in program space. The device has a maskable option to protect the memories. When the RAM/ROM security option is selected, the following restrictions apply: Only the on-chip ROM originating instructions can read the ROM; on-chip RAM and external RAM originating instruction can not read data from ROM: instead 0FFFFh is read. Code can still branch to ROM from on-chip RAM or external program memory. The instructions, even by instructions fetched from external memory. To protect the internal RAM, the user must never branch to external memory. The security feature completely disables the scan-based emulation capability of the 54x to prevent the use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG boundary scan test capability. The device is internally forced into microcomputer mode at reset (MP/ MC bit forced to zero), preventing the ROM from being disabled by the external MP/ MC pin. The status of the MP/ MC bit in the PMST register can be changed after reset by the user application. HPI writes have no restriction, but HPI reads are restricted to the 4000h 5FFFh address range. Submit Documentation Feedback Functional Overview

3.5 Memory Map Reserved (OVLY = 1) External (OVLY = 0) Page 0 ProgramHex Data On-Chip DARAM0−3 (OVLY = 1) External (OVLY = 0) MP/MC = 0 (Microcomputer Mode) MP/MC = 1 (Microprocessor Mode) 0000 007F 0080 FFFF Interrupts (External) FF80 Memory-Mapped Registers On-Chip DARAM0−3 (32K x 16-bit) On-Chip DARAM4−7 (DROM=1) or External (DROM=0) 0080 FFFF FF7F 0060 007F 0000 Hex External Scratch-Pad RAM 005F On-Chip ROM (4K x 16-bit) Interrupts (On-Chip) 7FFF 8000 Page 0 ProgramHex 0000 007F 0080 FFFF Reserved (OVLY = 1) External (OVLY = 0) FF80 FF7F External 7FFF 8000 ReservedFF00 FEFF C000 BFFF 8000 7FFF On-Chip DARAM0−3 (OVLY = 1) External (OVLY = 0) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com If the ROM- only security option is selected the following restrictions apply: Only the on-chip ROM originating instructions can read the ROM; on-chip RAM and external RAM originating instruction cannot read data from ROM: instead 0FFFFh is read. Code can still branch to ROM from on-chip RAM or external program memory. The instructions, even by instructions fetched from external memory. To protect the internal RAM the user must never branch to external memory. The security feature completely disables the scan-based emulation capability of the 54x to prevent the use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG boundary scan test capability. The device can be started in either microcomputer mode or microprocessor mode at reset (depends on the MP/ MC pin). HPI read and writes have no restriction. The program and data memory map is shown in Figure 3-2 Address ranges for on-chip DARAM in data memory are: DARAM0: 0080h-1FFFh DARAM1: 2000h-3FFFh DARAM2: 4000h-5FFFh DARAM3: 6000h-7FFFh DARAM4: 8000h-9FFFh DARAM5: A000h-BFFFh DARAM6: C000h-DFFFh DARAM7: E000h-FFFFh Figure 3-2. Program and Data Memory Map Functional Overview Submit Documentation Feedback

XPC=1 On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) On-Chip DARAM4−7 (MP/MC=0) External (MP/MC=1) Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) 020000 02FFFF Page 2 XPC=2 Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) 030000 03FFFF Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) External 040000 04FFFF Hex Program On-Chip DARAM0−3 (OVLY=1) External (OVLY=0) 7F0000 7FFFFF Page 3 XPC=3 Page 4 XPC=4 Page 127 XPC=7Fh External 7F7FFF 7F8000 047FFF037FFF027FFF017FFF 018000 028000 038000 048000On-Chip SARAM0−3 (MP/MC=0) External (MP/MC=1) On-Chip SARAM4−7 (MP/MC=0) External (MP/MC=1) 3.5.1 Relocatable Interrupt Vector Table TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The extended program memory map is shown in Figure 3-3 Address ranges for on-chip DARAM in data memory are: DARAM4: 018000h-019FFFh DARAM5: 01A000h-01BFFFh DARAM6: 01C000h-01DFFFh DARAM7: 01E000h-01FFFFh Address ranges for on-chip SARAM in program memory are: SARAM0: 028000h-029FFFh SARAM1: 02A000h-02BFFFh SARAM2: 02C000h-02DFFFh SARAM3: 02E000h-02FFFFh SARAM4: 038000h-039FFFh SARAM5: 03A000h-03BFFFh SARAM6: 03C000h-03DFFFh SARAM7: 03E000h-03FFFFh Figure 3-3. Extended Program Memory Map The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead. At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE The hardware reset RS vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. Submit Documentation Feedback Functional Overview

www.ti.com IPTR R/W-1FF IPTR MP/ MC OVLY AVIS DROM CLKOFF SMUL SST MP/ MC pin R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R Read, W Write, n value present after reset Figure 3-4. Process Mode Status Register Table 3-2. Processor Mode Status (PMST) Register Bit Fields BIT RESET FUNCTION VALUE NO. NAME Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, 15-7 IPTR 1FFh these bits are all set to the reset vector always resides at address FF80h in program memory space. The RESET instruction does not affect this field. Microprocessor/microcomputer mode. MP/ MC enables/disables the on-chip ROM to be addressable in program memory space. MP/ MC The on-chip ROM is enabled and addressable. MP/ MC MP/ MC The on-chip ROM is not available. MP/ MC pin MP/ MC is set to the value corresponding to the logic level on the MP/ MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software. RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are: OVLY OVLY The on-chip RAM is addressable in data space but not in program space. OVLY The on-chip RAM is mapped into program space and data space. Data page (addresses to 7Fh), however, is not mapped into program space. Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins. AVIS The external address lines do not change with the internal program address. Control AVIS and data lines are not affected and the address bus is driven with the last address on the bus. AVIS This mode allows the internal program address to appear at the pins of the device so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside on on-chip memory. DROM enables on-chip DARAM4-7 to be mapped into data space. The DROM bit values are: DROM DROM The on-chip DARAM4-7 is not mapped into data space. DROM The on-chip DARAM4-7 is mapped into data space. CLOCKOUT off. When the CLKOFF bit is the output of CLKOUT is disabled and remains at a high CLKOFF level. Saturation on multiplication. When SMUL saturation of a multiplication result occurs before SMUL N/A performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM and FRCT Saturation on store. When SST saturation of the data from the accumulator is enabled before SST N/A storing in memory. The saturation is performed after the shift operation. Functional Overview Submit Documentation Feedback

3.6 On-Chip Peripherals 3.6.1 Software-Programmable Wait-State Generator TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The device has the following peripherals: Software-programmable wait-state generator Programmable bank-switching A host-port interface (HPI8/16) Three multichannel buffered serial ports (McBSPs) A hardware timer A clock generator with a multiple phase-locked loop (PLL) Enhanced external parallel interface (XIO2) A DMA controller (DMA) The software wait-state generator of the device can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption. The software wait-state register (SWWSR) controls the operation of the wait-state generator. The LSBs of the SWWSR specify the number of wait states to to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of or for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3 XPA I/O DATA DATA R/W-0 R/W-111 R/W-111 DATA PROGRAM PROGRAM R/W-111 R/W-111 R/W-111 LEGEND: R Read, W Write, n value present after reset Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] Submit Documentation Feedback Functional Overview

www.ti.com Table 3-3. Software Wait-State Register (SWWSR) Bit Fields BIT RESET FUNCTION VALUE NO. NAME Extended program address control bit. XPA is used in conjunction with the program space fields XPA (bits through to select the address range for program space wait states. I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses 14-12 I/O 111 within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of or for the base number of wait states. Upper data space. The field value (0-7) corresponds to the base number of wait states for external 11-9 Data 111 data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of or for the base number of wait states. Lower data space. The field value (0-7) corresponds to the base number of wait states for external 8-6 Data 111 data space accesses within addresses 0000-7FFFh. The SWSM bit of the SWCR defines a multiplication factor of or for the base number of wait states. Upper program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses: XPA xx8000 xxFFFFh 5-3 Program 111 XPA 400000h 7FFFFFh The SWSM bit of the SWCR defines a multiplication factor of or for the base number of wait states. Program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses: XPA xx0000 xx7FFFh 2-0 Program 111 XPA 000000 3FFFFFh. The SWSM bit of the SWCR defines a multiplication factor of or for the base number of wait states. The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3-6 and described in Table 3-4 Reserved R/W-0 Reserved SWSM R/W-0 R/W-0 LEGEND: R Read, W Write, n value present after reset Figure 3-6. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] Table 3-4. Software Wait-State Control Register (SWCR) Bit Fields PIN RESET FUNCTION VALUE NO. NAME 15-1 Reserved These bits are reserved and are unaffected by writes. Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of or SWSM SWSM wait-state base values are unchanged (multiplied by SWSM wait-state base values are multiplied by for a maximum of wait states Functional Overview Submit Documentation Feedback

3.6.2 Programmable Bank-Switching TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Programmable bank-switching logic allows the device to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space. Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped ataddress 0029h. The bit fields of the BSCR are shown in Figure 3-7 and are described in Table 3-5 CONSEC DIVFCT IACKOFF Reserved R/W-1 R/W-11 R/W-1 R Reserved HBH BH Reserved R R/W-0 R/W-0 R LEGEND: R Read, W Write, n value present after reset Figure 3-7. Bank-Switching Control Register BSCR)[MMR Address 0029h] Table 3-5. Bank-Switching Control Register (BSCR) Fields RESET BIT NAME FUNCTION VALUE Consecutive bank-switching Specifies the bank-switching mode. CONSEC Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is CONSEC desired for continuous memory reads (i.e., no starting and trailing cycles between read cycles). (1) CONSEC Consecutive bank switches on external memory reads. Each read cycle consists of cycles: starting cycle, read cycle, and trailing cycle. CLKOUT output divide factor The CLKOUT output is driven by an on-chip source having a frequency equal to 1/(DIVFCT+1) of the DSP clock. DIVFCT 00: CLKOUT is not divided. 14-13 DIVFCT DIVFCT 01: CLKOUT is divided by from the DSP clock. DIVFCT 10: CLKOUT is divided by from the DSP clock. DIVFCT 11: CLKOUT is divided by from the DSP clock (default value following reset). IACK signal output off Controls the output of the IACK signal. IACKOFF is set to at reset. IACKOFF IACKOFF The IACK signal output off function is disabled. IACKOFF The IACK signal output off function is enabled. 11-3 Rsvd Reserved HPI bus holder. Controls the HPI bus holder. HBH is cleared to at reset. HBH The bus holder is disabled except when HPI16 HBH HBH The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous logic level. Bus holder. Controls the bus holder. BH is cleared to at reset. BH The bus holder is disabled. BH BH The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic level. Rsvd Reserved (1) For additional information, see Section 3.11 of this document. Submit Documentation Feedback Functional Overview

3.6.3 Bus Holders 3.7 Parallel I/O Ports TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The device has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches CONSEC 0), if the MSB of the address used for the current read does not match that contained in this internal register, the MSTRB (memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs. In non-consecutive bank switches CONSEC 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document. The bank-switching mechanism automatically inserts one extra cycle in the following cases: A memory read followed by another memory read from a different memory bank. A program-memory read followed by a data-memory read. A data-memory read followed by a program-memory read. A program-memory read followed by another program-memory read from a different page. The device has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[17-0]), data bus (D[15-0]), and the HPI data bus (HD[7-0]). Bus keeper enabling/disabling is described in Table 3-6 Table 3-6. Bus Holder Control Bits HPI16 PIN BH HBH D[15-0] A[17-0] HD[7-0] OFF OFF OFF OFF OFF ON ON OFF OFF ON OFF ON OFF OFF ON OFF ON ON ON OFF ON ON ON ON The device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The device can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits. Functional Overview Submit Documentation Feedback

3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier TMS320C54x DSPs (542, 545, 548, and 549). The HPI can be used to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external devices in program/data/IO spaces), the HPI can be configured as an HPI16 to interface to a 16-bit host. This configuration can be accomplished by connecting the HPI16 pin to logic When the HPI16 pin is connected to a logic "0", the HPI is configured as an HPI8. The HPI8 is an 8-bit parallel port for interprocessor communication. The include: Standard features: Sequential transfers (with autoincrement) or random-access transfers Host interrupt and C54x interrupt capability Multiple data strobes and control pins for interface flexibility The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers the HPI address register (HPIA), the HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the device. Enhanced features: Access to entire on-chip RAM through DMA bus Capability to continue transferring during emulation stop The HPI16 is an enhanced 16-bit version of the TMS320C54x DSP 8-bit host-port interface (HPI8). The HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Some of the include: 16-bit bidirectional data bus Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts Only nonmultiplexed address/data modes are supported 18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal extended address pages) HRDY signal to hold off host accesses due to DMA latency The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP. NOTE Only the nonmultiplexed mode is supported when the HPI is configured as a HPI16. The HPI functions as a slave and enables the host processor to access the on-chip memory. A major enhancement to the HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are always synchronized to the device clock, an active input clock (CLKIN) is required for HPI accesses during IDLE states, and host accesses are not allowed while the device reset pin is asserted. Submit Documentation Feedback Functional Overview

3.7.2 HPI Nonmultiplexed Mode HPID[15:0] HAS HDS1 , HDS2, HCS DMA Internal Memory PPD[15:0]DATA[15:0] Address[17:0] R/W Data Strobes READY HPI16 HRDY 54xx CPU VCC HCNTL0 HCNTL1 HR/W HINT HBIL HOST TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The host initiates the access with the strobe signals HDS1 HDS2 HCS and controls the direction of the access with the HR/ W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. Figure 3-8 shows a block diagram of the HPI16 in nonmultiplexed mode. Figure 3-9 shows the HPI memory map. Figure 3-8. Host-Port Interface Nonmulltiplexed Mode Functional Overview Submit Documentation Feedback

Address (Hex) Reserved Reserved Scratch-Pad RAM DARAM0 − DARAM3

001 FFFF

002 FFFF

003 FFFF

DARAM4 − DARAM7 SARAM4 − SARAM7 SARAM0 − SARAM3 TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Figure 3-9. HPI Memory Map Submit Documentation Feedback Functional Overview

3.8 Multichannel Buffered Serial Ports (McBSPs) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial-port interface found on other 54x devices. Like their predecessors, the McBSPs provide: Full-duplex communication Double-buffer data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit In addition, the McBSPs have the following capabilities: Direct interface to: T1/E1 framers MVIP switching compatible and ST-BUS compliant devices IOM-2 compliant devices AC97-compliant devices IIS-compliant devices Serial peripheral interface Multichannel transmit and receive of up to 128 channels A wide selection of data sizes, including 12, 16, 20, 24, or bits µ -law and A-law companding Programmable polarity for both frame synchronization and data clocks Programmable internal clock and frame generation The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and BCLKR, connect the control and data paths to external devices. The implemented pins can be programmed as general-purpose I/O pins if they are not used for serial communication. The data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for transmit and the data receive (BDR) pin for receive. The CPU or DMA reads the received data from the data receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then copied to DRR, which can be read by the CPU or DMA. This allows internal data movement and external data communications simultaneously. Control information in the form of clocking and frame synchronization is communicated by way of BCLKX, BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers accessible via the internal peripheral bus. The control block consists of internal clock generation, frame synchronization signal generation, and their control, and multichannel selection. This control block sends notification of important events to the CPU and DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT. The on-chip companding hardware allows compression and expansion of data in either µ -law or A-law format. When companding is used, transmitted data is encoded according to the specified companding law and received data is decoded to complement format. The sample rate generator provides the McBSP with several means of selecting clocking and framing for both the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently. Functional Overview Submit Documentation Feedback

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. All 128 channels in a bit stream consisting of a maximum of 128 channels can be enabled. Reserved XMCME XPBBLK R R/W R/W XPBBLK XPABLK XCBLK Reserved XMCM R/W R/W R R R/W LEGEND: R Read, W Write, n value present after reset Figure 3-10. Multichannel Control Register (MCR1) Reserved RMCME RPBBLK R R/W R/W RPBBLK RPABLK RCBLK Reserved RMCM R/W R/W R R R/W LEGEND: R Read, W Write, n value present after reset Figure 3-11. Multichannel Control Register (MCR2) The McBSP has two working modes: In the first mode, when (R/X)MCME it is comparable with the McBSPs used in the 5410 where the normal 32-channel selection is enabled (default). In the second mode, when (R/X)MCME it has 128-channel selection capability. Multichannel control register Bit (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME twelve new registers ((R/X)CERC (R/X)CERH) are used to enable the 128-channel selection. The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave. Although the BCLKS pin is not available on the device PGE and GGU packages, the device is capable of synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to accommodate this option. Reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM R/W R/W R/W R/W R/W R/W R/W SCLKME CLKS STAT DX STAT DR STAT FSXP FSRP CLKXP CLKRP R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R Read, W Write, n value present after reset Figure 3-12. Pin Control Register (PCR) Submit Documentation Feedback Functional Overview

3.9 Hardware Timer 3.10 Clock Generator TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The selection of sample rate input clock is made by the combination of the CLKSM (bit in SRGR2) bit value and the SCLKME bit value as shown in Table 3-7 Table 3-7. Sample Rate Input Clock Selection SCLKME CLKSM SAMPLE RATE CLOCK MODE Reserved (CLKS pin unavailable) CPU clock BCLKR BCLKX When the SCLKME bit is cleared to the CLKSM bit is used, as before, to select either the CPU clock or the CLKS pin (not bonded out on the device package) as the sample rate input clock. Setting the SCLKME bit to enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample rate input clock. When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is automatically disabled. For example, with SCLKME and CLKSM the BCLKR pin is configured as the input of the sample rate generator. Both the transmitter and receiver circuits can be synchronized to the sample rate generator output by setting the CLKXM and CLKRM bits of the pin configuration register (PCR) to Note that the sample rate generator output will only be driven on the BCLKX pin since the BCLKR output buffer is automatically disabled. The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating frequency, see Section 5.5.10 The device a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CLKOUT cycle. Each time the counter decrements to a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits. The clock generator provides clocks to the device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the device. Functional Overview Submit Documentation Feedback

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 This clock generator allows system designers to select the clock source. The sources that drive the clock generator are: A crystal resonator circuit. The crystal resonator circuit is connected across the and X2/CLKIN pins of the device to enable the internal oscillator. An external clock. The external clock source is directly connected to the X2/CLKIN pin, and is left unconnected. NOTE The crystal oscillator function is not supported by all die revisions of the device. See the TMS320VC5416 Digital Signal Processor Silicon Errata (literature number SPRZ172) to verify which die revisions support this functionality. The software-programmable PLL a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes: PLL mode. The input clock (X2/CLKIN) is multiplied by of possible ratios. DIV (divider) mode. The input clock is divided by or Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation. The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference Set, Volume CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options are shown in Table 3-8 Table 3-8. Clock Mode Settings at Reset CLKMD1 CLKMD2 CLKMD3 CLKMD RESET VALUE CLOCK MODE (1) 0000h (PLL disabled) 9007h PLL x 4007h PLL x 1007h PLL x F007h PLL x 0000h (PLL disabled) F000h (PLL disabled) Reserved (Bypass mode) (1) The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software. Submit Documentation Feedback Functional Overview

3.11 Enhanced External Parallel Interface (XIO2) READ A[22:0] D[15:0] CLKOUT R/W MSTRB or IOSTRB PS /DS/IS Leading Cycle Read Cycle Trailing Cycle TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The device external interface has been redesigned to include several improvements, including: simplification of the bus sequence, more immunity to bus contention when transitioning between read and write operations, the ability for external memory access to the DMA controller, and optimization of the power-down modes. The bus sequence on the device still maintains all of the same interface signals as on previous 54x devices, but the signal sequence has been simplified. Most external accesses now require cycles composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide additional immunity against bus contention when switching between read operations and write operations. To maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous 54x devices is available. Figure 3-13 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or single memory reads in consecutive mode. The accesses shown in Figure 3-13 always require CLKOUT cycles to complete. Figure 3-13. Nonconsecutive Memory Read and I/O Read Bus Sequence Functional Overview Submit Documentation Feedback

A[22:0] D[15:0] R/W MSTRB PS /DS READ Read Cycle Trailing Cycle Read Cycle Leading Cycle Read Cycle TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Figure 3-14 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in Figure 3-14 require CLKOUT cycles to complete, where n is the number of consecutive reads performed. Figure 3-14. Consecutive Memory Read Bus Sequence reads) Submit Documentation Feedback Functional Overview

A[22:0] D[15:0] R/W PS /DS/IS Leading Cycle Write Cycle MSTRB or IOSTRB Trailing Cycle TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 3-15 shows the bus sequence for all memory writes and I/O writes. The accesses shown in Figure 3-15 always require CLKOUT cycles to complete. Figure 3-15. Memory Write and I/O Write Bus Sequence The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more information on DMA capability, see the DMA sections that follow. The enhanced interface improves the low-power performance already present on the TMS320C5000 DSP platform by switching off the internal clocks to the interface when it is not being used. This power-saving feature is automatic, requires no software setup, and causes no latency in the operation of the interface. Additional (see Section 3.6.2 the ability to program up to wait states through software (see Section 3.6.1 and the ability to divide down CLKOUT by a factor of or Dividing down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3-5 Functional Overview Submit Documentation Feedback

3.12 DMA Controller 3.12.1 3.12.2 DMA External Access TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The device direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA allows movements of data to and from internal program/data memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU operation. The DMA has six independent programmable channels, allowing six different contexts for DMA operation. The DMA has the following features: The DMA operates independently of the CPU. The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. The DMA has higher priority than the CPU for both internal and external accesses. Each channel has independently programmable priorities. Each channel's source and destination address registers can have configurable indexes through memory on each read and write transfer, respectively. The address may remain constant, be post-incremented, be post-decremented, or be adjusted by a programmable value. Each read or write internal transfer may be initialized by selected events. On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU. The DMA can perform double-word internal transfers 32-bit transfer of two 16-bit words). The DMA supports external accesses to data, I/O, and extended program memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be used for external memory accesses. The DMA external accesses require a minimum of cycles for external writes and a minimum of cycles for external reads assuming the XIO02 is in consecutive mode CONSEC 1), wait state is set to two, and CLKOUT is not divided (DIVFCT 00). The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes precedence over XIO requests. Only two channels are available for external accesses. (One for external reads and one for external writes.) Single-word (16-bit) transfers are supported for external accesses. The DMA does not support transfers from the peripherals to external memory. The DMA does not support transfers from external memory to the peripherals. The DMA does not support external-to-external accesses. The DMA does not support synchronized external accesses. AUTOINIT DINM IMOD CTMOD SLAXS SIND DMS DLAXS DIND DMD LEGEND: R Read, W Write, n value present after reset Figure 3-16. DMA Transfer Mode Control Register (DMMCRn) Submit Documentation Feedback Functional Overview

www.ti.com These new bit fields were created to allow the user to define the space-select for the DMA (internal/external). The functions of the DLAXS and SLAXS bits are as follows: DLAXS(DMMCRn[5]) Destination No external access (default internal) External access SLAXS(DMMCRn[11]) Source No external access (default internal) External access Table 3-9 lists the DMD bit values and their corresponding destination space. Table 3-9. DMD Section of the DMMCRn Register DMD Destination Space PS DS I/O Reserved For the CPU external access, software can configure the memory cells to reside inside or outside the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the address generation logic generates an address outside its bounds, the device automatically generates an external access. Functional Overview Submit Documentation Feedback

3.12.3 DMA Memory Maps ProgramHex SLAXS = 0 DLAXS = 0 0000 005F 0060 3FFF 4000 FFFF 0x7FFF 0x8000 Hex 0x0000 7FFF 8000 On-Chip DARAM3 8K W ords 0xFFFF Program Page 0 Page 2 − 3 5FFF 6000 On-Chip DARAM2 8K W ords On-Chip DARAM1 8K W ords On-Chip DARAM0 8K W ords 1FFF 2000 Hex xx0000 xxFFFF Page 4 − 127 On-Chip SARAM 0/4 8K W ords On-Chip SARAM 1/5 8K W ords On-Chip SARAM 2/6 8K W ords On-Chip SARAM 3/7 8K W ords 0x9FFF 0xA000 0xBFFF 0xC000 0xDFFF 0xE000 Program Reserved Reserved Reserved Reserved ProgramHex 010000 017FFF Page 1 Reserved 018000 01FFFF On-Chip DARAM 4 8K W ords On-Chip DARAM 5 8K W ords On-Chip DARAM 6 8K W ords On-Chip DARAM 7 8K W ords 019FFF 01A000 01BFFF 01C000 01DFFF 01E000 TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The DMA memory maps, shown in Figure 3-17 and Figure 3-18 allows the DMA transfer to be unaffected by the status of the MP/ MC DROM, and OVLY bits. Figure 3-17. On-Chip DMA Memory Map for Program Space (DLAXS and SLAXS Submit Documentation Feedback Functional Overview

(See Breakout) I/O SpaceData SpaceData Space (0000 - 005F) Reserved Reserved Reserved Reserved Reserved Reserved 3.12.4 DMA Priority Level 3.12.5 DMA Source/Destination Address Modification TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 3-18. On-Chip DMA Memory Map for Data and IO Space (DLAXS and SLAXS Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA channels that are assigned to the same priority level are handled in a round-robin manner. The DMA provides flexible address-indexing modes for easy implementation of data management schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and can be post-incremented, post-decremented, or post-incremented with a specified index offset. Functional Overview Submit Documentation Feedback

3.12.6 DMA in Autoinitialization Mode 3.12.7 DMA Transfer Counting 3.12.8 DMA Transfer in Doubleword Mode TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR, and DMGFR). Autoinitialization allows: Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the completion of the current block transfers, but with the reload registers, it can reinitialize these values for the next block transfer any time after the current block transfer begins. Repetitive operation:The CPU does not preload the reload register with new values for each block transfer but only loads them on the first block transfer. The DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has its own DMA reload register set. For example, the DMA reload register set for channel has DMGSA0, DMGDA0, DMGCR0, and DMGFR0 while DMA channel has DMGSA1, DMGDA1, DMGCR1, and DMGFR1, etc. To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown in Figure 3-19 FREE AUTOIX DPRC[5:0] IOSEL DE[5:0] LEGEND: R Read, W Write, n value present after reset Figure 3-19. DMPREC Register Table 3-10. DMA Reload Register Selection AUTOIX DMA RELOAD REGISTER USAGE IN AUTO INIT MODE (default) All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0 Each DMA channel uses its own set of reload registers The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields that represent the number of frames and the number of elements per frame to be transferred. Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to A frame count of (default value) means the block transfer contains a single frame. Element count. This 16-bit value defines the number of elements per frame. This counter is decremented after the read transfer of each element. The maximum number of elements per frame is 65536 (DMCTRn 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded with the DMA global count reload register (DMGCR). Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated following each transfer. In this mode, each 32-bit word is considered to be one element. Submit Documentation Feedback Functional Overview

3.12.9 DMA Channel Index Registers 3.12.10 DMA Interrupts 3.12.11 DMA Controller Synchronization Events TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA transfer mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is the last in the current frame. The normal adjustment value (element index) is contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1. The element index and the frame index affect address adjustment as follows: Element index: For all except the last transfer in the frame, the element index determines the amount to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by the SIND/DIND bits. Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers. The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available modes are shown in Table 3-11 Table 3-11. DMA Interrupts MODE DINM IMOD INTERRUPT ABU (non-decrement) At full buffer only ABU (non-decrement) At half buffer and full buffer Multiframe At block transfer complete (DMCTRn DMSEFCn[7:0] Multiframe At end of frame and end of block (DMCTRn Either X No interrupt generated Either X No interrupt generated The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in Table 3-12 Table 3-12. DMA Synchronization Events DSYN VALUE DMA SYNCHRONIZATION EVENT 0000b No synchronization used 0001b McBSP0 receive event 0010b McBSP0 transmit event 0011b McBSP2 receive event 0100b McBSP2 transmit event 0101b McBSP1 receive event 0110b McBSP1 transmit event 0111b McBSP0 receive event ABIS mode 1000b McBSP0 transmit event ABIS mode 1001b McBSP2 receive event ABIS mode 1010b McBSP2 transmit event ABIS mode 1011b McBSP1 receive event ABIS mode 1100b McBSP1 transmit event ABIS mode 1101b Timer interrupt event Functional Overview Submit Documentation Feedback

3.13 General-Purpose I/O Pins 3.13.1 McBSP Pins as General-Purpose I/O TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 3-12. DMA Synchronization Events (continued) DSYN VALUE DMA SYNCHRONIZATION EVENT 1110b INT3 goes active 1111b Reserved The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the number of internal CPU interrupt inputs, channels and are multiplexed with other interrupt sources. DMA channels and share an interrupt line with the receive and transmit portions of the McBSP. When the device is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3-13 Table 3-13. DMA Channel Interrupt Selection INTSEL Value IMR/IFR[6] IMR/IFR[7] IMR/IFR[10] IMR/IFR[11] 00b (reset) BRINT2 BXINT2 BRINT1 BXINT1 01b BRINT2 BXINT2 DMAC2 DMAC3 10b DMAC0 DMAC1 DMAC2 DMAC3 11b Reserved In addition to the standard BIO and XF pins, the device has pins that can be configured for general-purpose I/O. These pins are: McBSP pins BCLKX0/1/2, BCLKR0/1/2 BDR0/1/2 BFSX0/1/2 BFSR0/1/2 BDX0/1/2 HPI data pins HD0-HD7 The general-purpose I/O function of these pins is only available when the primary pin function is not required. When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose inputs or outputs. For more details on this feature, see Section 3.8 Submit Documentation Feedback Functional Overview

3.13.2 HPI Data Pins as General-Purpose I/O 3.14 Device ID Register TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the HPI is disabled (HPIENA or when the HPI is used in HPI16 mode (HPI16 1). Two memory-mapped registers are used to control the GPIO function of the HPI data pins the general-purpose I/O control register (GPIOCR) and the general-purpose I/O status register (GPIOSR). The GPIOCR is shown in Figure 3-20 Reserved DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R Read, W Write, n value present after reset Figure 3-20. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] The direction bits (DIRx) are used to configure HD0-HD7 as inputs or outputs. The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in Figure 3-21 Reserved IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R Read, W Write, n value present after reset Figure 3-21. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] A read-only memory-mapped register has been added to the device to allow user application software to identify on which device the program is being executed. CHIP ID R CHIP REVISION SUBSYSID R R LEGEND: R Read, W Write, n value present after reset Figure 3-22. Device ID Register (CSIDR) [MMR Address 003Eh] Table 3-14. Device ID Register (CSIDR) Bits BIT FUNCTION 15-8 Chip ID (hex code of 16) 7-4 Chip revision ID 3-0 Subsystem ID (0000b for single core devices) Functional Overview Submit Documentation Feedback

3.15 Memory-Mapped Registers TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The device has memory-mapped CPU registers, which are mapped in data memory space address to 1Fh. Each device also has a set of memory-mapped registers associated with peripherals. Table 3-15 gives a list of CPU memory-mapped registers (MMRs) available. Table 3-16 shows additional peripheral MMRs associated with the device. Table 3-15. CPU Memory-Mapped Registers ADDRESS NAME A low word (15-0) AH Accumulator A high word (31-16) AG A Accumulator A guard bits (39-32) BL B Accumulator B low word (15-0) BH C Accumulator B high word (31-16) BG D Accumulator B guard bits (39-32) TREG E Temporary register TRN F Transition register AR0 Auxiliary register AR1 Auxiliary register AR2 Auxiliary register AR3 Auxiliary register AR4 Auxiliary register AR5 Auxiliary register AR6 Auxiliary register AR7 Auxiliary register SP Stack pointer register BK Circular buffer size register BRC Block repeat counter RSA Block repeat start address REA Block repeat end address PMST Processor mode status (PMST) register XPC Extended program page register Reserved Table 3-16. Peripheral Memory-Mapped Registers for Each DSP Subsystem ADDRESS NAME

www.ti.com Table 3-16. Peripheral Memory-Mapped Registers for Each DSP Subsystem (continued) ADDRESS NAME (HMODE only) 45-47 2D-2F Reserved DRR22 McBSP Data Receive Register DRR12 McBSP Data Receive Register DXR22 McBSP Data Transmit Register DXR12 McBSP Data Transmit Register SPSA2 McBSP Subbank Address Register (1) SPSD2 McBSP Subbank Data Register (1) 54-55 36-37 Reserved SPSA0 McBSP Subbank Address Register (1) SPSD0 McBSP Subbank Data Register (1) 58-59 3A-3B Reserved GPIOCR General-Purpose I/O Control Register GPIOSR General-Purpose I/O Status Register CSIDR Device ID Register Reserved DRR21 McBSP Data Receive Register DRR11 McBSP Data Receive Register DXR21 McBSP Data Transmit Register DXR11 McBSP Data Transmit Register 68-71 44-47 Reserved SPSA1 McBSP Subbank Address Register (1) SPSD1 McBSP Subbank Data Register (1) 74-83 4A-53 Reserved DMPREC DMA Priority and Enable Control Register DMSA DMA Subbank Address Register (2) DMSDI DMA Subbank Data Register with Autoincrement (2) DMSDN DMA Subbank Data Register (2) CLKMD Clock Mode Register (CLKMD) 89-95 59-5F Reserved (1) See Table 3-17 for a detailed subaddresses. (2) See Table 3-18 for a detailed registers. Functional Overview Submit Documentation Feedback

3.16 McBSP Control Registers and Subaddresses TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register. Table 3-17 shows the McBSP control registers and their corresponding subaddresses. Table 3-17. McBSP Control Registers and Subaddresses McBSP0 McBSP1 McBSP2 SUB- A RCERB0 39h RCERB1 49h RCERA2 35h 0Bh Receive channel enable register partition B XCERA0 39h XCERA1 49h XCERA2 35h 0Ch Transmit channel enable register partition A XCERB0 39h XCERB1 49h XCERA2 35h 0Dh Transmit channel enable register partition B PCR0 39h PCR1 49h PCR2 35h 0Eh Pin control register Additional channel enable register for RCERC0 39h RCERC1 49h RCERC2 35h 010h 128-channel selection Additional channel enable register for RCERD0 39h RCERD1 49h RCERD2 35h 011h 128-channel selection Additional channel enable register for XCERC0 39h XCERC1 49h XCERC2 35h 012h 128-channel selection Additional channel enable register for XCERD0 39h XCERD1 49h XCERD2 35h 013h 128-channel selection Additional channel enable register for RCERE0 39h RCERE1 49h RCERE2 35h 014h 128-channel selection Additional channel enable register for RCERF0 39h RCERF1 49h RCERF2 35h 015h 128-channel selection Additional channel enable register for XCERE0 39h XCERE1 49h XCERE2 35h 016h 128-channel selection Additional channel enable register for XCERF0 39h XCERF1 49h XCERF2 35h 017h 128-channel selection Additional channel enable register for RCERG0 39h RCERG1 49h RCERG2 35h 018h 128-channel selection Additional channel enable register for RCERH0 39h RCERH1 49h RCERH2 35h 019h 128-channel selection Additional channel enable register for XCERG0 39h XCERG1 49h XCERG2 35h 01Ah 128-channel selection Additional channel enable register for XCERH0 39h XCERH1 49h XCERH2 35h 01Bh 128-channel selection Submit Documentation Feedback Functional Overview

3.17 DMA Subbank Addressed Registers TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The direct memory access (DMA) controller has several control registers associated with it. The main control register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register. When the DMSDI register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. This autoincrement feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature is not required, the DMSDN register should be used to access the subbank. Table 3-18 shows the DMA controller subbank addressed registers and their corresponding subaddresses. Table 3-18. DMA Subbank Addressed Registers SUB- NAME ADDRESS (common channel) DMDSTP 56h/57h 1Fh DMA destination program page address (common channel) DMIDX0 56h/57h 20h DMA element index address register DMIDX1 56h/57h 21h DMA element index address register Functional Overview Submit Documentation Feedback

www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 3-18. DMA Subbank Addressed Registers (continued) SUB- NAME ADDRESS register, channel DMGDA0 56h/57h 25h DMA global destination address reload register, channel DMGCR0 56h/57h 26h DMA global count reload register, channel DMGFR0 56h/57h 27h DMA global frame count reload register, channel XSRCDP 56h/57h 28h DMA extended source data page (currently not supported) XDSTDP 56h/57h 29h DMA extended destination data page (currently not supported) DMGSA1 56h/57h 2Ah DMA global source address reload register, channel DMGDA1 56h/57h 2Bh DMA global destination address reload register, channel DMGCR1 56h/57h 2Ch DMA global count reload register, channel DMGFR1 56h/57h 2Dh DMA global frame count reload register, channel DMGSA2 56h/57h 2Eh DMA global source address reload register, channel DMGDA2 56h/57h 2Fh DMA global destination address reload register, channel DMGCR2 56h/57h 30h DMA global count reload register, channel DMGFR2 56h/57h 31h DMA global frame count reload register, channel DMGSA3 56h/57h 32h DMA global source address reload register, channel DMGDA3 56h/57h 33h DMA global destination address reload register, channel DMGCR3 56h/57h 34h DMA global count reload register, channel DMGFR3 56h/57h 35h DMA global frame count reload register, channel DMGSA4 56h/57h 36h DMA global source address reload register, channel DMGDA4 56h/57h 37h DMA global destination address reload register, channel DMGCR4 56h/57h 38h DMA global count reload register, channel DMGFR4 56h/57h 39h DMA global frame count reload register, channel DMGSA5 56h/57h 3Ah DMA global source address reload register, channel DMGDA5 56h/57h 3Bh DMA global destination address reload register, channel DMGCR5 56h/57h 3Ch DMA global count reload register, channel DMGFR5 56h/57h 3Dh DMA global frame count reload register, channel Submit Documentation Feedback Functional Overview

3.18 Interrupts TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-19 Table 3-19. Interrupt Locations and Priorities TRAP/INTR NAME LOCATION DECIMAL HEX PRIORITY FUNCTION NUMBER (K) RS SINTR Reset (hardware and software reset) NMI SINT16 Nonmaskable interrupt SINT17 Software interrupt #17 SINT18 Software interrupt #18 SINT19 Software interrupt #19 SINT20 Software interrupt #20 SINT21 Software interrupt #21 SINT22 Software interrupt #22 SINT23 Software interrupt #23 SINT24 Software interrupt #24 SINT25 Software interrupt #25 SINT26 Software interrupt #26 SINT27 Software interrupt #27 SINT28 Software interrupt #28 SINT29 Software interrupt #29 SINT30 Software interrupt #30 INT0 SINT0 External user interrupt INT1 SINT1 External user interrupt INT2 SINT2 External user interrupt TINT, SINT3 Timer interrupt RINT0, SINT4 McBSP receive interrupt (default) XINT0, SINT5 McBSP transmit interrupt (default) RINT2, SINT6 McBSP receive interrupt (default) XINT2, SINT7 McBSP transmit interrupt (default) INT3 SINT8 External user interrupt HINT SINT9 100 HPI interrupt RINT1, SINT10 104 McBSP receive interrupt (default) XINT1, SINT11 108 McBSP transmit interrupt (default) DMAC4,SINT12 112 DMA channel (default) DMAC5,SINT13 116 DMA channel (default) Reserved 30-31 120-127 78-7F Reserved The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3-23 Reserved DMAC5 DMAC4 XINT1 RINT1 HINT INT3 XINT2 RINT2 XINT0 RINT0 TINT INT2 INT1 INT0 LEGEND: R Read, W Write, n value present after reset Figure 3-23. IFR and IMR Registers Functional Overview Submit Documentation Feedback

4.1 Documentation Support TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Extensive documentation supports all TMS320 DSP family of devices from product announcement through

applications

development. The following types of documentation are available to support the design and use of the C5000 platform of DSPs: SPRU307: TMS320C54x DSP Family Functional Overview Provides a functional overview of the devices included in the TMS320C54x DSP generation of digital signal processors. Included are descriptions of the CPU architecture, bus structure, memory structure, on-chip peripherals, and instruction set. SPRA164: Calculation of TMS320LC54x Power Dissipation Describes the power-saving dissipaton. From this information, informed decisions can be made regarding power supply requirements and thermal management considerations. The five-volume TMS320C54x DSP Reference Set consists of: SPRU131: TMS320C54x DSP Reference Set, Volume CPU Describes the TMS320C54x 16-bit fixed-point general-purpose digital signal processors. Covered are its architecture, internal register structure, data and program addressing, and the instruction pipeline. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator. SPRU172: TMS320C54x DSP Reference Set, Volume Mnemonic Instruction Set Describes the TMS320C54x digital signal processor mnemonic instructions individually. Also includes a summary of instruction set classes and cycles. SPRU179: TMS320C54x DSP Reference Set, Volume Algebraic Instruction Set Describes the TMS320C54x digital signal processor algebraic instructions individually. Also includes a summary of instruction set classes and cycles. SPRU173: TMS320C54x DSP Reference Set, Volume processor. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator. SPRU302: TMS320C54x DSP Reference Set, Volume Enhanced Peripherals Describes the enhanced peripherals available on the TMS320C54x digital signal processors. Includes the multichannel buffered serial ports (McBSPs), direct memory access (DMA) controller, interprocessor communications, and the HPI-8 and HPI-16 host port interfaces. The reference set describes in detail the TMS320C54x DSP products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices. A series of DSP textbooks is published by Prentice-Hall and John Wiley Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding TI DSP porducts is also available on the web at www.ti.com Submit Documentation Feedback Support

4.2 Device and Development-Support Tool Nomenclature TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. Support Submit Documentation Feedback

5.1 Absolute Maximum Ratings 5.2 Recommended Operating Conditions TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320VC5416 DSP. The absolute maximum ratings are measure over operating case temperature range. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3.1 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to DV SS DV DD Supply voltage I/O range 0.3 V to 4.0 V CV DD Supply voltage core range 0.3 V to 2.0 V V I Input voltage range 0.3 V to 4.5 V V O Output voltage range 0.3 V to 4.5 V T C Operating case temperature range C to 100 C T stg Storage temperature range C to 150 C MIN NOM MAX UNIT DV DD Device supply voltage, I/O 2.7 3.3 3.6 V CV DD Device supply voltage, core (VC5416-160) 1.55 1.6 1.65 V CV DD Device supply voltage, core (VC5416-120) 1.42 1.5 1.65 V DV SS Supply voltage, GND V CV SS RS INTn NMI X2/CLKIN, CLKMDn, BCLKRn, BCLKXn, HCS HDS1 HDS2 HAS 2.4 DV DD 0.3 V IH High-level input voltage, I/O V TRST BIO Dn, An, HDn, TCK DV DD 2.7 V to 3.6 V All other inputs DV DD 0.3 V IL Low-level input voltage 0.3 0.8 V I OH High-level output current (1) (2) mA I OL Low-level output current (1) (2) mA T C Operating case temperature 100 C (1) The maximum output currents are DC values only. Transient currents may exceed these values. (2) These output current limits are used for the test conditions on V OL and V OH except where noted otherwise. Submit Documentation Feedback Electrical Specifications

5.3 Electrical Characteristics 5.3.1 Test Loading Transmission Line 4.0 pF 1.85 pF Z0 = 50 /C0087 (see note) Tester Pin Electronics Data Sheet Timing Reference Point Output Under Test NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. 42 /C0087 3.5 nH Device Pin (see note) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The electrical charactheristics are measured over recommended operating case temperature range (unless otherwise noted). All values are typical unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DV DD 2.7 V to I OH mA 2.2 V OH High-level output voltage (1) V DV DD V to 3.6 I OH MAX 2.4 V OL Low-level output voltage (1) I OL MAX 0.4 V X2/CLKIN µ A TRST HPI16 With internal pulldown 800 HPIENA With internal pulldown, RS 400 Input current I I TMS, TCK, TDI, HPI (2) With internal pullups 400 I DV SS to DV DD µ A A[17:0], D[15:0], Bus holders enabled, DV DD MAX (3) 275 275 HD[7:0] All other input-only pins I DDC Supply current, core CPU CV DD 1.6 f x 160 (4) T C C (5) mA I DDP Supply current, pins DV DD 3.0 f x 160 MHz, (4) T C C (6) mA IDLE2 PLL mode, MHz input Supply current, I DD T C C mA IDLE3 Divide-by-two standby mode, CLKIN stopped T C 100 C C i Input capacitance pF C o Output capacitance pF (1) All input and output voltage levels except RS INT0 INT3 NMI X2/CLKIN, CLKMD1-CLKMD3, BCLKRn, BCLKXn, HCS HAS HDS1 HDS2 BIO TCK, TRST Dn, An, HDn are LVTTL-compatible. (2) HPI input signals except for HPIENA and HPI16, when HPIENA (3) V IL(MIN) V I V IL(MAX) or V IH(MIN) V I V IH(MAX) (4) Clock mode: PLL with external source (5) This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed. (6) This value was obtained with single-cycle external writes, CLKOFF and load pF. For more details on how this calculation is performed, refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164). Figure 5-1. Tester Pin Electronics Electrical Specifications Submit Documentation Feedback

5.3.2 Timing Parameter Symbology TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) X Unknown, changing, or don't care level Submit Documentation Feedback Electrical Specifications

5.3.3 Internal Oscillator With External Crystal C L /C0043C 1C 2 (C 1 /C0041C 2) X1 X2/CLKIN C1 C2 Crystal TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent; see Section 3.10 and connecting a crystal or ceramic resonator across and X2/CLKIN. The CPU clock frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register. The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance of Ω maximum and power dissipation of mW. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5-2 The load capacitors, C and C should be chosen such that the equation below is satisfied. C L (recommended value of pF) in the equation is the load specified for the crystal. Table 5-1. Input Clock Frequency Characteristics MIN MAX Unit f x Input clock frequency (1) (2) MHz (1) This device utilizes a fully static design and therefore can operate with t c(CI) approaching The device is characterized at frequencies approaching Hz (2) It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation. Figure 5-2. Internal Divide-By-Two Clock Option With External Crystal Electrical Specifications Submit Documentation Feedback

5.4 Clock Options 5.4.1 Divide-By-Two and Divide-By-Four Clock Options TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or multiplied by one of several values to generate the internal machine cycle. The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10 When an external clock source is used, the frequency injected must conform to specifications listed in Table 5-3 An external frequency source can be used by applying an input clock to X2/CLKIN with left unconnected. Table 5-2 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or divide-by-4 clock option. Table 5-3 and Table 5-4 assume testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-3 Table 5-2. Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options CLKMD1 CLKMD2 CLKMD3 Clock Mode 1/2, PLL disabled 1/4, PLL disabled 1/2, PLL disabled Table 5-3. Divide-By-2 and Divide-By-4 Clock Options Timing Requirements 5416-120 5416-160 Unit MIN MAX t c(CI) Cycle time, X2/CLKIN ns t f(CI) Fall time, X2/CLKIN ns t r(CI) Rise time, X2/CLKIN ns t w(CIL) Pulse duration, X2/CLKIN low ns t w(CIH) Pulse duration, X2/CLKIN high ns Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics 5416-120 5416-160 PARAMETER Unit MIN TYP MAX MIN TYP MAX t c(CO) Cycle time, CLKOUT 8.33 (1) (2) 6.25 (1) (2) ns t d(CIH-CO) Delay time, X2/CLKIN high to CLKOUT high/low ns t f(CO) Fall time, CLKOUT ns t r(CO) Rise time, CLKOUT ns t w(COL) Pulse duration, CLKOUT low H H H H H H ns t w(COH) Pulse duration, CLKOUT high H H H H H H ns (1) It is recommended that the PLL clocking operation be used for maximum frequency operation. (2) This device utilizes a fully static design and therefore can operate with t c(Cl) approaching The device is characterized at frequencies approaching Hz. Submit Documentation Feedback Electrical Specifications

tr(CO) tf(CO) CLKOUT (see Note A) X2/CLKIN tw(COL)td(CIH-CO) tf(CI) tr(CI) tc(CO) tc(CI) tw(COH) tw(CIH) tw(CIL) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset. Figure 5-3. External Divide-By-Two Clock Timing Electrical Specifications Submit Documentation Feedback

5.4.2 Multiply-By-N Clock Option (PLL Enabled) tc(CO) tc(CI) tw(COH) tf(CO) tr(CO) tf(CI) X2/CLKIN CLKOUT (see Note A) td(CI-CO) tw(COL) tr(CI) tp Unstable tw(CIH) tw(CIL) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in Section 3.10 Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to the TMS320C54x DSP Reference Set, Volume CPU and Peripherals (literature number SPRU131) for detailed information on programming the PLL. When an external clock source is used, the external frequency injected must conform to specifications listed in Table 5-5 Table 5-5 and Table 5-6 assume testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-4 Table 5-5. Multiply-By-N Clock Option Timing Requirements 5416-120 5416-160 Unit MIN MAX Integer PLL multiplier N 1-15) (1) 200 t c(CI) Cycle time, X2/CLKIN PLL multiplier N x.5 (1) 100 ns PLL multiplier N x.25, x.75 (1) t f(CI) Fall time, X2/CLKIN ns t r(CI) Rise time, X2/CLKIN ns t w(CIL) Pulse duration, X2/CLKIN low ns t w(CIH) Pulse duration, X2/CLKIN high ns (1) N is the multiplication factor. Table 5-6. Multiply-By-N Clock Option Switching Characteristics 5416-120 5416-160 PARAMETER Unit MIN TYP MAX MIN TYP MAX t c(CO) Cycle time, CLKOUT 8.33 6.25 ns t d(CI-CO) Delay time, X2/CLKIN high/low to CLKOUT high/low ns t f(CO) Fall time, CLKOUT ns t r(CO) Rise time, CLKOUT ns t w(COL) Pulse duration, CLKOUT low H H H H H H ns t w(COH) Pulse duration, CLKOUT high H H H H H H ns t p Transitory phase, PLL lock-up time ms The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset. Figure 5-4. Multiply-By-One Clock Timing Submit Documentation Feedback Electrical Specifications

5.5 Memory and Parallel I/O Interface Timing 5.5.1 Memory Read TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com External memory reads can be performed in consecutive or nonconsecutive mode under control of the CONSEC bit in the BSCR. Table 5-7 and Table 5-8 assume testing over recommended operating conditions with MSTRB and H 0.5t c(CO) (see Figure 5-5 and Figure 5-6 Table 5-7. Memory Read Timing Requirements 5416-120 5416-160 UNIT MIN MAX t a(A)M1 Access time, read data access from address valid, first read access (1) ns t a(A)M2 Access time, read data access from address valid, consecutive read accesses (1) ns t su(D)R Setup time, read data valid before CLKOUT low ns t h(D)R Hold time, read data valid after CLKOUT low ns (1) Address, W PS DS and IS timings are all included in timings referenced as address. Table 5-8. Memory Read Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(CLKL-A) Delay time, CLKOUT low to address valid (1) ns t d(CLKL-MSL) Delay time, CLKOUT low to MSTRB low ns t d(CLKL-MSH) Delay time, CLKOUT low to MSTRB high ns (1) Address, W PS DS and IS timings are all included in timings referenced as address. Electrical Specifications Submit Documentation Feedback

td(CLKL-MSH) th(D)R td(CLKL-A) CLKOUT A[22:0] (see Note A) D[15:0] R/W (see Note A) MSTRB PS /DS (see Note A) tsu(D)R ta(A)M1 td(CLKL-MSL) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Address, W PS DS and IS timings are all included in timings referenced as address. Figure 5-5. Nonconsecutive Mode Memory Reads Submit Documentation Feedback Electrical Specifications

td(CLKL-MSH) th(D)R td(CLKL-A) A[22:0] (see Note A) td(CLKL-MSL) D[15:0] R/W (see Note A) MSTRB CLKOUT PS /DS (see Note A) th(D)R ta(A)M1 ta(A)M2 tsu(D)Rtsu(D)R td(CLKL-A)td(CLKL-A) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Address, W PS DS and IS timings are all included in timings referenced as address. Figure 5-6. Consecutive Mode Memory Reads Electrical Specifications Submit Documentation Feedback

5.5.2 Memory Write tsu(D)MSH td(CLKL-MSH) td(CLKL-A) CLKOUT A[22:0] (see Note A) D[15:0] MSTRB R/W (see Note A) PS /DS (see Note A) td(CLKL-D)W td(CLKL-MSL) tsu(A)MSL th(D)MSH tw(SL)MS td(CLKL-A) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-9 assumes testing over recommended operating conditions with MSTRB and H 0.5t c(CO) (see Figure 5-7 Table 5-9. Memory Write Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(CLKL-A) Delay time, CLKOUT low to address valid (1) ns t su(A)MSL Setup time, address valid before MSTRB low (1) ns t d(CLKL-D)W Delay time, CLKOUT low to data valid ns t su(D)MSH Setup time, data valid before MSTRB high ns t h(D)MSH Hold time, data valid after MSTRB high ns t d(CLKL-MSL) Delay time, CLKOUT low to MSTRB low ns t w(SL)MS Pulse duration, MSTRB low ns t d(CLKL-MSH) Delay time, CLKOUT low to MSTRB high ns (1) Address, W PS DS and IS timings are all included in timings referenced as address. Address, W PS DS and IS timings are all included in timings referenced as address. Figure 5-7. Memory Write MSTRB Submit Documentation Feedback Electrical Specifications

5.5.3 I/O Read td(CLKL-IOSH) th(D)R td(CLKL-A) CLKOUT A[22:0] (see Note A) D[15:0] IOSTRB R/W (see Note A) IS (see Note A) td(CLKL-IOSL) tsu(D)R ta(A)M1 td(CLKL-A) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-10 and Table 5-11 assume testing over recommended operating conditions, IOSTRB and H 0.5t c(CO) (see Figure 5-8 Table 5-10. I/O Read Timing Requirements 5416-120 5416-160 UNIT MIN MAX t a(A)M1 Access time, read data access from address valid, first read access (1) ns t su(D)R Setup time, read data valid before CLKOUT low ns t h(D)R Hold time, read data valid after CLKOUT low ns (1) Address, W PS DS and IS timings are all included in timings referenced as address. Table 5-11. I/O Read Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(CLKL-A) Delay time, CLKOUT low to address valid (1) ns t d(CLKL-IOSL) Delay time, CLKOUT low to IOSTRB low ns t d(CLKL-IOSH) Delay time, CLKOUT low to IOSTRB high ns (1) Address, W PS DS and IS timings are all included in timings referenced as address. Address, W PS DS and IS timings are all included in timings referenced as address. Figure 5-8. Parallel I/O Port Read IOSTRB Electrical Specifications Submit Documentation Feedback

5.5.4 I/O Write td(CLKL-D)W CLKOUT A[22:0] (see Note A) D[15:0] IOSTRB R/W (see Note A) IS (see Note A) td(CLKL-D)W tsu(D)IOSH th(D)IOSH tsu(A)IOSL tw(SL)IOS td(CLKL-IOSL) td(CLKL-IOSH) td(CLKL-A) td(CLKL-A) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-12 assumes testing over recommended operating conditions, IOSTRB and H 0.5t c(CO) (see Figure 5-9 Table 5-12. I/O Write Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(CLKL-A) Delay time, CLKOUT low to address valid (1) ns t su(A)IOSL Setup time, address valid before IOSTRB low (1) ns t d(CLKL-D)W Delay time, CLKOUT low to write data valid ns t su(D)IOSH Setup time, data valid before IOSTRB high ns t h(D)IOSH Hold time, data valid after IOSTRB high ns t d(CLKL-IOSL) Delay time, CLKOUT low to IOSTRB low ns t w(SL)IOS Pulse duration, IOSTRB low ns t d(CLKL-IOSH) Delay time, CLKOUT low to IOSTRB high ns (1) Address, W PS DS and IS timings are all included in timings referenced as address. Address, W PS DS and IS timings are all included in timings referenced as address. Figure 5-9. Parallel I/O Port Write IOSTRB Submit Documentation Feedback Electrical Specifications

5.5.5 Ready Timing for Externally Generated Wait States TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-13 and Table 5-14 assume testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-10 Figure 5-11 Figure 5-12 and Figure 5-13 Table 5-13. Ready Timing Requirements for Externally Generated Wait States (1) 5416-120 5416-160 UNIT MIN MAX t su(RDY) Setup time, READY before CLKOUT low ns t h(RDY) Hold time, READY after CLKOUT low ns t v(RDY)MSTRB Valid time, READY after MSTRB low (2) ns t h(RDY)MSTRB Hold time, READY after MSTRB low (2) ns t v(RDY)IOSTRB Valid time, READY after IOSTRB low (2) ns t h(RDY)IOSTRB Hold time, READY after IOSTRB low (2) ns (1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states. (2) These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT. Table 5-14. Ready Switching Characteristics for Externally Generated Wait States (1) 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(MSCL) Delay time, CLKOUT low to MSC low ns t d(MSCH) Delay time, CLKOUT low to MSC high ns (1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states. Electrical Specifications Submit Documentation Feedback

tsu(RDY) td(MSCH) CLKOUT A[22:0] READY MSC MSTRB W ait States Generated In- ternally Trailing Cycle Wait States Generated by READY Leading Cycle tv(RDY)MSTRB th(RDY) th(RDY)MSTRB td(MSCL) D[15:0] TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Figure 5-10. Memory Read With Externally Generated Wait States Submit Documentation Feedback Electrical Specifications

tsu(RDY) td(MSCL) CLKOUT A[22:0] D[15:0] READY MSC MSTRB td(MSCH) tv(RDY)MSTRB th(RDY)MSTRB th(RDY) Trailing Cycle Wait States Generated by READY Wait States Generated Internally Leading Cycle TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 5-11. Memory Write With Externally Generated Wait States Electrical Specifications Submit Documentation Feedback

tsu(RDY) td(MSCH) td(MSCL) CLKOUT A[22:0] READY MSC IOSTRB W ait States Generated In- ternally Trailing Cycle Wait States Generated by READY Leading Cycle tv(RDY)IOSTRB th(RDY) th(RDY)IOSTRB D[15:0] TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Figure 5-12. I/O Read With Externally Generated Wait States Submit Documentation Feedback Electrical Specifications

tsu(RDY) td(MSCL) CLKOUT A[22:0] D[15:0] READY MSC IOSTRB td(MSCH) tv(RDY)IOSTRB th(RDY)IOSTRB th(RDY) Trailing CycleWait States Generated by READY Wait States Generated Internally Leading Cycle TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 5-13. I/O Write With Externally Generated Wait States Electrical Specifications Submit Documentation Feedback

5.5.6 HOLD and HOLDA Timings TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-15 and Table 5-16 assume testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-14 Table 5-15. HOLD and HOLDA Timing Requirements 5416-120 5416-160 UNIT MIN MAX t w(HOLD) Pulse duration, HOLD low duration 4H+8 ns t su(HOLD) Setup time, HOLD before CLKOUT low (1) ns (1) This input can be driven from an asynchronous source, therefore, there are no specific timing requirments with respect to CLKOUT. However, if this timing is met, the input will be recognized on the CLKOUT edge referenced. Table 5-16. HOLD and HOLDA Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t dis(CLKL-A) Disable time, Address, PS DS IS high impedance from CLKOUT low ns t dis(CLKL-RW) Disable time, W high impedance from CLKOUT low ns t dis(CLKL-S) Disable time, MSTRB IOSTRB high impedance from CLKOUT low ns t en(CLKL-A) Enable time, Address, PS DS IS valid from CLKOUT low 2H+3 ns t en(CLKL-RW) Enable time, W enabled from CLKOUT low 2H+3 ns t en(CLKL-S) Enable time, MSTRB IOSTRB enabled from CLKOUT low 2H+3 ns Valid time, HOLDA low after CLKOUT low ns t v(HOLDA) Valid time, HOLDA high after CLKOUT low ns t w(HOLDA) Pulse duration, HOLDA low duration ns Submit Documentation Feedback Electrical Specifications

D[15:0] PS , DS, IS A[22:0] HOLDA HOLD CLKOUT ten(CLKL−S) ten(CLKL−S) ten(CLKL−RW) tdis(CLKL−S) tdis(CLKL−S) tdis(CLKL−RW) tdis(CLKL−A) tv(HOLDA) tv(HOLDA) tw(HOLDA) tw(HOLD) tsu(HOLD) tsu(HOLD) ten(CLKL−A) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 5-14. HOLD and HOLDA Timings (HM Electrical Specifications Submit Documentation Feedback

5.5.7 Reset, BIO Interrupt, and MP/ MC Timings BIO CLKOUT RS , INTn, NMI X2/CLKIN th(BIO) th(RS) tsu(INT) tw(BIO)S tsu(BIO) tw(RSL) tsu(RS) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-17 assumes testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-15 Figure 5-16 and Figure 5-17 Table 5-17. Reset, BIO Interrupt, and MP/ MC Timing Requirements 5416-120 5416-160 UNIT MIN MAX t h(RS) Hold time, RS after CLKOUT low (1) ns t h(BIO) Hold time, BIO after CLKOUT low (1) ns t h(INT) Hold time, INTn NMI after CLKOUT low (1) (2) ns t h(MPMC) Hold time, MP/ MC after CLKOUT low (1) ns t w(RSL) Pulse duration, RS low (3) (4) ns t w(BIO)S Pulse duration, BIO low, synchronous ns t w(BIO)A Pulse duration, BIO low, asynchronous ns t w(INTH)S Pulse duration, INTn NMI high (synchronous) ns t w(INTH)A Pulse duration, INTn NMI high (asynchronous) ns t w(INTL)S Pulse duration, INTn NMI low (synchronous) ns t w(INTL)A Pulse duration, INTn NMI low (asynchronous) ns t w(INTL)WKP Pulse duration, INTn NMI low for IDLE2/IDLE3 wakeup ns t su(RS) Setup time, RS before X2/CLKIN low (2) (1) ns t su(BIO) Setup time, BIO before CLKOUT low (1) ns t su(INT) Setup time, INTn NMI RS before CLKOUT low (1) ns t su(MPMC) Setup time, MP/ MC before CLKOUT low (1) ns (1) These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however, if setup and hod timings are met, the input will be recognized on the CLKOUT edge referenced. (2) The external interrupts INT0 INT3 NMI are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a1-0-0 sequence at the timing that is corresponding to three CLKOUTs sampling sequence. (3) If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least µ s to ensure synchronization and lock-in of the PLL. (4) Note that RS may cause a change in clock frequency, therefore changing the value of Figure 5-15. Reset and BIO Timings Submit Documentation Feedback Electrical Specifications

INT, NMI CLKOUT th(INT)tsu(INT)tsu(INT) tw(INTL)A tw(INTH)A MP/MC RS CLKOUT tsu(MPMC) th(MPMC) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 5-16. Interrupt Timing Figure 5-17. MP/ MC Timing Electrical Specifications Submit Documentation Feedback

5.5.8 Instruction Acquisition IAQ and Interrupt Acknowledge IACK Timings IACK IAQ A[22:0] CLKOUT td(CLKL−A) tw(IACKL) td(CLKL−IACKL) tw(IAQL) td(CLKL−IAQL) td(CLKL−IACKH) td(CLKL−IAQH) td(CLKL−A) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-18 assumes testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-18 Table 5-18. Instruction Acquisition IAQ and Interrupt Acknowledge IACK Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(CLKL-IAQL) Delay time, CLKOUT low to IAQ low ns t d(CLKL-IAQH) Delay time, CLKOUT low to IAQ high ns t d(CLKL-IACKL) Delay time, CLKOUT low to IACK low ns t d(CLKL-IACKH) Delay time, CLKOUT low to IACK high ns t d(CLKL-A) Delay time, CLKOUT low to address valid ns t w(IAQL) Pulse duration, IAQ low ns t w(IACKL) Pulse duration, IACK low ns Figure 5-18. Instruction Acquisition IAQ and Interrupt Acknowledge IACK Timings Submit Documentation Feedback Electrical Specifications

5.5.9 External Flag (XF) and TOUT Timings XF CLKOUT td(XF) TOUT CLKOUT tw(TOUT) td(TOUTL)td(TOUTH) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-19 assumes testing over recommended operating conditions and H 0.5t c(CO) (see Figure 5-19 and Figure 5-20 Table 5-19. External Flag (XF) and TOUT Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX Delay time, CLKOUT low to XF high t d(XF) ns Delay time, CLKOUT low to XF low t d(TOUTH) Delay time, CLKOUT low to TOUT high ns t d(TOUTL) Delay time, CLKOUT low to TOUT low ns t w(TOUT) Pulse duration, TOUT ns Figure 5-19. External Flag (XF) Timing Figure 5-20. TOUT Timing Electrical Specifications Submit Documentation Feedback

5.5.10 Multichannel Buffered Serial Port (McBSP) Timing 5.5.10.1 McBSP Transmit and Receive Timings TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-20 and Table 5-21 assume testing over recommended operating conditions (see Figure 5-21 and Figure 5-22 Table 5-20. McBSP Transmit and Receive Timing Requirements (1) 5416-120 5416-160 UNIT MIN MAX t c(BCKRX) Cycle time, BCLKR/X (2) BCLKR/X ext (3) ns t w(BCKRX) Pulse duration, BCLKR/X high or BCLKR/X low (2) BCLKR/X ext (3) ns BCLKR int t su(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low ns BCLKR ext BCLKR int t h(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low ns BCLKR ext BCLKR int t su(BDRV-BCKRL) Setup time, BDR valid before BCLKR low ns BCLKR ext BCLKR int t h(BCKRL-BDRV) Hold time, BDR valid after BCLKR low ns BCLKR ext BCLKX int t su(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low ns BCLKX ext BCLKX int t h(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low ns BCLKX ext t r(BCKRX) Rise time, BCKR/X BCLKR/X ext ns t f(BCKRX) Fall time, BCKR/X BCLKR/X ext ns (1) CLKRP CLKXP FSRP FSXP If the polaritiy of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing analysis should be performend for each specific McBSP interface. (3) P 0.5 processor clock. Submit Documentation Feedback Electrical Specifications

Bit(n-1) (n-2) (n-3) BCLKR BFSR (int) BFSR (ext) BDR tw(BCKRXH) tc(BCKRX) tw(BCKRXL) td(BCKRH-BFRV) td(BCKRH-BFRV) tsu(BFRH-BCKRL) th(BCKRL-BFRH) th(BCKRL-BDRV) tsu(BDRV-BCKRL) tr(BCKRX) tf(BCKRX) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-21. McBSP Transmit and Receive Switching Characteristics (1) 5416-120 5416-160 PARAMETER UNIT MIN MAX t c(BCKRX) Cycle time, BCLKR/X (2) BCLKR/X int (3) ns t w(BCKRXH) Pulse duration, BCLKR/X high (2) BCLKR/X int D (4) D (4) ns t w(BCKRXL) Pulse duration, BCLKR/X low (2) BCLKR/X int C (4) C (4) ns BCLKR int ns t d(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR ext ns BCLKX int t d(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid ns BCLKX ext BCLKX int Disable time, BCLKX high to BDX high impedance following last data t dis(BCKXH-BDXHZ) ns bit of transfer BCLKX ext BCLKX int (5) DXENA BCLKX ext t d(BCKXH-BDXV) Delay time, BCLKX high to BDX valid ns BCLKX int (5) DXENA BCLKX ext BFSX int (5) Delay time, BFSX high to BDX valid t d(BFXH-BDXV) ns ONLY applies when in data delay (XDATDLY 00b) mode BFSX ext (1) CLKRP CLKXP FSRP FSXP If the polaritiy of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing analysis should be performend for each specific McBSP interface. (3) P 0.5 processor clock. (4) T BCLKRX period CLKGDV) C BCLKRX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) when CLKGDV is even D BCLKRX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 +1) when CLKGDV is even (5) Minimum delay times also represent minimum output hold times. Figure 5-21. McBSP Receive Timings Electrical Specifications Submit Documentation Feedback

Bit 0 Bit(n-1) (n-2) (n-3) BCLKX BFSX (int) BFSX (ext) BFSX BDX tc(BCKRX) tw(BCKRXH) tw(BCKRXL) td(BCKXH-BFXV) tsu(BFXH-BCKXL) th(BCKXL-BFXH) tdis(BCKXH-BDXHZ) td(BFXH-BDXV) td(BCKXH-BDXV) td(BCKXH-BDXV) (XDATDLY=00b) tr(BCKRX) tf(BCKRX) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Figure 5-22. McBSP Transmit Timings Submit Documentation Feedback Electrical Specifications

5.5.10.2 McBSP General-Purpose I/O Timing tsu(BGPIO-COH) th(COH-BGPIO) td(COH-BGPIO) CLKOUT BGPIOx Input Mode (see Note A) BGPIOx Output Mode (see Note B) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-22 and Table 5-23 assume testing over recommended operating conditions (see Figure 5-23 Table 5-22. McBSP General-Purpose I/O Timing Requirements 5416-120 5416-160 UNIT MIN MAX t su(BGPIO-COH) Setup time, BGPIOx input mode before CLKOUT high (1) ns t h(COH-BGPIO) Hold time, BGPIOx input mode after CLKOUT high (1) ns (1) BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. Table 5-23. McBSP General-Purpose I/O Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(COH-BGPIO) Delay time, CLKOUT high to BGPIOx output mode (1) ns (1) BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose output. BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input. BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output. Figure 5-23. McBSP General-Purpose I/O Timings Electrical Specifications Submit Documentation Feedback

5.5.10.3 McBSP as SPI Master or Slave Timing Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) BCLKX BFSX BDX BDR tsu(BDRV-BCLXL) td(BCKXH-BDXV) th(BCKXL-BDRV) tdis(BFXH-BDXHZ) tdis(BCKXL-BDXHZ) th(BCKXL-BFXL) td(BFXL-BDXV) td(BFXL-BCKXH) LSB MSB TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-24 to Table 5-31 assume testing over recommended operating conditions (see Figure 5-24 Figure 5-25 Figure 5-26 and Figure 5-27 Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP 10b, CLKXP (1) 5416-120 5416-160 UNIT MASTER SLAVE MIN MAX MIN MAX t su(BDRV-BCKXL) Setup time, BDR valid before BCLKX low (2) ns t h(BCKXL-BDRV) Hold time, BDR valid after BCLKX low 12P (2) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) P 0.5 processor clock. Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 10b, CLKXP (1) 5416-120 5416-160 PARAMETER UNIT MASTER (2) SLAVE MIN MAX MIN MAX t h(BCKXL-BFXL) Hold time, BFSX low after BCLKX low (3) T T ns t d(BFXL-BCKXH) Delay time, BFSX low to BCLKX high (4) C C ns t d(BCKXH-BDXV) Delay time, BCLKX high to BDX valid (5) 10P (5) ns Disable time, BDX high impedance following last data bit from t dis(BCKXL-BDXHZ) C C ns BCLKX low Disable time, BDX high impedance following last data bit from t dis(BFXH-BDXHZ) (5) (5) ns BFSX high t d(BFXL-BDXV) Delay time, BFSX low to BDX valid 4P+ (5) (5) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) T BCLKX period CLKGDV) C BCLKX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) *2P when CLKGDV is even (3) FSRP FSXP As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM FSXM CLKRM FRSRM for master McBSP CLKXM CLKRm FSXM FSRM for slave McBSP (4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). (5) P 0.5 processor clock. Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP 10b, CLKXP Submit Documentation Feedback Electrical Specifications

Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) BCLKX BFSX BDX BDR td(BFXL-BCKXH) tdis(BCKXL-BDXHZ) td(BCKXL-BDXV) th(BCKXH-BDRV) tsu(BDRV-BCKXL) td(BFXL-BDXV) th(BCKXL-BFXL) LSB MSB TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP 11b, CLKXP (1) 5416-120 5416-160 UNIT MASTER SLAVE MIN MAX MIN MAX t su(BDRV-BCKXL) Setup time, BDR valid before BCLKX low (2) ns t h(BCKXH-BDRV) Hold time, BDR valid after BCLKX high 12P (2) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) P 0.5 processor clock. Table 5-27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 11b, CLKXP (1) 5416-120 5416-160 PARAMETER UNIT MASTER (2) SLAVE MIN MAX MIN MAX t h(BCKXL-BFXL) Hold time, BFSX low after BCLKX low (3) C C ns t d(BFXL-BCKXH) Delay time, BFSX low to BCLKX high (4) T T ns t d(BCKXL-BDXV) Delay time, BCLKX low to BDX valid (5) 10P (5) ns Disable time, BDX high impedance following last data bit from t dis(BCKXL-BDXHZ) (5) 10P (5) ns BCLKX low t d(BFXL-BDXV) Delay time, BFSX low to BDX valid D D (5) (5) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) T BCLKX period CLKGDV) C BCLKX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) *2P when CLKGDV is even D BCLKX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 when CLKGDV is even (3) FSRP FSXP As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM FSXM CLKRM FRSRM for master McBSP CLKXM CLKRm FSXM FSRM for slave McBSP (4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). (5) P 0.5 processor clock. Figure 5-25. McBSP Timing as SPI Master or Slave: CLKSTP 11b, CLKXP Electrical Specifications Submit Documentation Feedback

th(BCKXH-BDRV) tdis(BFXH-BDXHZ) tdis(BCKXH-BDXHZ) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) BCLKX BFSX BDX BDR td(BFXL-BCKXL) td(BFXL-BDXV) td(BCKXL-BDXV) tsu(BDRV-BCKXH) th(BCKXH-BFXL) LSB MSB TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP 10b, CLKXP (1) 5416-120 5416-160 UNIT MASTER SLAVE MIN MAX MIN MAX t su(BDRV-BCKXH) Setup time, BDR valid before BCLKX high (2) ns t h(BCKXH-BDRV) Hold time, BDR valid after BCLKX high 12P (2) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) P 0.5 processor clock. Table 5-29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 10b, CLKXP (1) 5416-120 5416-160 PARAMETER UNIT MASTER (2) SLAVE MIN MAX MIN MAX t h(BCKXH-BFXL) Hold time, BFSX low after BCLKX high (3) T T ns t d(BFXL-BCKXL) Delay time, BFSX low to BCLKX lowTNote9543 (4) D D ns t d(BCKXL-BDXV) Delay time, BCLKX low to BDX valid (5) 10P (5) ns Disable time, BDX high impedance following last data bit from t dis(BCKXH-BDXHZ) D D ns BCLKX high Disable time, BDX high impedance following last data bit from t dis(BFXH-BDXHZ) (5) (5) ns BFSX high t d(BFXL-BDXV) Delay time, BFSX low to BDX valid (5) (5) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) T BCLKX period CLKGDV) D BCLKX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 when CLKGDV is even (3) FSRP FSXP As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM FSXM CLKRM FRSRM for master McBSP CLKXM CLKRm FSXM FSRM for slave McBSP (4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). (5) P 0.5 processor clock. Figure 5-26. McBSP Timing as SPI Master or Slave: CLKSTP 10b, CLKXP Submit Documentation Feedback Electrical Specifications

Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) BCLKX BFSX BDX BDR td(BFXL-BCKXL) tsu(BDRV-BCKXL) tdis(BCKXH-BDXHZ) th(BCKXH-BFXL) td(BCKXH-BDXV) th(BCKXL-BDRV) td(BFXL-BDXV) LSB MSB TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP 11b, CLKXP (1) 5416-120 5416-160 UNIT MASTER SLAVE MIN MAX MIN MAX t su(BDRV-BCKXL) Setup time, BDR valid before BCLKX low (2) ns t h(BCKXL BDRV) Hold time, BDR valid after BCLKX low 12P (2) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) P 0.5 processor clock. Table 5-31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP 11b, CLKXP (1) 5416-120 5416-160 PARAMETER UNIT MASTER (2) SLAVE MIN MAX MIN MAX t h(BCKXH-BFXL) Hold time, BFSX low after BCLKX high (3) D D ns t d(BFXL-BCKXL) Delay time, BFSX low to BCLKX low (4) T T ns t d(BCKXH-BDXV) Delay time, BCLKX high to BDX valid (5) 10P (5) ns Disable time, BDX high impedance following last data bit from t dis(BCKXH-BDXHZ) (5) 10P (5) ns BCLKX high t d(BFXL-BDXV) Delay time, BFSX low to BDX valid C C (5) (5) ns (1) For all SPI slave modes, CLKG is programmed as of the CPU clock by setting CLKSM CLKGDV (2) T BCLKX period CLKGDV) C BCLKX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) when CLKGDV is even D BCLKX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 when CLKGDV is even (3) FSRP FSXP As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM FSXM CLKRM FRSRM for master McBSP CLKXM CLKRm FSXM FSRM for slave McBSP (4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). (5) P 0.5 processor clock. Figure 5-27. McBSP Timing as SPI Master or Slave: CLKSTP 11b, CLKXP Electrical Specifications Submit Documentation Feedback

5.5.11 Host-Port Interface Timing 5.5.11.1 HPI8 Mode TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-32 and Table 5-33 assume testing over recommended operating conditions and P 0.5 processor clock (see Figure 5-28 through Figure 5-31 In the following tables, DS refers to the logical OR of HCS HDS1 and HDS2 HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1, and HR/ W Table 5-32. HPI8 Mode Timing Requirements 5416-120 5416-160 UNIT MIN MAX Setup time, HBIL and HAD valid before DS low (when HAS is not used), or HBIL and HAD t su(DSL-HBV) ns valid before HAS low Hold time, HBIL and HAD valid after DS low (when HAS is not used), or HBIL and HAD t h(DSL-HBV) ns valid after HAS low t su(HSL-DSL) Setup time, HAS low before DS low ns t w(DSL) Pulse duration, DS low ns t w(DSH) Pulse duration, DS high ns t su(HDV-DSH) Setup time, HD valid before DS high, HPI write ns t h(DSH-HDV)W Hold time, HD valid after DS high, HPI write ns Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose t su(GPIO-COH) ns input t h(GPIO-COH) Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input ns Submit Documentation Feedback Electrical Specifications

www.ti.com Table 5-33. HPI8 Mode Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t en(DSL-HD) Enable time, HD driven from DS low ns Case 1a: Memory accesses when DMAC is active 36P in 32-bit mode and t w(DSH) 36P (1) t w(DSH) Case 1b: Memory accesses when DMAC is active in 32-bit mode and t w(DSH) 36P (1) Case 1c: Memory accesses when DMAC is active 18P in 16-bit mode and t w(DSH) I8P (1) t w(DSH) Delay time, DS low to HD valid t d(DSL-HDV1) Case 1d: Memory accesses when DMAC is active ns for first byte of an HPI read in 16-bit mode and t w(DSH) I8P (1) Case 2a: Memory accesses when DMAC is inactive 10P and t w(DSH) 10P (1) t w(DSH) Case 2b: Memory accesses when DMAC is inactive and t w(DSH) 10P (1) Case Register accesses t d(DSL-HDV2) Delay time, DS low to HD valid for second byte of an HPI read ns t h(DSH-HDV)R Hold time, HD valid after DS high, for a HPI read ns t v(HYH-HDV) Valid time, HD valid after HRDY high ns t d(DSH-HYL) Delay time, DS high to HRDY low (2) ns Case 1a: Memory accesses when DMAC is active 18P in 16-bit mode (1) Case 1b: Memory accesses when DMAC is active 36P Delay time, DS high to HRDY in 32-bit mode (1) t d(DSH-HYH) ns high (2) Case Memory accesses when DMAC is 10P inactive (1) Case Write accesses to HPIC register (3) t d(HCS-HRDY) Delay time, HCS low/high to HRDY low/high ns t d(COH-HYH) Delay time, CLKOUT high to HRDY high ns t d(COH-HTX) Delay time, CLKOUT high to HINT change ns Delay time, CLKOUT high to HDx output change. HDx is configured as a t d(COH-GPIO) ns general-purpose output (1) DMAS stands for direct memory access controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are affected by DMAC activity. (2) The HRDY output is always high when the HCS input is high, regardless of DS timings. (3) This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously, and do not cause HRDY to be deasserted. Electrical Specifications Submit Documentation Feedback

tsu(HSL-DSL) Valid tsu(HBV-DSL) tsu(HBV-DSL)‡ HAS HAD (see Note A) HBIL th(DSL-HBV) th(DSL-HBV) (see Note B) td(DSL-HDV1) tv(HYH-HDV) Valid Valid Valid td(COH-HYH) Valid td(DSH-HYL) th(DSH-HDV)W Valid tsu(HDV-DSH) td(DSL-HDV2) ten(DSL-HD) HCS HDS HRDY HD READ ValidHD WRITE Processor CLK Second Byte First Byte Second Byte td(DSH-HYH) th(DSH-HDV)R tw(DSL) tw(DSH) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 HAD refers to HCNTL0, HCNTL1, and HR/ W When HAS is not used HAS always high) Figure 5-28. Using HDS to Control Accesses HCS Always Low) Submit Documentation Feedback Electrical Specifications

td(HCS-HRDY) HCS HDS HRDY HINT CLKOUT td(COH-HTX) GPIOx Input Mode (see Note A) CLKOUT th(GPIO-COH) GPIOx Output Mode (see Note A) tsu(GPIO-COH) td(COH-GPIO) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Figure 5-29. Using HCS to Control Accesses Figure 5-30. HINT Timing In Figure 5-31 GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O). Figure 5-31. GPIOx Timings Electrical Specifications Submit Documentation Feedback

5.5.11.2 HPI16 Mode TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P 0.5 processor clock (see Figure 5-32 through Figure 5-34 In the following tables, DS refers to the logical OR of HCS HDS1 and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set, Volume Enhanced Peripherals (literature number SPRU302) for additional information. Table 5-34. HPI16 Mode Timing Requirements 5416-120 5416-160 UNIT MIN MAX t su(HBV-DSL) Setup time, HR/ W valid before DS falling edge ns t h(DSL-HBV) Hold time, HR/ W valid after DS falling edge ns t su(HAV-DSH) Setup time, address valid before DS rising edge (write) ns t su(HAV-DSL) Setup time, address valid before DS falling edge (read) (4P (1) ns t h(DSH-HAV) Hold time, address valid after DS rising edge ns t w(DSL) Pulse duration, DS low ns t w(DSH) Pulse duration, DS high ns Reads 10P (1) Memory accesses with no DMA activity. Writes 10P (1) Reads 16P (1) Cycle time, DS rising edge to Memory accesses with 16-bit DMA t c(DSH-DSH) ns next DS rising edge activity. Writes 16P (1) Reads 24P (1) Memory accesses with 32-bit DMA activity. Writes 24P (1) t su(HDV-DSH)W Setup time, HD valid before DS rising edge ns t h(DSH-HDV)W Hold time, HD valid after DS rising edge, write ns (1) P 0.5 processor clock. Submit Documentation Feedback Electrical Specifications

tc(DSH−DSH) tw(DSH) tsu(HBV−DSL) tw(DSL) th(DSL−HBV) tsu(HAV−DSL) th(DSH−HDV)R tv(HYH−HDV) td(DSL−HYL) HCS HDS HR/W HA[17:0] HD[15:0] HRDY Valid Address Data Valid Address tsu(HBV−DSL) th(DSL−HBV) td(DSL−HDV1) Data td(DSL−HDV1) tv(HYH−HDV) th(DSH−HDV)R td(DSL−HYL) th(DSH−HAV) td(DSL−HDD) td(DSL−HDD) TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com Table 5-35. HPI16 Mode Switching Characteristics 5416-120 5416-160 PARAMETER UNIT MIN MAX t d(DSL-HDD) Delay time, DS low to HD driven Case 1a: Memory accesses initiated immediately following a write 48P t w(DSH) when DMAC is active in 32-bit mode and t w(DSH) was 26P Case 1b: Memory access not immediately following a write when 24P DMAC is active in 32-bit mode Case 1c: Memory accesses initiated immediately following a write Delay time, DS 32P t w(DSH) when DMAC is active in 16-bit mode and t w(DSH) was 18P ns low to HD valid t d(DSL-HDV1) for first word of Case 1d: Memory accesses not immediately following a write when 16P an HPI read DMAC is active in 16-bit mode Case 2a: Memory accesses initiated immediately following a write 20P t w(DSH) when DMAC is inactive and t w(DSH) was 10P Case 2b: Memory accesses not immediately following a write when 10P DMAC is inactive Memory writes when no DMA is active 10P Delay time, DS t d(DSH-HYH) high to HRDY Memory writes with one or more 16-bit DMA channels active 16P ns high Memory writes with one or more 32-bit DMA channels active 24P t v(HYH-HDV) Valid time, HD valid after HRDY high ns t h(DSH-HDV)R Hold time, HD valid after DS rising edge, read ns t d(COH-HYH) Delay time, CLKOUT rising edge to HRDY high ns t d(DSL-HYL) Delay time, DS low to HRDY low ns t d(DSH-HYL) Delay time, DS high to HRDY low ns Figure 5-32. Nonmultiplexed Read Timings Electrical Specifications Submit Documentation Feedback

HD[15:0] HA[17:0] HR/W HDS HCS Data ValidData Valid th(DSH−HDV)W tsu(HDV−DSH)W Valid AddressValid Address th(DSH−HAV) th(DSL−HBV) tw(DSL) tsu(HBV−DSL) tw(DSH) tc(DSH−DSH) td(DSH−HYH) td(DSH−HYL) tsu(HAV−DSH) th(DSL−HBV) tsu(HBV−DSL) th(DSH−HDV)W tsu(HDV−DSH)W CLKOUT HRDY td(COH−HYH) TMS320VC5416 Fixed-Point Digital Signal Processor www.ti.com SPRS095P MARCH 1999 REVISED OCTOBER 2008 Figure 5-33. Nonmultiplexed Write Timings Figure 5-34. HRDY Relative to CLKOUT Submit Documentation Feedback Electrical Specifications

6.1 Package Thermal Resistance Characteristics TMS320VC5416 Fixed-Point Digital Signal Processor SPRS095P MARCH 1999 REVISED OCTOBER 2008 www.ti.com The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s). Table 6-1 provides the estimated thermal resistance characteristics for the recommended package types used on the device. Table 6-1. Thermal Resistance Characteristics PARAMETER GGU PACKAGE PGE PACKAGE UNIT R θ JA C/W R θ JC C/W Mechanical Data Submit Documentation Feedback

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DVC5416PGE160IDWLD ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 100 320VC5416 PGE 160 TMS DVC5416PGE160TOOAN ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 100 320VC5416 PGE 160 TMS DVC5416ZGU160IDWLD ACTIVE BGA MICROSTAR ZGU 144 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 100 DVC5416ZGU 160 TMS320VC5416GGU120 ACTIVE BGA MICROSTAR GGU 144 160 TBD SNPB Level-3-220C-168 HR -40 to 100 DVC5416GGU 120 TMS320VC5416GGU160 ACTIVE BGA MICROSTAR GGU 144 160 TBD SNPB Level-3-220C-168 HR -40 to 100 DVC5416GGU 160 TMS320VC5416PGE120 ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 100 320VC5416PGE 120 TMS TMS320VC5416PGE160 ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 100 320VC5416 PGE 160 TMS TMS320VC5416ZGU120 ACTIVE BGA MICROSTAR ZGU 144 1 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 100 DVC5416ZGU 120 TMS320VC5416ZGU160 ACTIVE BGA MICROSTAR ZGU 144 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 100 DVC5416ZGU 160 TX5416PGE ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 100 320VC5416 PGE 160 TMS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 15-Apr-2017 Addendum-Page 2 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TMS320VC5416 :

• Military: SMJ320VC5416 NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications

MPBG021C – DECEMBER 1996 – REVISED MAY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GGU (S–PBGA–N144) PLASTIC BALL GRID ARRAY 1,40 MAX0,85 0,55 0,45 0,45 0,35 0,95 12,10 11,90SQ 4073221-2/C 12/01 Seating Plane G A D B C E F 32 4 H J L K M N 76 98 1110 1312 9,60 TYP 0,80 0,80 Bottom View A1 Corner 0,08 0,10 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGA/C0116 configuration MicroStar BGA is a trademark of Texas Instruments Incorporated.

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 10/96 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS”AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non- compliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated