Power Management

TWL6030B1A0CMRR.B

Texas Instruments

Fully Integrated Power Management with Switch Mode Charger REVISED JULY 2011

Manufacturer: Texas Instruments

Document: 101 Pages / 962Kb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse T parts

Online Datasheet

Read TWL6030B1A0CMRR.B online.

TWL6030 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 101

Technical content

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 FullyIntegratedPowerManagementwithSwitchModeCharger Check forSamples: TWL6030 1FEATURES • Control – Configurablepower-up and power-down 23• Seven highlyefficient6-MHz buck converters sequences (EPROM programmable)– Two 0.6to2.1V @ 1.6A

Clock managementvibratordriver.) 32-kHz output– One 1.0to3.3V @ 50 mA withbatteryor preregulatedsupply • Batterycharger1.5A – One low noise1.0to3.3V @ 50 mA with – Charger forsingle-cellLi-Ionand batteryor preregulatedsupply Li-Polymerbatterypacks – 3.3V @ 35 mA USB LDO – Switched mode chargerwithintegrated power FET forup to1.5-Acurrent– One LDO forTWL6030 internaluse – High-accuracyvoltageand current– One LDO forinternaland externaluse regulation• USB OTG module – Safetytimerand resetcontrol• Backup batterycharger – Thermal regulationprotection• 10-bitADC with17 inputchannels – Input/outputovervoltageprotection• 13-bitCoulomb counterwithfour – Charging indicatorLED driverprogrammable integrationperiods – Boost mode operationforUSB OTG• Low power consumption – Compliant with:– 5 µA inbackup mode – USB 2.0– 20 µA inwait-onmode – OTG and EH 2.0– 110 µA indeep sleep,withtwo DCDCs active – YD/T 1591-2006
RTC withalarm wake-up mechanism – USB batterycharging1.1and 1.2
SIM and MMC card detections – Japanese batterychargingrequirements
Two digitalPWM outputs • Package 7 mm x 7 mm 187-pinnFBGA
Thermal monitoring APPLICATIONS– High-temperaturewarning
Mobilephones and smart phones– Thermal shutdown
Gaming handsets
Portablemedia players
Portablenavigationsystems
Handheld devices
Tablets Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2SmartReflexisa trademarkofTexas Instruments. 3MIPIisa registeredtrademarkofMobilIndustryProcessorInterface. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com

DESCRIPTION

The TWL6030 deviceisan integratedpower-management integratedcircuit(IC)forapplicationspowered by a rechargeablebattery.The deviceprovidesseven configurablestep-downconverterswithup to1.6Acapabilityfor memory, processorcore,I/O,auxiliary,preregulationforLDOs, etc.The devicealsocontains11 LDO regulators thatcan be suppliedfrom a batteryor a preregulatedsupply.Power-up/power-downcontrollerisconfigurable and can supportany power-up/power-downsequences (EPROM based).The real-timeclock(RTC) providesa 32-kHz outputbuffer,second/minute/hour/day/month/yearinformation,and alarm wake up. The TWL6030 supports32-kHz clockgenerationbased on a crystaloscillator.The deviceintegratesa switched-modecharger allowingfasterbatterycharge,higherefficiency,and lesspower dissipation. The TWL6030 devicegeneratespower suppliesforOMAP ™ 4 processorsand operatestogetherwiththe TWL6040 device,which includesallaudio and relateddetectionfeatures.For audio IC parameters,see the TWL6040 datasheet.In addition,the TWL6030 devicecan be used as a power management multichannelIC (PMIC) forseveralotherprocessors,thankstotheprogrammablestartup/shutdowncontrollerand defaultsupply Figure1 shows theTWL6030 blockdiagram.

2 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table1.PartNumber Differentiation PRIMARY HW CHARGER TRANSPORT MEDIAPART NUMBER ORDERING OMAP VERSION WATCHDOG WATCHDOG QUANTITY TWL6030 TWL6030B107CMRR OMAP4430 Disabled Disabled Tape and reel,2500 TWL6030 TWL6030B107CMR OMAP4430 Disabled Disabled Trays,260 TWL6030 (P)TWL6030B1AECMRR OMAP4430 Disabled Enabled Tape and reel,2500 TWL6030 (P)TWL6030B1AECMR OMAP4430 Disabled Enabled Trays,260 TWL6030 (P)TWL6030B1A0CMRR OMAP4430 Enabled Enabled Tape and reel,2500 TWL6030 (P)TWL6030B1A0CMR OMAP4430 Enabled Enabled Trays,260 TWL6030 TWL6030B1A4CMRR OMAP4460/4470 Disabled Disabled Tape and reel,2500 TWL6030 TWL6030B1A4CMR OMAP4460/4470 Disabled Disabled Trays,260 TWL6030 (P)TWL6030B1AFCMRR OMAP4460/4470 Disabled Enabled Tape and reel,2500 TWL6030 (P)TWL6030B1AFCMR OMAP4460/4470 Disabled Enabled Trays,260 TWL6030 (P)TWL6030B1AACMRR OMAP4460/4470 Enabled Enabled Tape and reel,2500 TWL6030 (P)TWL6030B1AACMR OMAP4460/4470 Enabled Enabled Trays,260 Copyright© 2010–2011,Texas InstrumentsIncorporated 3

3 MHz

Control, data, and test logic Events bus Card detect and PWM Xtal 32K RC 32K RC USB SRP I2C control I2C SmartReflex Events detect SR bus SRI2C_SDA SRI2C_SCL ID CTLI2C_SDA CTLI2C_SCL SIM MMC BATREMOVAL PWM1 BOOT0 BOOT1 BOOT2 BOOT3 RESPWRON NRESWARM PWRON RPWRON PREQ1 PREQ2A PREQ3 INT SYSEN REGEN1 REGEN2 MSECURE CLK32KG CLK32KAO CLK32KAUDIO OSC32KOUT OSC32KIN VAC CHRG_CSIN CHRG_CSOUT CHRG_EXTCHRG_ENZ CHRG_EXTCHRG_STATZ USB charger and VBUS OTG CHRG_PMID CHRG_SW VBUS CHRG_AUXPWR CHRG_GND VANA VANA_IN VRTC_IN VRTC V1V29_SW V1V29_IN V1V29_FDBK V1V29_GND V2V1_SW V1V2_IN V2V1_FDBK V2V1_GND V1V8_SW V1V8_IN V1V8_FDBK V1V8_GND VMEM_SW VMEM_IN VMEM_FDBK VMEM_GND VCORE3_SW VCORE3_IN VCORE3_FDBK VCORE3_GND VCORE2_SW VCORE2_IN VCORE2_FDBK VCORE2_GND VCORE1_SW VCORE1_IN VCORE1_FDBK VCORE1_GND REFS TESTEN TESTV PWM2 10-bit ADC GPADC_IN0 GPADC_IN1 GPADC_VREF1 GPADC_IN2 GPADC_IN3 GPADC_IN4 GPADC_VREF4 GPADC_IN5 GPADC_IN6 GPADC_START Digital filter 13-bit ADC /c83/c68GGAUGE_RESP GGAUGE_RESN OCP bus PREQ2B PREQ2C OSC32KCAP GND_DIG_VRTC VBAT VDD_B4VDD_B2VDD_B1 GND_ANA_B7GND_ANA_B6GND_ANA_B5GND_ANA_B4GND_ANA_B3GND_ANA_B2GND_ANA_B1 VAUX3_IN VAUX3 VCXIO_IN VCXIO VDAC_IN VDAC CHRG_PMID VDD_B3 VUSB CHRG_LED_IN CHRG_LED_TEST CHRG_VREFCHRG_DET_N REFGNDIREFVBGVAUX2VAUX2_INVAUX1VAUX1_INVUSIMVUSIM_IN1VMMCVMMC_IN1VPPVPP_INVIOGND_DIG_VIO Control Ols VPP VMMC VUSIM VAUX1 VAUX2 VAUX3VCXIOVDACVUSB MUXScalers Auto calib TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com DEVICE INFORMATION Figure1. TWL6030 Block Diagram

4 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table2 presentstheballdescriptionoftheTWL6030 device.Figure2 shows theballmapping fromthetopview. Table2.BallDescription CONNECTION IFNAME BALL TYPE I/O(1) DESCRIPTION PU/PD (2) NOT USED CHARGER Switchedchargerauxiliarypower supply, CHRG_AUXPWR E6 Analog I connectedtothebatterypack toprovidepower in Ground – high-impedancemode Switchedchargerboot-strappedcapacitorfortheCHRG_BOOT G2 Analog O Floating –high-sideMOSFET gatedriver CHRG_CSIN E4 Analog I Switchedchargercurrent-senseinput Ground Switchedchargerbatteryvoltage/currentsenseCHRG_CSOUT D4 Analog I Groundinput USB chargingportdetectionsignalfromUSBCHRG_DET_N E5 Analog I GroundPHY CHRG_EXTCHRG_EN J7 Digital O Outputcontrolsignaltoan externalVAC charger FloatingZ Floatingortiedto CHRG_EXTCHRG_ST VRTC (fixed *PUH7 Digital I ExternalchargerstatusinputpinATZ internalpullupto 70–190 kΩ VRTC) CHRG_LED_IN D6 Power I LED indicatorinputsupply Ground ExternalLED driveroutput/dedicatedchargerCHRG_LED_TEST D5 Analog I/O Ground orfloatingTEST ball CHRG_PGND_B1 A5 CHRG_PGND_B2 A6 Ground I Switchedchargerpower ground Ground – CHRG_PGND_B3 B6 CHRG_PGND_B4 B5 CHRG_PMID_B1 E1 SwitchedchargerconnectionpointbetweenCHRG_PMID_B2 F1 Analog O reverseblockingMOSFET and high-side Floating – CHRG_PMID_B3 E2 switchingMOSFET CHRG_PMID_B4 F2 CHRG_SW_B1 A3 CHRG_SW_B2 A4 SwitchedchargerinternalswitchtooutputPower O Floating –inductorconnectionCHRG_SW_B3 B4 CHRG_SW_B4 B3 CHRG_VREF F5 Analog O Switchedchargerinternalbiasregulatorvoltage Floating – Ground (ifnotVAC F4 Power Inputsupplyfroman externalVAC charger –used inBBS) VBUS_B1 C1 Ground (Mustbe connectedtoVBUS_B2 D1 VBUS ifVBUSVBUS inputvoltage,USB batterychargerpowerVBUS_B3 C2 Power I/O detectionfrom –supply PMIC isneeded; forexample,forVBUS_B4 D2 USB bootupt) POWER SUPPLIES (1) I= Input;O = Output (2) PU/PD shows thepullup/downresistorson digitalinputlines.An asteriskindicatesthedefaultoption. Copyright© 2010–2011,Texas InstrumentsIncorporated 5

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Table2.BallDescription(continued) CONNECTION IFNAME BALL TYPE I/O(1) DESCRIPTION PU/PD (2) NOT USED GND_ANA_B1 N8 GND_ANA_B2 M10 GND_ANA_B3 E11 GND_ANA_B4 L13 Ground I Analogpower ground Ground – GND_ANA_B5 D9 GND_ANA_B6 H4 GND_ANA_B7 G7 GND_DIG_VIO M8 Ground I VIO digitalground Ground – GND_DIG_VRTC G4 Ground I VRTC digitalground Ground – PBKG_B11 T1 PBKG_B12 T2 PBKG_B13 R1 PBKG_B2 H5 PBKG_B31 T16 PBKG_B32 T15 Substrate I Substrateground Ground – PBKG_B33 R16 PBKG_B41 A1 PBKG_B42 A2 PBKG_B43 B1 PBKG_B51 A16 PBKG_B53 B16 VDD_B1 N9 VDD_B2 G13 Power I Analoginputvoltagesupply N/A – VDD_B3 B9 VDD_B4 L4 The TWL6030 devicedigitalI/OinputsupplyVIO M9 Power I N/A –voltage(1.8V) VPROG G10 Power I EPROM programmingvoltage Ground – Ground (prefered)VBACKUP E10 Analog I Backup batteryinputvoltage –orFloating VBAT B13 Power I Batteryvoltagesense line N/A – CLOCKING 32-kHzdigitaloutputclockalwayson when VIOCLK32KAO H10 Digital O Floating –inputsupplyispresent 32-kHzdigitalgatedoutputclocktowardtheaudioCLK32KAUDIO E9 Digital O Floating –device 32-kHzdigitalgatedoutputclockcontrolledbyCLK32KG J10 Digital O Floating –software VRTC power supplyexternalfilteringcap fortheOSC32KCAP E8 Analog O Floating –32-kHzcrystaloscillator Digitalclock OSC32KIN A10 Analog I 32-kHzcrystaloscillatorinputordigitalclockinput input,analogclock – input Floatingwhen 32-kHzcrystaloscillatoroutputorfloatingincase digitalclockinput,OSC32KOUT A8 Analog O –ofdigitalclockinput capacitorwhen analogclockinput REFERENCES IREF H12 Analog I/O Referencecurrentgeneration N/A –

6 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table2.BallDescription(continued) CONNECTION IFNAME BALL TYPE I/O(1) DESCRIPTION PU/PD (2) NOT USED REFGND_B1 A9 Ground I System referenceground Ground – REFGND_B2 F12 VBG G12 Analog O Band gap outputreferencevoltage N/A – TESTING Ground (fixed *PDTESTEN J8 Digital I Testmode enable internalpulldown 170–950 kΩtoground) TESTV A15 Analog O Internalvoltagessense line Floating SYSTEM CONTROL PUControlI2C serialclock(I2C voltagelevelissetbyCTLI2C_SCL M4 Digital I/O N/A 0.46–1.76an externalpullup.) kΩ PUControlI2C serialbidirectionaldata(I2C voltageCTLI2C_SDA N4 Digital I/O N/A 0.46–1.76levelissetby an externalpullup.) kΩ MaskableinterruptoutputrequesttothehostINT K10 Digital O Floating –processor BATREMOVAL L12 Digital O Batteryremovalindicator Floating BOOT0 H8 Digital I Bootball0 forpower-upsequence selection Ground orVRTC BOOT1 G8 Digital I Bootball1 forpower-upsequence selection Ground orVRTC BOOT2 G9 Digital I Bootball2 forpower-upsequence selection Ground orVRTC BOOT3 H9 Digital I Bootball3 forpower-upsequence selection Ground orVRTC *PUNRESPWRON N5 Digital O System reset/poweron output Floating 70–190 kΩ Floating(fixed PUNRESWARM M5 Digital I Warm resetinput internalpullupto 170–950 kΩVIO) Floating(useof internalPU/PD) or tiedtocommon PU/*PDPREQ1 J9 Digital I Peripheral1 power requestinput groundorVIO 170–950 kΩ(dependingon selected sensitivity) Floating(useof internalPU/PD) or tiedtocommon PU/*PDPREQ2A K9 Digital I Peripheral2A power requestinput groundorVIO 170–950 kΩ(dependingon selected sensitivity) Floating(useof internalPU/PD) or tiedtocommon PU/*PDPREQ2B K8 Digital I Peripheral2B power requestinput groundorVIO 170–950 kΩ(dependingon selected sensitivity) Floating(useof internalPU/PD) or tiedtocommon PU/*PDPREQ2C M7 Digital I Peripheral2C power requestinput groundorVIO 170–950 kΩ(dependingon selected sensitivity) Copyright© 2010–2011,Texas InstrumentsIncorporated 7

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Table2.BallDescription(continued) CONNECTION IFNAME BALL TYPE I/O(1) DESCRIPTION PU/PD (2) NOT USED Floating(useof internalPU/PD) or tiedtocommon PU/*PDPREQ3 N6 Digital I Peripheral3 power requestinput groundorVIO 170–950 kΩ(dependingon selected sensitivity) PWM1 M11 Digital O Floating – PWM2 M12 Digital O Pulsewidthmodulation2 Floating – Externalon-buttonswitch-onevent(primaryinput *PUPWRON L5 Digital I N/Atolaunchsystemwakeup) 55–370 kΩ REGEN1 K7 Digital O Externalregulatorenable1 Floating – REGEN2 J5 Digital O Externalregulatorenable2 Floating – Floating(fixedExternalremoteswitch-onevent(secondaryinput *PURPWRON K5 Digital I internalpull-uptotolaunchsystemwakeup) 55–370 kΩVBAT) SYSEN M6 Digital O Externalsystemenable Floating – Securemode input.AllowI2C accesstosecure *PDMSECURE N2 Digital I Ground orfloatingregisters. 170–950 kΩ PUSmartReflex™ I2C serialclock(I2C voltagelevel InternalpulluponSRI2C_SCL M13 Digital I/O 0.46–1.76issetby an externalpullup.) VIO kΩ PUSmartReflexI2C serialdata(I2C voltagesetby an InternalpulluponSRI2C_SDA N13 Analog I/O 0.46–1.76externalpullup.) VIO kΩ DETECTION Floating(InternalID E12 Digital I/O USB connectoridentificationsignal –pull-uptoVUSB) InternalpulluptoMMC cardinsertionand extractiondetectionto PU/*PDMMC N11 Digital I VIO orpulldowntodeactivatetheVMMC LDO 70–190 kΩground InternalpulluptoSIM cardinsertionand extractiondetectionto PU/*PDSIM N12 Power I VIO orpulldowntodeactivatetheVUSIM LDO 70–190 kΩground LDO REGULATORS VANA B10 Power O OutputvoltageforVANA regulator N/A – VANA_IN D10 Power I SupplyofoutputstageofVANA regulator VBAT – VAUX1 T8 Power O OutputvoltageforVAUX1 regulator Floating – VAUX1_IN N7 Power I SupplyofoutputstageofVAUX1 regulator VBAT – VAUX2 T9 Power O OutputvoltageforVAUX2 regulator Floating – VAUX2_IN N10 Power I SupplyofoutputstageofVAUX2 regulator VBAT – OutputvoltageforVAUX3 regulator(vibratorVAUX3 R9 Power O Floating –driveroutput) VAUX3_IN R8 Power I SupplyofoutputstageofVAUX3 regulator VBAT – VCXIO F15 Power O OutputvoltageforVCXIO regulator Floating – VCXIO_IN F13 Power I SupplyofoutputstageofVCXIO regulator VBAT – VDAC G15 Power O OutputvoltageforVDAC regulator Floating – VDAC_IN H13 Power I SupplyofoutputstageofVDAC regulator VBAT – VMMC J13 Power O OutputvoltageforVMMC regulator Floating – VMMC_IN J12 Power I Supply1 ofoutputstageofVMMC regulator VBAT – VPP K4 Power O OutputvoltageforVPP regulator Floating – VPP_IN J4 Power I SupplyofoutputstageofVPP regulator VBAT – VRTC D7 Power O OutputvoltageforVRTC regulator N/A –

8 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table2.BallDescription(continued) CONNECTION IFNAME BALL TYPE I/O(1) DESCRIPTION PU/PD (2) NOT USED VRTC_IN D11 Power I InputvoltagesupplyforVRTC regulator VBAT – VUSB A7 Power O OutputvoltageforVUSB regulator Floating – VUSIM B8 Power O OutputvoltageforVUSIM regulator Floating – VUSIM_IN D8 Power I Supply1 ofoutputstageofVUSIM regulator VBAT – MONITORING GGAUGE_RESN D13 Analog I Sense resistorinputsignalnegative(groundside) Ground – Sense resistorinputsignalpositive(batteryGGAUGE_RESP E13 Analog I Ground –negativeside) General-purposeanalog-to-digitalconverterGPADC_IN0 D12 Analog I/O Ground/VRTC –(GPADC) input0 GPADC_IN1 B11 Analog I/O GPADC input1 Ground – GPADC_VREF1 A11 Analog O GPADC outputreference1 Floating – GPADC_IN2 B14 Analog I GPADC input2 Ground – GPADC_IN3 A13 Analog I GPADC input3 Ground – GPADC_IN4 B12 Analog I/O GPADC input4 Ground – GPADC_VREF4 A12 Analog O GPADC outputreference4 Floating – GPADC_IN5 A14 Analog I GPADC input5 Ground – GPADC_IN6 B15 Analog I GPADC input6 Ground – TriggerhardwarerequesttostartGPADC *PDGPADC_START K12 Digital I Groundsynchronousconversion 170–950 kΩ SMPS REGULATORS V1V29_FDBK G16 Analog I V1V29 SMPS feedback Ground – V1V29_GND_B1 H16 Ground I V1V29 SMPS ground Ground – V1V29_GND_B2 H15 V1V29_IN_B1 K16 Power I V1V29 SMPS inputvoltage VBAT – V1V29_IN_B2 K15 V1V29_SW_B1 J16 Power O V1V29 SMPS switch Floating – V1V29_SW_B2 J15 V1V8_FDBK L15 Analog I V1V8 SMPS feedback Ground – V1V8_GND_B1 M16 V1V8_GND_B2 L16 Ground I V1V8 SMPS ground Ground – V1V8_GND_B3 M15 V1V8_IN_B1 T13 V1V8_IN_B2 T14 Power I V1V8 SMPS inputvoltage VBAT – V1V8_IN_B3 R14 V1V8_SW_B1 N16 V1V8_SW_B2 P16 Power O V1V8 SMPS switch Floating – V1V8_SW_B3 P15 V2V1_FDBK F16 Analog I V2V1 SMPS feedback Ground – V2V1_GND_B1 E16 Ground I V2V1 SMPS ground Ground – V2V1_GND_B2 E15 V2V1_IN_B1 C16 Power I V2V1 SMPS inputvoltage VBAT – V2V1_IN_B2 C15 V2V1_SW_B1 D16 Power O V2V1 SMPS switch Floating – V2V1_SW_B2 D15 VMEM_FDBK R13 Analog I VMEM SMPS feedback Ground – Copyright© 2010–2011,Texas InstrumentsIncorporated 9

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Table2.BallDescription(continued) CONNECTION IFNAME BALL TYPE I/O(1) DESCRIPTION PU/PD (2) NOT USED VMEM_GND_B1 T12 Ground I VMEM SMPS ground Ground – VMEM_GND_B2 R12 VMEM_IN_B1 T10 Power I VMEM SMPS inputvoltage VBAT – VMEM_IN_B2 R10 VMEM_SW_B1 T11 Power O VMEM SMPS switch Floating – VMEM_SW_B2 R11 VCORE1_FDBK L2 Analog I VCORE1 SMPS feedback Ground – VCORE1_GND_B1 M1 VCORE1_GND_B2 L1 Ground I VCORE1 SMPS ground Ground – VCORE1_GND_B3 M2 VCORE1_IN_B1 T4 VCORE1_IN_B2 T3 Power I VCORE1 SMPS inputvoltage VBAT – VCORE1_IN_B3 R3 VCORE1_SW_B1 N1 VCORE1_SW_B2 P1 Power O VCORE1 SMPS switch Floating – VCORE1_SW_B3 P2 VCORE2_FDBK R4 Analog I VCORE2 SMPS feedback Ground – VCORE2_GND_B1 T5 Ground I VCORE2 SMPS ground Ground – VCORE2_GND_B2 R5 VCORE2_IN_B1 T7 Power I VCORE2 SMPS inputvoltage VBAT – VCORE2_IN_B2 R7 VCORE2_SW_B1 T6 Power O VCORE2 SMPS switch Floating – VCORE2_SW_B2 R6 VCORE3_FDBK G1 Analog I VCORE3 SMPS feedback Ground – VCORE3_GND_B1 H1 Ground I VCORE3 SMPS ground Ground – VCORE3_GND_B2 H2 VCORE3_IN_B1 K1 Power I VCORE3 SMPS inputvoltage VBAT – VCORE3_IN_B2 K2 VCORE3_SW_B1 J1 Power O VCORE3 SMPS switch Floating – VCORE3_SW_B2 J2 RESERVED PINS RESERVED1 N15 Reserved(tiedtoground) Ground(3) RESERVED2 K13 Reserved(tobe leftfloating) Floating(4) RESERVED3 B7 Reserved(tobe leftfloating) Floating(5) (3) Floatisalsopossible (4) ConnectedtoVMMC_IN1 isalsopossible (5) ConnectedtoVUSIM_IN1 isalsopossible

10 Copyright© 2010–2011,Texas InstrumentsIncorporated

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 T PBKG _B31 PBKG _B32 V1V8 _IN _B2 V1V8 _IN _B1 VMEM _GND _B1 VMEM _SW _B1 VMEM _IN _B1 V AUX2 V AUX1 VCORE 2_IN _B1 VCORE 2_SW _B1 VCORE 2_GND _B1 VCORE 1_IN _B1 VCORE 1_IN _B2 PBKG _B12 PBKG _B1 1 T R PBKG _B33 V1V8 _IN _B3 VMEM _FDBK VMEM _GND _B2 VMEM _SW _B2 VMEM _IN _B2 V AUX3 V AUX _IN VCORE 2_IN _B2 VCORE 2_SW _B2 VCORE 2_GND _B2 VCORE _FDBK VCORE 1_IN _B3 PBKG _B13 R P V1V8 _SW _B2 V1V8 _SW _B3 VCORE 1_SW _B3 VCORE 1_SW _B2 P N V1V8 _SW _B1 SR I2C _SDA SIM MMC V AUX _IN VDD _B1 GND _ANA _B1 V AUX _IN PREQ3 NRESP WRON CTL I2C _SDA MSE CURE VCORE 1_SW _B1 N M V1V8 _GND _B1 V1V8 _GND _B3 SR I2C _SCL PWM2 PWM1 GND _ANA _B2 VIO GND _DIG _VIO PREQ 2C SYSEN NRES WARM CTL I2C _SCL VCORE 1_GND _B3 VCORE 1_GND _B1 M L V1V8 _GND _B2 V1V8 _FDBK GND _ANA _B4 BA T RE MOV AL PWR ON VDD _B4 VCORE _FDBK VCORE 1_GND _B2 L K V1V29 _IN _B1 V1V29 _IN _B2 GP ADC_ ST ART INT PREQ2A PREQ2B REGEN RPWR ON VPP VCORE 3_IN _B2 VCORE 3_IN _B1 K J V1V29 _SW _B1 V1V29 _SW _B2 VMMC VMMC _IN CLK 32K G PREQ1 TEST EN CHRG _EXT CHRG _ENZ REGEN VPP _IN VCORE 3_SW _B2 VCORE 3_SW _B1 J H V1V29 _GND _B1 V1V29 _GND _B2 VDAC _IN IREF CLK 32K AO BOOT3 BOOT0 CHRG _EXT CHRG_ ST A TZ PBKG _B2 GND _ANA _B6 VCORE 3_GND _B2 VCORE 3_GND _B1 H G V1V29 _FDBK VDAC VDD _B2 VBG VPROG BOOT2 BOOT1 GND _ANA _B7 GND _DIG _VRTC CHRG _BOOT VCORE _FDBK G F V2V1 _FDBK VCXIO VCXIO _IN REF GND _B2 CHRG _VREF V AC CHRG _PMID _B4 CHRG _PMID _B2 F E V2V1 _GND _B1 V2V1 _GND _B2 G GAUGE _RESP ID GND _ANA _B3 VBACK UP CLK 32K AUDIO OSC 32K CAP CHRG _AUX PWR CHRG_ DET_N CHRG _CSIN CHRG _PMID _B3 CHRG _PMID _B1 E D V2V1 _SW _B1 V2V1 _SW _B2 G GAUGE _RESN GP ADC _IN0 VRTC _IN V ANA _IN GND _ANA _B5 VUSIM _IN VRTC CHRG _LED_IN CHRG _LED _TEST CHRG_ CSOUT VBUS _B4 VBUS _B2 D C V2V1 _IN _B1 V2V1 _IN _B2 VBUS _B3 VBUS _B1 C B PBKG _B53 GP ADC _IN6 GP ADC _IN2 VBA T GP ADC _IN4 GP ADC _IN1 V ANA VDD _B3 VUSIM CHRG _PGND _B3 CHRG _PGND _B4 CHRG _SW _B3 CHRG _SW _B4 PBKG _B43 B A PBKG _B51 TESTV GP ADC _IN5 GP ADC _IN3 GP ADC _VREF4 GP ADC _VREF1 OSC 32K IN REF GND _B1 OSC 32K OUT VUSB CHRG _PGND _B2 CHRG _PGND _B1 CHRG _SW _B2 CHRG _SW _B1 PBKG _B42 PBKG _B41 A 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SWCS045-003 RESERVED RESERVED RESERVED TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Figure2. TWL6030 Package Top View BallMapping Copyright© 2010–2011,Texas InstrumentsIncorporated 11

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER MIN MAX UNIT Allbattery-relatedinputballs(LDOs and SMPSs) and supplyvoltage:VBAT, VDD, –0.3 5.5 V_IN AllbatterySMPS-relatedinputballs_FDBK –0.3 VOUTmax + 0.3 V Backup batterysupplyvoltageVBACKUP –0.3 5.5 V I/OdigitalsupplyvoltageVIO –0.3 VIOmax + 0.3 V BatterychargersupplyvoltageVBUS -0.3 20.0 V BatterychargersupplyvoltageVAC –0.3 20.0 V BatterychargerCHRG_PMID –0.3 20.0 V BatterychargerCHRG_SW, CHRG_BOOT –0.7 20.0 V Voltagedifferencebetween CSIN and CSOUT inputs(VCSIN -VCSOUT ) –7 7 V BatterychargerCHRG_VREF –0.3 6.5 V BatterychargerCHRG_DET_N –0.3 VUSBmax + 0.3 V Allotherchargeranalog-relatedinputballs,such as CHRG_AUXPWR, –0.3 5.5 VCHRG_CSIN, CHRG_CSOUT, and CHRG_LED_IN Voltageon theUSB OTG ID ball –0.3 5.5 V Voltageon theVRTC GPADC balls:GPADC_IN0, GPADC_IN1, and GPADC_IN4 –0.3 VRTCmax + 0.3 V Voltageon theVANA GPADC balls:GPADC_IN2, GPADC_IN3, GPADC_IN5, and –0.3 VANAmax + 0.3 VGPADC_IN6 Voltageon theVDD_B3 GPADC balls –0.3 5.5 V Voltageon thecrystaloscillatorOSC32KIN ball –0.3 VRTCmax + 0.3 V Voltageon allotheranaloginputballssuch as GGAUGE_RESN, GGAUGE_RESP –0.3 VANAmax + 0.3 V EPROM supplyvoltageVPROG –0.3 20.0 V Voltageon VRTC digitalinputballs –0.3 VRTCmax + 0.3 V Voltageon VIO digitalinputballs –0.3 VIOmax + 0.3 V Voltageon VBAT digitalinputballs –0.3 VBAT + 0.3≤ 5.5 V Externalbuck boostsupplyvoltage –0.3 5.5 V Junctiontemperaturerange –45 150 °C Peak outputcurrenton allotherterminalsthanpower resources –5.0 5.0 mA

12 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER MIN NOM MAX UNIT Main batterysupplyvoltageVBAT 2.5 3.8 4.8 V PreregulatedLDO-relatedinputballs_IN 1.8 3.8 4.8 V OtherLDO-relatedinputballs_IN 2.3 3.8 4.8 V AllbatterySMPS-relatedinputballs_IN 2.5 3.8 4.8 V AllbatterySMPS-relatedinputballs_FDBK VCOREmin 1.1 VOUTmax V Backup batterysupplyvoltageVBACKUP 1.9 3.2 4.8 V I/OdigitalsupplyvoltageVIO VIOmin VIO VIOmax V BatterychargersupplyvoltageVBUS 0 5.0 6.7 V BatterychargersupplyvoltageVAC 0 5.0 10.0 V BatterychargerCHRG_PMID 0 5.0 6.0 V BatterychargerCHRG_SW, CHRG_BOOT 0 5.0 6.0 V BatterychargerCHRG_VREF 0 5.0 6.5 V BatterychargerCHRG_DET_N 0 VUSB VUSBmax V Allotherchargeranalog-relatedinputballs,such as CHRG_AUXPWR, 0 3.8 4.8 VCHRG_CSIN, CHRG_CSOUT, CHRG_LED_IN Voltageon theUSB OTG ID ball 0 VUSB VUSBmax V Voltageon theVRTC GPADC ballsGPADC_IN0, GPADC_IN1, and 0 VRTC VRTCmax VGPADC_IN4 Voltageon theVANA GPADC ballsGPADC_IN2, GPADC_IN3, 0 VANA VANAmax VGPADC_IN5, and GPADC_IN6 Voltageon theVDD_B3 GPADC balls 0 3.8 4.8 V Voltageon thecrystaloscillatorOSC32KIN ball 0 VRTC VRTCmax V Voltageon allotheranaloginputballssuch as GGAUGE_RESN, 0 VANA VANAmax VGGAUGE_RESP EPROM supplyvoltageVPROG 0 8.0 10.0 V Voltageon VRTC digitalinputballs 0 VRTC VRTCmax V Voltageon VIO digitalinputballs 0 VIO VIOmax V Voltageon VBAT digitalinputballs 0 3.8 4.8 V MAXLDO (TDCOVmaxExternalbuck boostsupplyvoltage 3.8 4.8 V+ DV) Ambienttemperaturerange –40 27 85 °C Junctiontemperature(Tj) –40 27 125 °C Storagetemperaturerange –65 27 150 °C Lead temperature(soldering,10 seconds) 260 °C ESD SPECIFICATIONS ESD METHOD STANDARD LEVEL Human body model (HBM) EIA/JESD22-A114D 2 kV Charge devicemodel (CDM) EIA/JESD22-C101C 500 V Copyright© 2010–2011,Texas InstrumentsIncorporated 13

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com

ELECTRICAL CHARACTERISTICS

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Switched-mode regulators C I Inputcapacitor 0.6 4.7 6.5 µF Outputfiltercapacitor 4 10 15 µF C O FiltercapacitorESR f= [1–10]MHz 1 10 20 m Ω V1V29, V2V1, VCORE1, VCORE2, 0.68 1 1.30VCORE3, V1V8, VMEMLO Filterinductor µH Atinductorsaturation,IDC=Isat 0.30 FilterinductorDC resistance 1 50 100 DCR L m Ω FilterinductorQ factor >6 MHz 20 V1V29, V2V1, VCORE2, VCORE3, VMEM ILIMIT[1:0]= 00 (nocurrentlimitation) – – – PMOS currentlimit(highside) mAILIMIT[1:0]= 01 (800mA IOUTmax 1300 1620 2000mode) ILIMIT[1:0]= 1X (1000mA IOUTmax 1640 2050 2520mode) V1V8, VCORE1 ILIMIT[1:0]= 00 (nocurrentlimitation) – – – PMOS currentlimit(highside) ILIMIT[1:0]= 01 (1.2A IOUTmax mode) 1640 2050 2460 mA ILIMIT[1:0]= 10 (1.5A IOUTmax mode) 1920 2400 2800 ILIMIT[1:0]= 11 (1.6A IOUTmax mode) 2540 3100 3600 V1V29_FDBK, V2V1_FDBK, Inputcurrentlimitunder VCORE1_FDBK, VCORE2_FDBK, 10 20 30 mAshort-circuitconditions VCORE3_FDBK, V1V8_FDBK, VMEM_FDBK = 0 V max(Vout+VINF Inputvoltage(functional) 5.5 V0.4,2.5) Inputvoltage(performances) max(Vout+ VINP V1V29, V2V1, VCORE2, MinDOV, 3.8 4.8 V VCORE3, VMEM 2.5) V1V29, V2V1, VCORE2, VCORE3, VMEM IOUT = 800 mA 0.65 IOUT = 1000 mA 0.90DropoutvoltageforperformancesMinDOV V(DOV = Vin–Vout) VCORE1, V1V8 IOUT = 1200 mA 0.70 IOUT = 1500 mA 0.90 IOUT = 2000 mA 1.10 PWM mode: V1V29, V2V1, VCORE2, VCORE3, VMEM (limitationon 0 800 maximum temperature)(1) IOUT Rated outputcurrent PWM mode: VCORE1, V1V8 mA0 1500(limitationon maximum temperature)(2) Pulse-frequencymodulation(PFM) 200mode: All (1) V1V29, V2V1, VCORE2, VCORE3, VMEM atIOUT = 800 mA. Maximum junctiontemperatureforVOUT ≤ 1.4V:125°C. Maximum junctiontemperatureforVOUT > 1.4V :115°C. (2) VCORE1, V1V8 atIOUT = 1500 mA. Maximum junctiontemperatureforVOUT ≤ 1.4V:125°C. Maximum junctiontemperatureforVOUT > 1.4V:115°C.

14 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM mode: V1V29, V2V1, VCORE2, VCORE3, VMEM (limitationon 0 1000 maximum temperature)(3)(4) IOUT EXT Extendedoutputcurrent mA PWM mode: VCORE1, V1V8 (limitationon maximum temperature) 0 1600 (5)(6) Includesvoltagereferences,DC load/lineregulationsinPFM and PWM modes, process,and temperature (–1.2%/+2.4%) 0.6V 0.601 0.608 0.623 1.1V 1.101 1.114 1.141 TDCOV TotalDC outputvoltageaccuracy 1.225V 1.226 1.241 1.271 1.3V 1.301 1.317 1.349 V 1.35V 1.352 1.368 1.401 1.8V 1.801 1.823 1.867 1.9V 1.902 1.925 1.971 2.1V 2.101 2.127 2.178 Low range(EPROM dependent) 0.6 1.3 V Highrange(EPROM dependent) 0.7 1.4 Stepsize 12.5 mV 1.35 1.5VOUT Outputvoltage,programmable Otherselectablevoltages 1.8 V 1.9 2.1 Extendedvoltagerange,multiplierfor 3.0476nominallevels(enabledby EPROM) PWM mode, IOUT = 0 toIOUTmax 5 10 mVpp R V Ripplevoltage PFM mode, IOUT = 1 mA, ΔVOUT /VOUT 1 2 % PWM mode, IOUT = 0 toIOUTmax ,DC LDR DC loadregulation 0.25 0.5 %ΔVOUT /VOUT PWM mode, IOUT = 0 toIOUTmax ,VIN =DC LNR DC lineregulation 0.8 1.6 %VINPmin toVINPmax ,ΔVOUT /VOUT (3) V1V29, V2V1, VCORE2, VCORE3, VMEM atIOUT = 1000 mA. Maximum junctiontemperatureforVOUT ≤ 1.4V:115°C. Maximum junctiontemperatureforVOUT > 1.4V:105°C. (4) Abletowithstandthismaximum currentduringcumulativestresstimeof1900 hours. (5) VCORE1, V1V8 atIOUT = 2000 mA. Maximum junctiontemperatureforVOUT ≤ 1.4V:115°C. Maximum junctiontemperatureforVOUT > 1.4V:100°C. (6) Abletowithstandthismaximum currentduringcumulativestresstimeof1900 hours. Copyright© 2010–2011,Texas InstrumentsIncorporated 15

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V1V29, V2V1, VCORE2, VCORE3, VMEM atVout < 0.75V IOUT = 0–150 mA, Tr/Tf= 100 ns IOUT = 50–250 mA, Tr/Tf= 100 ns 2 3 IOUT = 150–400 mA, Tr/Tf= 100 ns V1V29, V2V1, VCORE2, VCORE3, VMEM atVout ≥ 0.75V IOUT = 0–150 mA, Tr/Tf= 100 ns IOUT = 50–250 mA, Tr/Tf= 100 ns 1 1.5Transientloadregulation,ΔVOUT /TLDR %IOUT = 150–400 mA, Tr/Tf= 100 nsVOUT VCORE1, V1V8 atVout < 0.75V IOUT = 0–150 mA, Tr/Tf= 100 ns IOUT = 50–250 mA, Tr/Tf= 100 ns 3.3 4.2 IOUT = 350–800 mA, Tr/Tf= 100 ns VCORE1, V1V8 atVout >= 0.75V IOUT = 0–150 mA, Tr/Tf= 100 ns IOUT = 50–250 mA, Tr/Tf= 100 ns 2.8 3.6 IOUT = 350–800 mA, Tr/Tf= 100 ns VIN step= ±0.6V;Tr/Tf= 10 us; IOUT =IOUTmaxTransientlineregulation,ΔVOUT /TLNR %VOUT Vout< 0.75V 0.7 1.4 Vout≥ 0.75V 0.5 1.0 IOUT = 200 mA, VOUT withinaccuracy 350 500 µslimits,SMPS notfrequencylocked TON Offtoon IOUT = 200 mA, VOUT withinaccuracy 2 3 mslimits,SMPS frequencylocked TOFF On tooff IOUT = 0 @ VOUT down to10% x VOUT 250 500 µs Pulldownresistor Offmode 3 7.5 15 Ω Outputvoltagesettlingtime From VOUTMIN = 0.6V toVOUTMAX =(normalmode) VCORE1, 50 57 65 µs1.3V ±5%, ILOAD = ILOADmaxVCORE2, VCORE3 From VOUTMIN = 0.6V toVOUTMAX =Slew rate 11 12.7 14 mV/µs1.3V ±5%, ILOAD = ILOADmax Overshoot 3 10 % Switchingfrequency 5.1 6 6.9 MHz Offmode @ 25°C 0.1 0.25 IQOFF Offgroundcurrent µA Offmode 0.2 1 PFM mode, no switching 35 50 V1V29,V2V1,VCORE2,VCORE3,VME M inPWM Mode, IOUT = 0 mA, VIN = 8000IQ On groundcurrent µA3.8V VCORE1,V1V8 inPWM mode, IOUT = 120000 mA, VIN = 3.8V

16 Copyright© 2010–2011,Texas InstrumentsIncorporated

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure3. 0.8A and 1.5A SMPS RegulatorEfficiencies(7) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LDO REGULATORS Connectedfrom_IN toGND. Shared inputtankcapacitance 0.3 10(dependingon platform C IN Inputfilteringcapacitor µFrequirementsand power tree) ForVUSB -Connectedfrom 0.9 4.7 6.5CHRG_PMID toGND C OUT Outputfilteringcapacitor ConnectedfromLDO outputtoGND 0.6 2.2 2.7 µF FilteringDC capacitorESR < 100 kHz 20 100 600 m Ω FilteringAC capacitorESR [1–10]MHz 1 10 20 m Ω VRTC: VBAT duringon mode VBAT min 3.8 5.5 VRTC: VBAT duringbackup mode 1.9 2.1 3.1 VRTC: Vbackup duringbackup 1.9 3.8 5.5mode VAUX1, VAUX2, VAUX3, VCXIO, TDCOV +TDCOV + D V –VDAC, VMMC, VPP, VUSIM (for D V – 5.50.2VOUT > 1.5V) 0.1VINF Inputvoltage(functional) V VAUX1, VAUX2, VAUX3, VCXIO, VDAC, VMMC, VPP, VUSIM (for 1.8 3.8 5.5 VOUT ≤ 1.5V) VANA 2.3 3.8 5.5 VUSB fromVBAT 3.5 3.8 5.5 VUSB fromCHRG_PMID 3.5 6.0 6.8 VRTC VBAT min 3.8 5.5 VANA: VBAT inputsourcesupply 2.3 3.8 4.8onlysupported VAUX1, VAUX2, VAUX3, VCXIO, TDCOVmax +VDAC, VMMC, VPP, VUSIM (for 3.8 4.8D VVOUT > 1.5V)VINP Inputvoltage(performance) V VAUX1, VAUX2, VAUX3, VCXIO, VDAC, VMMC, VPP, VUSIM (for 1.8 3.8 4.8 VOUT ≤ 1.5V) VUSB: fromVBAT 3.6 3.8 4.8 VUSB: fromCHRG_PMID 4.3 5.0 5.5 (7) Coilsused: (a) ForVCORE1: MURATA LQM32PN1R0MG0 3.2x2.5x1 (b) ForVCORE2: MURATA LQM2MPN1R0NG0 2x1.6x1

18 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.0V 1.018 1.2V 1.222 1.3V 1.323 1.4V 1.425 1.5V 1.527 1.6V 1.628 1.7V 1.730 2.4V 2.443 2.5V 2.545 2.75V 2.800 2.8V 2.850 2.9V 2.952 3.0V 3.054 3.3V 3.359 VRTC 1.8V 1.801 1.823 1.890 V 1.0V 1.018 1.2V 1.222 1.3V 1.323 1.4V 1.425 1.5V 1.527 1.6V 1.628 1.7V 1.730 2.4V 2.443 2.5V 2.545 2.75V 2.800 2.8V 2.850 2.9V 2.952 3.0V 3.054 3.3V 3.359 VCXIO, VDAC, IOUT = IOUTmax 150 VANA, IOUT = IOUTmax 100 VMMC, VUSIM: IOUT = 50 mA 140 Dropoutvoltage@V IN_MIN = 2.3V VUSB, @I OUT =IOUTmax 200 VAUX1, VAUX2, VAUX3, VMMC,D V mVVPP, VRTC, VUSIM: VINPmin = 300 TDCOV + D V,@I OUT =IOUTmax VCXIO, VDAC, IOUT = IOUTmax 250 VAUX1, VAUX2, VAUX3, VMMC,Dropoutvoltage@V IN_MIN =1.8V VPP, VUSIM: VINPmin = TDCOV + D V, 400 @I OUT =IOUTmax VANA, VRTC 25 VUSB 35 IOUT Rated outputcurrent mAVDAC, VPP 50 VAUX1, VAUX2, VAUX3, VCXIO, 200VMMC, VUSIM Range 1.0 3.3 V Outputvoltage,programmableVOUT Stepsize 100 mV(exceptVRTC and VANA) Additionalselectablevoltagelevel 2.75 V VANA, VDAC, VPP, VRTC, VUSB 100 250 400 Load currentlimitation mAVAUX1, VAUX2, VAUX3, VCXIO, 400 650 900VMMC, VUSIM Copyright© 2010–2011,Texas InstrumentsIncorporated 19

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC LDR DC loadregulation,∆VOUT /VOUT IOUT = 0 toIOUTmax 0.25 0.5 % VIN = VINPmin toVINPmaxDC LNR DC lineregulation,∆VOUT /VOUT 0.1 0.2 %IOUT = IOUTmax Ton Turn-ontime IOUT = 0,VOUT = 0.1V up toVOUTmin 100 500 µs Toff Turn-offtime(exceptVRTC) IOUT = 0,VOUT down to10% x VOUT 250 500 µs Pulldownresistor(exceptVRTC) Offmode 40 60 80 Ω f= 217 Hz,IOUT = IOUTmax 55 90 PSRR Power supplyripplerejection f= 50 kHz,IOUT = IOUTmax 35 45 dB f= 1 MHz, IOUT = IOUTmax 30 35 Offmode @ 25°C 0 0.05 0.15 IQOFF Offgroundcurrent µA Offmode 0 0.2 1 IOUT = 0,(exceptVDAC) 12 18 23 IQ0 On groundcurrent µA IOUT = 0,VDAC 75 150 175 IOUT < 100 μA 4 On groundcurrentcoefficientOnαQ 100 μA < IOUT < 1 mA 2 %mode, IQOUT = IQ0 + αQ *IOUT IOUT > 1 mA 1 On mode, IOUT = 100 µA toTransientloadregulation,TLDR IOUTmax /2, 0.75 1.5 %∆VOUT /VOUT Tr = Tf= 1 µs Transientlineregulation, VIN step= 600 mVpp, Tr = Tf= 10TLNR 0.25 0.5 %∆VOUT /VOUT µs 100 < f< 10 kHz 5000 8000 10 kHz < f< 100 kHz 1250 2500 Noise(exceptVDAC) nV/√Hz 100 kHz < f< 1 MHz 150 300 f> 1 MHz 250 500 100 < f< 5 kHz 200 400 Noise(VDAC) 5 kHz < f< 400 kHz 62 125 nV/√Hz 400 kHz < f< 10 MHz 25 50 VAUX3 WHEN USED AS VIBRATOR DRIVER C OUT Outputfilteringcapacitor ConnectedfromLDO outputtoGND 0.6 2.2 2.7 µF Outputregulatedoutputrange Configurablestepof100 mV 1.0 3.3 V Vibratorinductiveload ConnectedfromVAUX3 toground 70 350 700 µH Vibratorloadresistance 15 40 50 Ω REFERENCE GENERATOR Filteringcapacitor ConnectedfromVBG toREFGND 30 100 150 nF Biasingresistor(±1%) @ 25°C ConnectedfromIREF toREFGND 0.990 1.000 1.010 M Ω Biasingresistor(±1%) temperature 25 50 ppm/°Ccoefficient VINF InputvoltageVINF Functional 1.9 2.2 2.3 V VINP InputvoltageVINP Performance 2.3 3.8 5.5 V Ground current 15 20 40 µA Start-uptime 1 3 ms CRYSTAL CHARACTERISTICS Crystalfrequency @ specifiedloadcap value 32768 Hz Crystaltolerance T = 25°C –20 0 20 ppm Secondarytemperaturecoefficient –0.04 –0.035 –0.03 ppm/°C 2 Crystalseriesresistor @ fundamentalfrequency 90 kΩ Operatingdrivelevel 0.1 0.5 µW Crystalloadcapacitor(accordingto 12.5 pFcrystaldatasheet)

20 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Shuntcapacitor 1.4 2.6 pF Qualityfactor 8000 80000 CRYSTAL OSCILLATOR EXTERNAL COMPONENTS VRTC power supplyexternalfilteringOSC32KCAP 0.6 1.0 2.7 µFcap Frequency 32.768 kHzLoad capacitorson OSC32KIN and Dutycycle 40 50 60 %OSC32KOUT (parallelmode, includingparasiticofPCB for Riseand falltime(10–90%) 10 20 ns externalcap) Setuptime 1 ms @ 25°C, normalandFrequencyaccuracy(considering –30 0 30high-performance(HP)modescrystaltoleranceand internalload ppm capacitorsvariation) @ 25°C, backup mode –80 0 80 Oscillatorcapacitorratio: 1COSC32KIN/COSC32KOUT Oscillatorcontributioninnormaland Frequencytemperaturecoefficient HP modes (notincludingthecrystal ±0.5 ppm/°C variations) SSB phase noiseata 1-kHzoffset HP mode OSC_HPMODE = 1 –125 dBc/Hzfromthecarrier SSB phase noiseata 100-Hz offset HP mode OSC_HPMODE = 1 –105 dBc/Hzfromthecarrier Cyclejittershortterm(peak-peak) Normal mode OSC_HPMODE = 0 25 ns Period-to-periodjitter,long-term Normal mode OSC_HPMODE = 0 120 ns100k pulses(peak-peak) 20 Hz – 20 kHz flat 0.86 Integratedjitter(HP mode) nsRMS 80 Hz – 20 kHz flat 0.43 Gm boostedduringstart-upphaseStartuptimeon power on 300 msShuntcapacitor≤ 1.4pF Oscillatorratiobetween negative Sixthharmonicmode rejection resistance@ 32 kHz and negative 10RS32/RS200 resistance@ 200 kHz (sixth harmonic) Crystalmounted: – Backup mode (@ 25°C) 1.5 – Normal mode: OSC_HPMODE = 0 3 Ground current µA – HP mode: OSC_HPMODE = 1 5 – Start-up(boost)phase 20 Bypass mode: OSC_BYPASS = 1 3 DutycycleCLK32KAO/CLK32KG Logicoutputsignal 40 50 60 % Riseand falltime(10–20%) CLK32KAO/CLK32KG 5 20 100 ns 32-kHz RC OSCILLATOR Outputfrequency 32 kHz Outputfrequencyaccuracy Aftertrimming –15 0 +15 % Cyclejitter(RMS) 10 % Outputdutycycle 40 50 60 % Settlingtime 150 µs Activecurrentconsumption 4 8 µA Power-down current 30 nA 6-MHz RC OSCILLATOR Outputfrequency 6 MHz Outputfrequencyaccuracy Aftertrimming –10 0 +10 % Cyclejitter(RMS) 5 % Copyright© 2010–2011,Texas InstrumentsIncorporated 21

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Outputdutycycle 40 50 60 % Settlingtime 5 µs Activecurrentconsumption 50 100 µA Power-down current 50 nA CLK32KAUDIO OUTPUT BUFFER Settlingtime 0 25 50 µs Activecurrentconsumption 5 7 10 µA Power down current 30 nA Highoutputlevel(VHOUT) 1.70 1.80 1.90 V Dutycycledegradationcontribution –2 0 2 %

20 Hz–20 kHz flat 0 25 50

Integratedjittercontribution psRMS

80 Hz–20 kHz flat 0 10 20

Externaloutputload 5 10 50 pF Outputdelaytime Outputload= 10 pF 0 15 30 ns Outputrise/falltime Outputload= 10 pF 5 7.5 10 ns VOL = 0.2V ±1% ±2% Outputdrivestrength mA VOH = VHOUT –0.2V BACKUP BATTERY CHARGER VBACKUP toGPADC input VBACKUP from2.4to4.5V 0.2 V/Vattenuation VBACKUP = 0 to2.6VBackup batterychargingcurrent 350 650 900 µABB_CHG_EN = 1 IVBACKUP = –10 µA,BB_SEL = 00 2.90 3.00 3.10(VBAT > 3.2V) IVBACKUP = –10 µA,BB_SEL = 01 2.42 2.52 2.60(VBAT > 2.7V) End backup batterycharging IVBACKUP = –10 µA,BB_SEL = 10 3.05 3.15 3.25 Vvoltage:VBBCHGEND (VBAT > 3.35V) IVBACKUP = –10 µA,BB_SEL = 11 VBAT –0.3 VBAT(VBAT > 2.5V) IVBACKUP = –10 µA,BB_SEL = XX VBAT –0.2 VBAT(VBAT < 2.5V) BB_CHG_EN = 1,IVBACKUP = 0Currentconsumption 10 µAµA Capacitance= 5 to15 mF 10 1500 Backup batteryseriesresistance Ω Capacitance= 100 to2000 mF 5 15 BATTERY CHARGER 0 V < VBUS < 5.25V 1.2 4.7 6.5 µF C VBUS VBUS capacitor(VBUS – PGND) 0 V < VBUS < 6 V 0.9 4.7 6.5 µF ESR (1–10 MHz) 1 10 20 m Ω 0 V < VBUS < 5.25V 1.2 4.7 6.5 µF C PMID PMID capacitor(PMID – PGND) 0 V < VBUS < 6 V 0.9 4.7 6.5 ESR (1–10 MHz) 1 10 20 m Ω 0 V < CSOUT < 4.5V 3 10 15 µF Outputcapacitor(CSOUT – PGND) ESR (1–10 MHz) 20 m Ω 0 V < CSIN < 4.5V 20 100 150 nF Outputcapacitor(CSIN – PGND) ESR (100kHz) 400 m Ω 5 10 20 nF Bootstrapcapacitor(BOOT – SW) ESR (9MHz) 200 m Ω Ref voltagecapacitor 0 V < VREF < 6.5V 0.7 2.2 2.86 µF (VREF – PGND) ESR (1–10 MHz) 20 m Ω

22 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0 A–1.5A 0.7 1 1.45 µH Coil(option1),(SW – CSIN) DCR 130 m Ω 0 A–2.7A 0.7 1 1.3 µH Coil(option2),(SW – CSIN) DCR 60 m Ω Rsense resistor(CSIN – CSOUT) –1% 68 +1% m Ω Outputaveragecurrent CHRG_SW 1.5 1.545 A VBUS > VBUSmin, PWM switching 10 mAVBUS > VBUSmin, PWM not 5IVBUS VBUS supplycurrentcontrol switching 0°C < TJ < 85°C, HZ_MODE = 1, 30 µA32S mode Leakage currentfrombatteryto 0°C < TJ < 85°C, CHRG_AUXPWRIVBUS_LEAK 5 µAVBUS ball = 4.2V,high-impedancemode Nominaloutputchargevoltage, 20-mV steps 3.50 3.54 4.76 Vprogrammable VOREG T = 25°C –0.5 0.5 Voltageregulationaccuracy % Nominaloutputchargecurrent, 300 1500 mAprogrammable IOCHARGE IOCHARGE < 600 mA –5 5 Charge currentaccuracy % IOCHARGE ≥ 600 mA –3 3 Terminationchargecurrent ITERM = 50 mA –33 33 100 mA ≤ ITERM ≤ 250 mA –25 25 % Terminationcurrentaccuracy 300 mA ≤ ITERM ≤ 400 mA –5 5ITERM Bothrisingand falling,2-mV Deglitchtimeforchargeterminationoverdrive, 30 31 34 ms TR ,TF = 100 ns VAC_DET positivethreshold 2.90 3.00 3.15 V VAC detection Hysteresis 100 135 170 mV VBUS_DET positivethreshold 2.90 3.00 3.15 V VBUS detection Hysteresis 100 135 170 mV VAC/VBUS detectiondeglitchtime 25 30 36 ms Inputpower sourcedetectionforVBUS inputvoltagelowerlimit 3.6 3.8 4.0 Vbatterycharging VVBUS_MIN DeglitchtimeforVBUS risingabove Risingvoltage,2-mV overdrive,TR = 4 5 6 msVVBUS_MIN 100 ns HysteresisforVVBUS_MIN Inputvoltagerising 100 200 mV Inputcurrentisautomatically Collapsethreshold reduced,programmable,80-mV 4.2 4.76 V steps AnalogDPM loopkick-inthreshold –2 +2 %accuracy Collapsecomparatorthreshold (DigitalDPM feature) –4 4 %accuracy Analoganticollapsecomparator 50 mVhysteresis VBUS fallingfromcollapsethresholdInputsourcedV/dt 2000 V/stoVINmin VBUS falling 0.0625Collapsedebounce time msVBUS rising 100 Tintdetectioninterval Inputpower sourcedetection 1.7 2 2.6 s Copyright© 2010–2011,Texas InstrumentsIncorporated 23

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIN_LIMIT= 100 mA, VBAT > 84 91 98VBATMIN_LO IIN_LIMIT VBUS inputcurrentlimitingthreshold mA IIN_LIMIT= 500 mA, VBAT > 425 460 495VBATMIN_LO VBUS > VINmin or VREF internalreferencevoltage CHRG_AUXPWR > VBATMIN, 1.65 6.5 V IVREF = 1 mA, CVREF = 1 µF VoltagefromBOOT pintoSW pin Duringchargeorboostoperation 6.5 V Below VOREG 70 120 160 mV Deglitchtime,VCOUT decreasingRecharge thresholdvoltage belowthreshold,TF = 100 ns,10 mV 130 ms overdrive BATTERY CHARGER, BATTERY DETECTION IDETECT batterydetectioncurrent Beginsafterterminationdetected, -0.6 –0.45 -0.2 mAbeforechargedone (sinkcurrent) CHRG_AUXPWR ≤ VOREG TDETECT batterydetectiontime 215 262 335 ms BATTERY CHARGER, SLEEP COMPARATOR VBUS above CHRG_AUXPWR 2.3 CHRG_CHRG_AUXP CHRG_AUVSLP SLEEP stateentrythreshold V ≤ CHRG_AUXPWR ≤ VOREG, AUXPW mVWR+0.0 XPWR+0.1VBUS falling R+0.04 VSLP_ EXIT SLEEP stateexithysteresis 2.3V ≤ HRG_AUXPWR ≤ VOREG 140 200 260 mV DeglitchtimeforVBUS risingabove Risingvoltage,2-mV overdrive,TR = 31 32 34 msVSLP + VSLP_EXIT 100 ns BATTERY CHARGER, PWM Internaltopreverseblocking 180 250 m ΩMOSFET on-resistance InternaltopN-channelswitching Measured fromPMID toSW 120 250 m ΩMOSFET on-resistance InternalbottomN-channelMOSFET Measured fromSW toPGND 150 200 m Ωon-resistance fOSC Oscillatorfrequency 2.7 3 3.3 MHz D MAX Maximum dutycycle 99.5 % D MIN Minimum dutycycle 0 % BATTERY CHARGER, BOOST MODE Boostoutputvoltage(topinVBUS) 2.5V < CHRG_AUXPWR < 4.5V 5.05 V VBUS_B Boostoutputvoltagetolerance Includingline,loadregulation –3 0 3 % Maximum outputcurrentforboostat VBUS_B = 5.10V,IBO1 200 mAUSB connectorlevel 2.5V < CHRG_AUXPWR < 4.5V Maximum outputcurrentforboostat VBUS_B = 5.10V,IBO2 235 mAPMID connectorlevel 2.5V < CHRG_AUXPWR < 4.5V Overvoltageprotectionthresholdfor ThresholdoverVBUS toturnoff 5.8 6.0 6.2 Vboost(VBUS pin) converterduringboostVBUSOVP Hysteresis VBUS fallingfromabove VBUSOVP 90 125 160 mV CHRG_AUXPWR = 3.6V,IBO = 200 Efficiency mA, TA = 25°C, synchronous 70 85 % operation IDDQ Quiescentcurrent 2.34 2.7 mA Maximum batteryvoltageforboost VCSOUT risingedge duringboost 4.75 4.9 5.05 V(CSOUT pin) VBATMAX VCSOUT fallingfromaboveHysteresis 149 200 260 mVVBATMAX

24 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Minimum batteryvoltageforboost 2.5 V(CHRG_AUXPWR pin) VBATMIN BoostoutputresistanceatHP mode HZ_MODE = 1 165 kΩ(fromVBUS toPGND) BATTERY CHARGER, PROTECTION ThresholdoverVBUS toturnoffVBUS OVP thresholdvoltage 6.3 6.5 6.7 VVOVP_ converterduringcharge VBUS Hysteresis VBUS fallingfromabove VOVP_VBUS 120 140 160 mV VCSOUT thresholdoverVOREG toBatteryOVP thresholdvoltage 110 117 121turnoffchargerduringcharge VOVP_ VBAT % Lower limitforVCSOUT fallingfromHysteresis 11above VOVP_VBAT BUCK_HSLIMI = 0:2.55A 2.10 2.55 3.30ILIMITcycle-by-cyclecurrentlimitfor Acharge(1) BUCK_HSLIMI = 1:1.90A default 1.50 1.90 2.60 Short-circuitvoltagethreshold CHRG_AUXPWR rising(default) 2.00 2.10 2.20 V VBAT_ CHRG_AUXPWR fallingfromaboveSHORT Hysteresis 90 100 110 mVVBAT_SHORT IBAT_ Short-circuitdetectioncurrent CHRG_AUXPWR ≤ VBAT_SHORT 20 30 40 mA SHORT VBUS inputcurrent VBUS = 9.7V,OVP active 4 mA Temperaturethreshold, 148TCHRGSHTDWNChargerthermalshutdown °C Hysteresis,TCHRGHYS 10 ThermalregulationthresholdTCF 125 °C BATTERY TEMPERATURE MEASUREMENT R BRI Externalpulldownresistor 0 130 kΩ IBRI Currentsourceforthedetection 7.5 µA VBRIRef Detectionthreshold Threshold 1.5 1.6 V Offsetofthecomparator –10 10 mV Currentconsumptionofthe 10 µAcomparator Delayofthecomparator With>10-mV overdrive 10 µs INDICATOR LED DRIVER VBAT 4.8 V CH_LED_CURR[1:0] = 00 0 0 CH_LED_CURR[1:0] = 01 –15% 1 +15% LED current mA CH_LED_CURR[1:0] = 10 –15% 2.5 +15% CH_LED_CURR[1:0] = 11 –15% 5 +15% Riseand falltimeforthecurrent Transitionon PWM signal,10–90% 5 µs CH_LED_CURR[1:0] from00 →Startuptime 20 µsothers Disabled VRTC (backupmode) 0.1 VRTC (wait-on/sleep/activemodes) 1 2 µA VAC (@ 20 V) 70 Quiescentcurrent CHRG_PMID (@ 5.25V) 20 CHRG_PMID (@ 20 V) 70 CH_LED_CURR[1:0] = 01 (1mA) 200 CH_LED_CURR[1:0] = 10 (2.5mA) 400 µA CH_LED_CURR[1:0] = 11 (5mA) 750 (1) Ifusinga chargerwitha currentchargealwayslowerand equalto1.25A,you can use a 1.5-Acurrentratedinductor.Ifthecurrent chargeishigherthan1.25A,a 2.1-Acurrentratedinductormust be used. Copyright© 2010–2011,Texas InstrumentsIncorporated 25

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CH_LED_CURR[1:0] = 00,can bePulldownresistance 50 100 200 kΩdisabledby theDIS_PULLDOWN bit Voltageattheoutputfor 3.2 Vperformance CHRG_LED_TEST pinisdrivenVoltageattheoutputfortolerance 5.5 Vexternally Dropoutvoltage 1 mA 0.2 Minimum voltagebetween 2.5mA 0.4 VCHRG_LED_IN and 5 mA 0.6CHRG_LED_TEST VAC voltage Duringoperation 4.1 V VBUS voltage Duringoperation 4.0 V CHRG_LED_IN voltage 2.3 5.5 V USB OTG ID EXTERNAL RESISTORS SPECIFICATIONS R ID_FLOAT ID pulldown,when ID pinisfloating Inputspec forexternalID resistor 220 kΩ ACA ID pulldown,TWL6030 isR ID_A Inputspec forexternalID resistor 119 132 kΩA-Device ACA ID pulldown,TWL6030 isR ID_B Inputspec forexternalID resistor 65 72 kΩB-Device,butcan’tconnect ACA ID pulldown,TWL6030 isR ID_C Inputspec forexternalID resistor 35 39 kΩB-Device,can connect R IDGND ID pulldownwhen ID pinisgrounded Inputspec forexternalID resistor 1 kΩ USB OTG PULLUP AND PULLDOWN RESISTORS R ID_PU_100 ID 100k pulluptoVUSB 70 100 130 kΩ K R ID_PU_220 ID 220k pulluptoVUSB 160 220 280 kΩ K R ID_GND_D ID 10k pulldowntoground 1 10 20 kΩ RV ID internalleakagewithoutGPADCR ID_ LKG 350 nA(7V) ID internalleakagewithoutGPADCR ID_ LKG 650 nA(2V) ID externalleakage –1.5 0 1 µA USB OTG COMPARATORS VID_WK ID wake-up comparatorthreshold No hysteresis 0.300 0.650 1.150 V ID wake-up equivalentthresholdR ID_WK_UP 10 100 220 kΩresistance VID_CMP1 ID comparator1 threshold No hysteresis 0.150 0.200 0.250 V VID_CMP2 ID comparator2 threshold No hysteresis 0.683 0.720 0.757 V VID_CMP3 ID comparator3 threshold No hysteresis 1.300 1.400 1.500 V VID_CMP4 ID comparator4 threshold No hysteresis 2.350 2.500 2.650 V USB OTG CURRENT SOURCES IID_WK_SRC ID wake-up currentsource VID < 2.75V 3.5 9 25 µA IID_SRC_16u ID currentsource(trimmed) VID < 2.75V 15.5 16 16.5 µA IID_SRC_5u ID currentsource VID < 2.75V 4.5 5 5.5 µA USB OTG ADP COMPARATORS VADP_ PRB ADP probingvoltagethreshold No hysteresis 0.6 0.65 0.7 V VADP_ SNS ADP sensingvoltagethreshold No hysteresis 0.20 0.40 0.55 V VADP_ ADP dischargevoltage 0.15 V DSCHRG USB OTG ADP CURRENT SOURCES/SINKS VBUS_IAD ADP sourcecurrent VBUS < 0.8V 1.10 1.40 1.65 mAP_SRC

26 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT USB OTG ADP TIMINGS T_ADP_SI ADP sinktime 13 14 15 msNK TA_ADP_ ADP probingperiod,A-device 1.25 1.75 1.85 sPRB TA_ADP_ ADP probingperiod,B-device 1.9 2.0 2.6 sPRB T_ADP_S ADP sensingtime-out 3 sNS USB OTG COMPARATORS VVBUS_W VBUS wake-up comparator 2.90 3.00 3.15 VKUP_UP threshold(up) VVBUS_W VBUS wake-up comparatorKUP_DW 2.80 2.90 3.05 Vthreshold(down)N VVBUS_W VBUS wake-up hysteresisvoltage 50 100 175 mVKUP_HYS VA_VBUS A-deviceVBUS validcomparator No hysteresis 4.4 4.5 4.6 V_VLD threshold VB_SESS B-devicesessionvalidcomparator 2.2 2.4 2.6 V_VLD_UP threshold(up) VB_SESS B-devicesessionvalidcomparator_VLD_DW 2.1 2.3 2.5 Vthreshold(down)N VB_SESS B-devicesessionvalidhysteresis_VLD_HY 20 80 140 mVvoltageS VA_SESS A-devicesessionvalidcomparator 0.9 1.1 1.3 V_VLD_UP threshold(up) VA_SESS A-devicesessionvalidcomparator_VLD_DW 0.8 1.0 1.2 Vthreshold(down)N VA_SESS A-devicesessionvalidhysteresis_VLD_HY 10 40 70 mVvoltageS VB_SESS B-devicesessionend comparator 0.3 0.5 0.8 V_END_UP threshold(up) VB_SESS B-devicesessionend comparator_END_DW 0.2 0.4 0.7 Vthreshold(down)N VB_SESS B-devicesessionend hysteresis_END_HY 10 40 70 mVvoltageS VOTG_SE OTG sessionvalidcomparatorSS_VLD_ 2.90 3.10 3.40 Vthreshold(up)UP VOTG_SE OTG sessionvalidcomparatorSS_VLD_ 2.80 3.00 3.30 Vthreshold(down)DWN VOTG_SE OTG sessionvalidhysteresisSS_VLD_ 20 80 140 mVvoltageHYS VOTG_OV OTG overvoltagecomparator 6.3 6.5 6.8 VV_UP threshold(up) VOTG_OV OTG overvoltagecomparator 6.2 6.4 6.7 VV_DWN threshold(down) Copyright© 2010–2011,Texas InstrumentsIncorporated 27

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOTG_OV OTG overvoltagehysteresisvoltage 40 110 180 mVV_HYS GAS GAUGE Currentmeasurement range 10-mΩ sense resistor –6.2 0 6.2 A CG_PERIOD[1:0] = 00 200 CG_PERIOD[1:0] = 01 200 Offsetbeforeautocalibration µV CG_PERIOD[1:0] = 10 200 CG_PERIOD[1:0] = 11 450 CG_PERIOD[1:0] = 00 10 CG_PERIOD[1:0] = 01 10 \` Offsetafterautocalibration µV CG_PERIOD[1:0] = 10 100 CG_PERIOD[1:0] = 11 450 Usableinputvoltagerange –62 0 62 mV Inputclockfrequency 32-kHzcrystaloscillator 32.768 kHz Power on;FG_EN = 1 50 70 Currentconsumption µA Power off;FG_EN = 0 0.2 00:250 ms 250 01:62.5ms 62.5Integrationperiod(samplecounter msuses 32-kHzcrystaloscillator) 10:15.625ms 15.625 11:3.90625ms 3.90625 Externalsense resistor 10 m Ω CG_PERIOD[1:0] = 00 1 + 13 CG_PERIOD[1:0] = 01 1 + 11Integratordatasize(two’s Bitcomplement) CG_PERIOD[1:0] = 10 1 + 9 CG_PERIOD[1:0] = 11 1 + 7 CG_PERIOD[1:0] = 00 -3.5 0 +3.5 CG_PERIOD[1:0] = 01 -2.5 0 +2.5 INL Integralnonlinearity LSB CG_PERIOD[1:0] = 10 -2.0 0 +2.0 CG_PERIOD[1:0] = 11 -1.5 0 +1.5 CG_PERIOD[1:0] = 00 -4.0 0 +4.0 CG_PERIOD[1:0] = 01 -2.5 0 +2.5 DNL Differentialnonlinearity LSB CG_PERIOD[1:0] = 10 -1.5 0 +1.5 CG_PERIOD[1:0] = 11 -1.0 0 +1.0 Accumulatordatasize 1 + 31 Bit Offsetdatasize 1 + 9 Bit Sample counterdatasize 24 Bit GPADC Currentconsumption GPADC_EN = 1 750 900 1400 µA Off– mode current GPADC_EN = 0 1 µA RunningfrequencyF 0.85 1 1.15 MHz ClockperiodT = 1/F Dutycycle50/50 1 µs Resolution 10 Bit Number ofexternalinputs 7 Number ofinternalinputs 10

28 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT N = number ofanaloginputsto 0 17convertinone sequence GPADC_EN 0 to1 orGPADC_EN 1Turnon/offtime 0 50 100 µsto0 Gain error(withoutscalar) –3.5 0 3.5 % Offset(inputsusingopamp-based Channel11 (ICHG) –20 0 20 LSBscalar) Offset(inputsusingresistivescalar) –9 0 9 LSB Offset(otherinputswithoutscalar) –9 0 9 LSB Offsetdrift(aftertrimming) Temperatureand supply –1 0 1 LSB Gain errordrift(includingreference Temperatureand supply –0.6 0 0.2 %voltage) Integralnonlinearity Bestfitting –2 0 2 LSB Differentialnonlinearity –2 0 2 LSB GPADC_IN# inputimpedance 100 M Ω InputcapacitorC bank 12 pF Maximum sourceinputresistance 100 kΩRS (forallinternalorexternalinputs) GPADC voltagereference 1.25 V Inputrange(SAR) 0 1.25 V Gain errorofthescalar –1 0 1 % GPADC_IN0 currentsource ±5% 7 µA GPADC_IN0 additionalcurrent ±5% 15 µAsource THERMAL MONITORING Offmode 0.1Offgroundcurrent(twosensorsonIQOFF µAthedie,specificationforone sensor) @ 25°C offmode 0.5 On mode, standardmode 7 15On groundcurrent(twosensorsonIQO µAthedie,specificationforone sensor) On mode, GPADC measurement 25 40 Risingtemperature 104 117 127 00 (firsthot-diethreshold) °C Fallingtemperature 95 108 119 Risingtemperature 109 121 132 01 (secondhot-diethreshold) °C Fallingtemperature 99 112 123 Risingtemperature 113 125 136 10 (thirdhot-diethreshold) °C Fallingtemperature 104 116 128 Risingtemperature 118 130 141 11 (fourthhot-diethreshold) °C Fallingtemperature 108 120 132 Risingtemperature 136 148 160 Thermalshutdown °C Fallingtemperature 126 138 150 SYSTEM CONTROL THRESHOLDS POR rising-edgethreshold 2.00 2.15 2.50 V POR falling-edgethreshold 1.90 2.00 2.10 V POR hysteresis Risingedge – fallingedge 40 150 350 mV VBATMIN Thresholdofswitch-off(configurable 2.0 3.1 V_LO by 50-mV steps) VBATMIN Thresholdofswitch-on(configurable 2.5 3.55 V_HI by 50-mV steps) CURRENT CONSUMPTION, BACKUP MODE VBAT = 0 VVBACKUP, suppliedon VBACKUP 5 8 µAVBACKUP = 3.2V VBACKUP = 0 VVBAT, suppliedon VBAT 11 16 µAVBAT = 2.7V Copyright© 2010–2011,Texas InstrumentsIncorporated 29

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION, WAIT-ON STATE VBAT = 3.8V 20 30 µA CURRENT CONSUMPTION, SLEEP STATE VBACKUP = 0 V,VBAT = 3.8V VANA = 0 V,VAUX1 = 0 V,VAUX2 = 0 V,VAUX3 = 0 V,VCXIO = 0 V, VDAC = 0 V VMMC = 0 V,VPP = 0 V,VBRTC = 1.8V,VRTC = 0V, VUSB = 0 V,VUSIM = 0 V,V1V29 = 0 V,V1V8 = 1.8V,V2V1 = 0 V, VCORE1 = 0 V,VCORE2 = 0 V,V1V8 and VMEM enabled,no load 110 µAVCORE3 = 0 V,VMEM = 0 V RC6MHZ = OFF, CLK32KG = OFF, CLK32KAUDIO = OFF VBG = ON, VBATMIN_HI = OFF, TMP = OFF, FG = OFF EPROM Features: BSI_ISOURCE = OFF, BAT_DET_EN = OFF, VMEM = 1.35 V The followingtabledescribesthedigitalinputsignalelectricalparameters. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWRON, RPWRON Low-levelinputvoltageVIL-related –0.3 0 0.35× VBAT VtoVBAT/VDD High-levelinputvoltageVIH-related VBAT + 0.3≤0.65× VBAT VBAT VtoVBAT/VDD 5.5 BOOT0, BOOT1, BOOT2, BOOT3, CHRG_EXTCHRG_STATZ, GPADC_START, MMC, MSECURE, NRESWARM, OSC32KIN, PREQ1, PREQ2A, PREQ2B, PREQ2C, PREQ3, SIM,TESTEN Low-levelinputvoltageVIL-related –0.3 0 0.35× VR VtoVIO orVRTC High-levelinputvoltageVIH-related 0.65× VR VR VR + 0.3 VtoVIO orVRTC CTLI2C_SCL, CTLI2C_SDA, SRI2C_SCL, SRI2C_SDA Low-levelinputvoltageVIL-related –0.3 0 0.3× VIO VtoVIO High-levelinputvoltageVIH-related 0.7× VIO VIO VIO + 0.3 VtoVIO Hysteresis 0.1× VIO V 1.2-VSPECIFIC RELATED I/Os:PREQ3 (1)(2) Low-levelinputvoltageVIL-related –0.3 0 0.3× VIO VtoVIO High-levelinputvoltageVIH-related 0.7× VIO VIO VIO + 0.3 VtoVIO (1) PREQ3 can be programmed fortwo differentinputsupplies(1.2/1.8V) and,as such,has a configurableinputthreshold. (2) Applying1.8-Vinputlogicon thePREQ3 ballwhen the1.2-Vsupplymode isselecteddoes notdamage thePREQ3 inputbuffer. Nevertheless,because thethresholdisreducedtoits1.2-Vconfiguration,theinputbufferismore sensitivetothelow1.8-Vlogiclevel. The followingtabledescribesthedigitaloutputsignalelectricalparameters. PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT REGEN1, REGEN2 Low-leveloutputvoltageVOL IOL = 100 µA 0 0.1× VBAT 0.2× VBAT V High-leveloutputvoltageVOH IOH = 100 µA 0.8× VBAT 0.9× VBAT VBAT V BATREMOVAL, CLK32KAO, CLK32KG, INT,CHRG_EXTCHRG_ENZ, NRESPWRON, PWM1, PWM2, SYSEN (1) Alloutputsignalsareguaranteedlowwhen VRTC isnotavailable,especiallyREGEN1, REGEN2, and SYSEN, allthreeofwhichcontrol some externalpower resources.

30 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT Low-leveloutputvoltageVOL -relatedIOL = 2 mA 0 0.18 0.45 VtoVIO orVRTC Low-leveloutputvoltageVOL -relatedIOL = 100 µA 0 0.09 0.2 VtoVIO orVRTC High-leveloutputvoltage IOH = 2 mA VR – 0.45(2) VR – 0.18(2) VR VVOH -relatedtoVIO orVRTC High-leveloutputvoltage IOH = 100 µA VR – 0.2(2) VR – 0.09(2) VR VVOH -relatedtoVIO orVRTC CTLI2C_SDA, SRI2C_SDA Low-leveloutputvoltageVOL -related3-mA sinkcurrent 0 0.1× VIO 0.2× VIO VtoVIO Outputcurrent VOL = 0.4V 0 1 3 mA (2) VR replaceseitherVRTC orVIO. The followingtabledescribesthedigitaloutputsignaltimingcharacteristics. LOAD (pF) RISE/FALL TIME (ns) BALL NAME/OUTPUT BUFFER MAX MIN NOM MAX CHRG_EXTCHRG_ENZ 35 5 10 15 INT 35 5 10 15 BATREMOVAL 35 5 10 15 NRESPWRON 35 5 10 15 PWM1 35 5 10 15 PWM2 35 5 10 15 REGEN1 35 5 15 25 REGEN2 35 5 15 25 SYSEN 35 5 10 15 5 1 6 20 4 11 VR supplyoutputbuffer 35 5 15 50 8 20 5 1 9 20 3 17 VBAT supplyoutputbuffer 35 5 25 50 6 34 5 5 15 20 8 30CLK32KAO outputbuffer CLK32KG outputbuffer 35 10 45 50 15 100 Copyright© 2010–2011,Texas InstrumentsIncorporated 31

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com OPERATION REAL-TIME CLOCK The RTC isdrivenby the 32-kHz oscillatorand itprovidesthe alarm and timekeepingfunctions.The RTC is suppliedby thebackup battery(when available)ifthemain batteryfailsand ifno externalpower isapplied. The main functionsoftheRTC blockare:

Time information(seconds/minutes/hours)inbinary-codeddecimal(BCD) code
Calendarinformation(day/month/year/dayoftheweek) inBCD code up toyear2099
Programmable interruptsgeneration.The RTC can generatetwo interrupts:a timerinterruptsperiodically (1s/1m/1h/1dperiod)and an alarminterruptata precisetimeoftheday (alarmfunction).The timerinterrupt can be masked duringtheSLEEP periodtopreventthehostprocessorfromwakingup.
Oscillatorfrequencycalibrationand timecorrection
Otherfeaturesare: – Time mode switchingbetween 12 h or 24 h at any timewithoutdisturbingthe RTC (Read or writeare alwaysperformedwiththecurrentmode.) – Shadow registersthatcan storetimeand datecontentand make itavailableand stableforreading For securitypurpose,theregistersrelatedtotimeand calendarinformationareprotectedby restrictingtheirwrite accesstosoftwarerunninginthesecuremode ofthehost(MSECURE). Read accessisalwaysallowedeven in no securedmode. NOTE
IT_ALARM can generatea wake-up oftheplatform.
IT_TIMER cannotgeneratea wake-up oftheplatform. Date and CalendarSettings Allthe timeand calendarinformationare availableinthesededicatedregisters,calledTC registers.The TC registersvaluesarewritteninBCD code. 1. Year datarangesfrom00 to99: – Leap years≈ Yearsdivisibleby 4 (2008,2012,etc.). – Common years= otheryears. 2. Month datarangesfrom01 to12. 3. Day valuerangesfrom: – 1 to31 when months are1,3,5,7,8,10,12 – 1 to30 when months are4,6,9,11 – 1 to29 when month is2 and yearisa leapyear – 1 to28 when month is2 and yearisa common year 4. Week valuerangesfrom0 to6. 5. Hour valuerangesfrom00 to23 in24-hourmode and from1 to12 inAM/PM mode. 6. Minutesvaluerangesfrom0 to59.. 7. Seconds valuerangesfrom0 to59. To modifythe currenttime,softwarewritesthe new timeintoTC registersto fixthe time/calendarinformation (SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEARS_REG, and WEEKS_REG). The DBB can writeintoTC registerswithoutstoppingtheRTC. Inaddition,softwarecan stopthe RTC by clearingthe STOP_RTC bitof the RTC_CRTL_REG controlregisterand check the RUN bitof the RTC_STATUS_REG statusregistertoensurethattheRTC isfrozen.Then updatetheTC values,and restartthe RTC by settingtheSTOP_RTC bit.

32 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 NOTE The 32-kHz second primarycounteris not resetwhen the RTC restartswith the STOP_RTC bit.Therefore,a maximum inaccuracyof1s isstoredintheRTC, depending on theinstantthesecond primarycounterisstopped. Example :Time is10H54M36S PM (AM/PM mode set),2008 September 5.Previousregistersvaluesare: Table3.Real-TimeClock RegistersExample REGISTER VALUE SECONDS_REG 0x36 MINUTES_REG 0x54 HOURS_REG 0x10 DAYS_REG 0x05 MONTHS_REG 0x09 YEARS_REG 0x08 Rounding The usercan round totheclosestminute,by settingtheROUND_30S bitoftheRTC_CTRL_REG register.TC valuesare setto the closestminutevalueat the nextsecond.ROUND_30S bitwillbe automaticallycleared when theroundingtimeisperformed(See calendarregisters,such as SECONDS_REG, MINUTES_REG, etc., and RTC_CTRL_REG). Example :

Ifthecurrenttimeis10H59M45S, roundingchanges thetimeto11H00M00S.
Ifthecurrenttimeis10H59M29S, roundingchanges thetimeto10H59M00S. Get Time The GET_TIME featureloadsthe RTC counterin shadow registersand makes the contentof the shadow registersavailableand stableforreading.Shadowed registers,linkedtotheGET_TIME feature,area parallelset ofcalendarstaticregisters,atthesame I2C addressesas thecalendardynamicregisters.The GET_TIME bitisa self-clearingbit.Once the copy to shadow registersisexecuted,itisresetto 0. Ifthe time isread without GET_TIME, thereadvaluecomes directlyfromtheRTC counterand softwaremust manage thecounterchange duringthe reading.Time readingremainsalways at the same address,withor withoutusingthe GET_TIME feature. Compensation Registers The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registersmust respectthe availableaccess period. These registersmust be updated beforeeach compensationprocess.For example, softwarecan load the compensationvalueintotheseregistersaftereach hourevent,duringan availableaccessperiod. Figure4 shows compensationschedulingfortheRTC. Copyright© 2010–2011,Texas InstrumentsIncorporated 33

Load compensation register Compensation event Load compensation register Compensation event Load compensation register Compensation event Hour event Hours Seconds Hours Seconds Compensation enable 3 4 58 59 0 1 2 58 59 0 1 2 3 4 59 0 1 swcs045-026 TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure4. RTC Compensation Scheduling To compensate forinaccuracyinthe32-kHz oscillator,itispossibletobalancethisdrift.Softwaremust calibrate theoscillatorfrequency,calculatethedriftcompensationversusa 1-hourperiod,and thenloadthecompensation registerswith the driftcompensation value.Ifthe AUTO_COMP bitin RTC_CTRL_REG is enabled,the RTC_COMP_MSB_REG/RTC_COMP_LSB_REG value(in2'scomplement)isadded totheRTC 32-kHz counter ateach hourand 1 second.When RTC_COMP_MSB_REG/RTC_COMP_LSB_REG isadded totheRTC 32-kHz counter,the durationof the currentsecond becomes (32768 – RTC_COMP_M/LSB_REG) / 32768 seconds; therefore,itispossibletocompensate theRTC witha 1/32768-stimeunitaccuracyby hour. NOTE The compensationistakenintoaccountonce writtenintheregisters.When theTWL6030 deviceentersbackup mode, thehostIC must writethepreviouslycorrectcompensation value. Interrupts Table4.RTC Interrupts INTERRUPT DESCRIPTION RTC_ALARM RTC alarmevent:Occursatprogrammed dateand time. RTC periodicevent:Occursatprogrammed periodoftime(eachRTC_PERIOD second orminute,etc.). The RTC can generatetwo typesofinterrupts:

Timer interrupt(RTC_PERIOD) can be generatedperiodically;thatis,each second,minute,hour,or day (RTC_INTERRUPTS_REG EVERY[1:0] bits).This interruptis enabled by the IT_TIMER bit of the RTC_INTERRUPTS_REG interruptsregister.It is a negative edge-sensitiveinterrupt.The RTC_STATUS_REG[5:2] bits(1D_EVENT, 1H_EVENT, 1M_EVENT, 1S_EVENT) are updatedonlyateach new interrupt.They presentwhichtypeofeventsoccur.
Alarm interrupt(RTC_ALARM) can be generated when the time set into the TC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG, ALARM_DAYS_REG, ALARM_MONTHS_REG, ALARM_YEARS_REG) is the same as in the TC registers(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG, YEAR_REG, WEEKS_REG). Thisinterruptis thengeneratediftheIT_ALARM bitoftheRTC_INTERRUPTS_REG interruptsregisterisset.Thisinterruptis

34 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 low-levelsensitive;itindicatesthatan alarminterruptoccurred.Thisinterruptisdisabledby writing1. NOTE

Bothalarm(RTC_ALARM) and timer(RTC_PERIOD) interruptscan occuratthesame time.
Both theprimaryhandlerand RTC IT_ALARM/IT_TIMER bitsmust be cleared;otherwise,they hidenew interruptevents.
Only theRTC alarm(RTC_ALARM) can wake up theTWL6030 device(seetheSTRT_ON_RTC bitinthePHOENIX_START_CONDITION register). CLOCKS The TWL6030 deviceisindependentofany high-frequencysystem clock:Itprovidesonlya 32-kHz clocktothe platform(seeFigure5).The oscillatorcan use an externalcrystalunittogeneratetheclockor use an external 32-kHzoscillator,inwhichcase theinternaloscillatormodule isbypassed. To providea high-performance,32-kHz clockforthe audio device(TWL6040), a dedicatedoutputbufferis implementedon theCLK32KAUDIO ball.Thisaudiobufferuses theVRTC regulatoras an inputsupplysource. The CLK32KAUDIO clockmightnotalwaysbe available,and itsassociatedregisterconfigurationdepends on theplatformrequirements. Higherfrequenciesare requiredforthe differentfunctionsof the TWL6030 deviceand are generatedfrom an internal6-MHz resistor-capacitor(RC) oscillator. Copyright© 2010–2011,Texas InstrumentsIncorporated 35

6 MHz

6 MHz1 MHz32 kHz16 Hz

OCP-CLK(6 MHz) G PADC-CLK(1 MHz) S MPS-CLK(6 MHz CGAUGE-CLK(32 kHz) VIB-CLK(16 Hz) TCK (multiplexer or INT functionalpd) CHG-CLK (3 MHz) SWCS045-027 TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure5. Clock System FunctionalDescription The RC 32-kHz oscillatorprovidestheclockduringthecrystaloscillatorstart-upphase.A 250-ms timerclocked by the32-kHz crystalclockcontrolstheswitchingphase fromRC tocrystaloscillator.The crystalclockstartsin 50 ms maximum. The totalcrystaloscillatorstart-upsequence is lessthan 300 ms. The crystaloscillator incorporatesan analogdetectionmechanism ofthepresenceofthecrystal.When thecrystalisnotvisiblefora nominalperiodof500 µs,thecrystaloscillatorisresetand themultiplexerreselectstheRC 32-kHz input.The TWL6030 deviceisresetwitha power-onreset(POR).A crystalstart-upsequence phase isreinitializedas soon as thecrystalisdetected The RC 6-MHz oscillatorisprincipallyrequiredforthe SMPS and OCP buses.IfallTWL6030 groups are configuredinsleep,theTWL6030 deviceenterstheSLEEP state.IntheSLEEP state,theRC 6-MHz oscillatoris off;otherwise,theRC 6-MHz oscillatorremainsactive.Still,ifrequired,thereissome flexibilitytomaintainthe 6-MHz activewhen theTWL6030 deviceentersSLEEP state. The clockgeneratordeliversthefollowingclocksfromtheRC 6-MHz oscillator:

6 MHz fortheinternalOCP bus
6 MHz fortheseven SMPSs
1 MHz fortheGPADC
32 kHz forthedigitalvibrator

36 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011

16 Hz fortheanalogvibrator The clockgeneratordeliversthefollowingclockfromthe32-kHz multiplexeroutput(RC32K orOSC32K): 32 kHz forthegas gauge. NOTE The 3-MHz chargerclockisdirectlygeneratedinthe chargermodule and not from the common clockgenerator. POWER RESOURCES The power resourcesprovidedby theTWL6030 deviceincludeinductor-basedSMPSs and linearLDO voltage regulators.These supplyresourcesprovidethe requiredpower to the externalprocessorcoresand external components as wellas tothemodules embedded intheTWL6030 device. Short-CircuitProtection The short-circuitcurrentlimitsforallLDOs and SMPS regulatorsembedded in the TWL6030 device are approximatelytwicetheirrespectivemaximum loadcurrent.For specificLDO use cases,when theoutputofthe module isshortedtoground,thepower dissipationcan exceed the1.7-W power dissipationrequirement,ifthere isno continuouspreventiveactionengaged. The short-circuitprotectionscheme compares an LDO/SMPS outputvoltagetoa referencevoltageand detectsa shortcircuitiftheregulatorvoltagedropsslightlybelow itsminimum outputvoltage(1V fortheLDO and 0.55V fortheSMPS). A short-circuitprotectionscheme isincludedineach power resourceoftheTWL6030 deviceto ensure that,ifthe outputof an LDO or SMPS is short-circuited,the power dissipationdoes not increase drastically. AllLDOs/SMPSs includethisshort-circuitprotectionthatmonitorstheregulatoroutputvoltageand generatesan interruptwhen a shortcircuitisdetected(see interruptmapping).The VRTC regulatoristhe unique power resourcethatcannotgeneratean interruptwhen shorted.Therefore,thisregulatorincludesa differentanalog short-circuitmechanism thatdoes notrequirea switchoffoftheregulator. The TWL6030 devicewaitsforthe applicationprocessorto clearthe short-circuitinterruptand turnoffthe associatedpower resourcewithinthe10-ms defaulttime.The short-circuitcounterisconfigurablewith6 EPROM bitsloadedduringthepower-upsequence.The possibleprogrammingrangeis0–640 ms in10-ms steps.Ifthe interruptisnotclearedbeforethecounterexpires,theTWL6030 deviceswitchesoffautomatically.Inparallel,the primarywatchdogcan shutdown thedevice,ifthewatchdogexpires. In normal use conditions,when the TWL6030 device is turned off,allLDO/SMPS resources(except VRTC/VBRTC) are turnedoffand theircorrespondingshort-circuitmechanisms are reset.Ifa short-circuit conditionpersistsinwhichallpower resourcesshouldnormallybe off,theTWL6030 devicedoes notpower up again. SMPS Regulators The TWL6030 deviceincludesseven SMPSs. Three oftheseSMPSs have DVS capabilityand areSmartReflex class3 compatible.These threeSmartReflexSMPSs provideindependentcore voltagedomains to the host processor.The fourremainingSMPSs providesupplyvoltagesforthe hostprocessorI/Os.Each SMPS isa high-frequency,synchronous,step-down DCDC converterallowingthe use of low-costchip inductorsand capacitors. Each SMPS operatesat 6-MHz fixed-switchingfrequencyand entersthe power-savemode operationat light loadcurrentstomaintainhighefficiencyovertheentireloadcurrent.The PFM mode extendsthebatterylifeby reducingthe quiescentcurrentto 30 µA (typical)duringlightloadand standbyoperation.For noise-sensitive applications,therequiredSMPS can be forcedintofixed-frequencyPWM mode. Inshutdown mode, thecurrent consumptionisreducedtolessthan1 µA. Copyright© 2010–2011,Texas InstrumentsIncorporated 37

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Each SMPS is a synchronous step-down converteroperatingwith a 6-MHz, fixed-frequencyPWM at moderate-to-heavyloadcurrents.At lightloadcurrents,theconverteroperatesinpower-savemode withPFM. The converteruses a uniquefrequencylocked-ringoscillatingmodulatortoachievebest-in-classloadand line responseand allowstheuse oftinyinductorsand smallceramicinputand outputcapacitors.At thebeginningof each switchingcycle,theP-channelMOSFET switchisturnedon and theinductorcurrentramps up,raisingthe outputvoltageuntilthemain comparatortrips.The controllogicthenturnsofftheswitch. When a SMPS isnotused,theSMPS inputand ground must stillbe provided(SMPS_IN atVBAT level).The switchingnode SMPS_SW can be leftunconnected,butSMPS_GND and SMPS_FDBK must be tiedtoground. One key advantageofthenonlineararchitectureistheabsence ofa traditionalfeedbackloop.The loopresponse tochange inVO isessentiallyinstantaneous,whichexplainsitsextraordinarytransientresponse.The absence of a traditional,high-gaincompensated linearloopmeans thattheregulatorisinherentlystableovera widerangeof L and CO. Each SMPS integratestwo currentlimits,one in the P-channelMOSFET and anotherin the N-channelMOSFET. When the currentin the P-channelMOSFET reaches itscurrentlimit,the P-channel MOSFET isturnedoffand theN-channelMOSFET isturnedon foratleast150 ns. Withdecreasingloadcurrent,thedeviceautomaticallyswitchesintopulse-skippingoperationinwhichthepower stageoperatesintermittentlybased on loaddemand. By runningcyclesperiodically,the switchinglossesare minimized,and thedevicerunswitha minimum quiescentcurrentand maintaininghighefficiency.The converter willpositionthe DC output voltageapproximately1 percent above the nominal output voltage.This voltage-positioningfeatureminimizesvoltagedrops caused by a sudden loadstep.When inPFM mode, the converterresumes itsoperationwhen theoutputvoltagetripsbelow thenominalvoltage.Itramps up theoutput voltagewitha minimum of threepulsesand goes intoPFM mode when the inductorcurrentreturnto a zero steadystate.Because ofthedynamic voltagepositioning,inPFM mode theaverageoutputvoltageisslightly higherthanitsnominalvalueinPWM mode. DuringPFM operation,theconverteroperatesonlywhen theoutput voltagetripsbelowa setthresholdvoltage.Itramps up theoutputvoltagewithseveralpulsesand goes intoPFM mode when theoutputvoltageexceedsthenominaloutputvoltage. Foreach SMPS, alloutputvoltagescan be selected,regardlesstheexternaldevicesconnectedtothem.Thereis no hardware protectionto preventsoftwarefrom selectingan improperoutputvoltagethatwould damage the relatedexternalequipments.The outputvoltagecodes aredescribedby thefollowingequation. Nominalvoltagevalue= (0.6077V + SMPS_OFFSET bit× 0.1013V)+ (0.01266V × (binaryvalue– 00000001))× (SMPS_MULT bit× 43/21+ 1) (1) An extendedoutputvoltageselectionmode as wellas an offsetapplicationcan be enabledthroughEPROM. The extended outputvoltagecodes withand withoutoffsetapplicationare presentedin Table 7 and in the SMPS_MULT and SMPS_OFFSET registers. The slew rateofvoltagechanges iscontrolledusinga stepregister.For non-SmartReflexsupplies,thevoltage registeris used forvoltageselection(forsupplieshaving programmable outputvoltages).A SmartReflex command does notchange thegroupstate. NOTE

The OFFSET_RW and SMPS_OFFSET bitarepartoftheSMPS_OFFSET register.
The MULT_RW and SMPS_MULT bitarepartoftheSMPS_MULT register.
Binarycode standsfortheSMPS VSEL[5:0]bits.
ThisformulaappliestoallSMPSs, instantiatingthesame IP,forallcodes from000001 to111001.
Fortheremainingcodes,itisspecifieddedicateddiscreteoutputvoltages: – 000000 setstheoutputvoltageto0 V. – 111010 to111110 settheoutputvoltagesintherangeof1.35– 2.1V. – 111111 code isreservedand must notbe used. Table5 liststheSMPS outputvoltageselectioncode instandardmode withoutoffset.

38 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table5.SMPS Output VoltageSelectionCode (StandardMode WithoutOffset) VOUTCODE VOUT (mV) CODE CODE VOUT (mV) CODE VOUT (mV)(mV) 000000 0 010000 797.6 100000 1000.2 110000 1202.7 000001 607.7 010001 810.3 100001 1012.8 110001 1215.4 000010 620.4 010010 822.9 100010 1025.5 110010 1228.0 000011 633.0 010011 835.6 100011 1038.1 110011 1240.7 000100 645.7 010100 848.2 100100 1050.8 110100 1253.4 000101 658.3 010101 860.0 100101 1063.5 110101 1266.0 000110 671.0 010110 873.6 100110 1076.1 110110 1278.7 000111 683.7 010111 886.2 100111 1088.8 110111 1291.3 001000 696.3 011000 898.92 101000 1101.4 111000 1304.0 001001 709.0 011001 911.5 101001 1114.1 111001 1316.7 001010 721.6 011010 924.2 101010 1126.8 111010 1367.4 001011 734.3 011011 936.9 101011 1139.4 111011 1519.3 001100 747.0 011100 949.5 101100 1152.1 111100 1823.1 001101 759.6 011101 962.2 101101 1164.7 111101 1924.4 001110 772.3 011110 974.8 101110 1177.4 111110 2127.0 001111 785.0 011111 987.5 101111 1190.1 111111 Reserved NOTE

The VOUT valueslistedin thistablerepresentnominal voltages.The totaloutput accuracyis–4.1% (±3.8%).
0.600– 1.300V voltagestepsarenormallyused by theSmartReflexSMPS.
SMPS can be configuredtoany outputselectioncode,withoutrestriction. The offsetapplicationfeaturecan be unlockedby an EPROM bitand inthiscase theoutputvoltagevaluesare as describedinTable6: Table6.SMPS Output VoltageSelectionCode (StandardMode With Offset) VOUTCODE VOUT (mV) CODE CODE VOUT (mV) CODE VOUT (mV)(mV) 000000 0 010000 898.9 100000 1101.5 110000 1304.0 000001 709.0 010001 911.6 100001 1114.1 110001 1316.7 000010 721.7 010010 924.2 100010 1126.8 110010 1329.3 000011 734.3 010011 936.9 100011 1139.4 110011 1342.0 000100 747.0 010100 949.5 100100 1152.1 110100 1354.7 000101 759.6 010101 962.2 100101 1164.8 110101 1367.3 000110 772.3 010110 974.9 100110 1177.4 110110 1380.0 000111 785.0 010111 987.5 100111 1190.1 110111 1392.6 001000 797.6 011000 1000.2 101000 1202.7 111000 1405.3 001001 810.3 011001 1012.8 101001 1215.4 111001 1418.0 001010 822.9 011010 1025.5 101010 1228.1 111010 1367.4 001011 835.6 011011 1038.2 101011 1240.7 111011 1519.3 001100 848.3 011100 1050.8 101100 1253.4 111100 1823.1 001101 860.9 011101 1063.5 101101 1266.0 111101 1924.4 001110 873.6 011110 1076.1 101110 1278.7 111110 2127.0 001111 886.2 011111 1088.8 101111 1291.4 111111 Reserved Copyright© 2010–2011,Texas InstrumentsIncorporated 39

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com An EPROM bitunlockstheextendedoutputvoltagefeature,as listedinTable7.Inthismode, theSMPS voltage levelstepis38.1 mV. Some trimmingadjustmentscan shiftthoselevelsup or down by one or two settings, meaning ±9.5 mV or 19.05 mV. The resistordividerratiois 21/64 versus the originalconfigurationset (SMPS_MULT). Table7.SMPS Output VoltageSelectionCode (ExtendedMode WithoutOffset) CODE VOUT (V) CODE VOUT (V) CODE VOUT (V) CODE VOUT (V) 000000 0 010000 2.431 100000 3.048 110000 3.665 000001 1.852 010001 2.469 100001 3.087 110001 3.704 000010 1.891 010010 2.508 100010 3.125 110010 3.743 000011 1.929 010011 2.547 100011 3.164 110011 3.781 000100 1.968 010100 2.585 100100 3.202 110100 3.820 000101 2.006 010101 2.624 100101 3.242 110101 3.858 000110 2.045 010110 2.662 100110 3.280 110110 3.897 000111 2.084 010111 2.701 100111 3.318 110111 3.936 001000 2.122 011000 2.739 101000 3.357 111000 3.974 001001 2.161 011001 2.778 101001 3.395 111001 4.013 001010 2.199 011010 2.817 101010 3.434 111010 2.084 001011 2,238 011011 2.855 101011 3.473 111011 2.315 001100 2.276 011100 2.894 101100 3.511 111100 2.778 001101 2.315 011101 2.932 101101 3.550 111101 2.932 001110 2.354 011110 2.971 101110 3.588 111110 3.241 001111 2.392 011111 3.010 101111 3.627 111111 Reserved NOTE The VOUT valueslistedinTable8 representnominalvoltages.The totaloutputaccuracy is–4.1% (±3.8%). Table8.SMPS Output VoltageSelectionCode (ExtendedMode With Offset) CODE VOUT (V) CODE VOUT (V) CODE VOUT (V) CODE VOUT (V) 000000 0 010000 2.739 100000 3.357 110000 3.974 000001 2.161 010001 2.778 100001 3.395 110001 4.013 000010 2.199 010010 2.817 100010 3.434 110010 4.051 000011 2.238 010011 2.855 100011 3.473 110011 4.090 000100 2.277 010100 2.894 100100 3.511 110100 4.128 000101 2.315 010101 2.932 100101 3.550 110101 4.167 000110 2.354 010110 2.971 100110 3.588 110110 4.206 000111 2.392 010111 3.010 100111 3.627 110111 4.244 001000 2.431 011000 3.048 101000 3.665 111000 4.283 001001 2.469 011001 3.087 101001 3.704 111001 4.321 001010 2.508 011010 3.125 101010 3.743 111010 4.167 001011 2.547 011011 3.164 101011 3.781 111011 2.315 001100 2.585 011100 3.202 101100 3.820 111100 2.778 001101 2.624 011101 3.241 101101 3.858 111101 2.932 001110 2.662 011110 3.280 101110 3.897 111110 3.241 001111 2.701 011111 3.318 101111 3.936 111111 Reserved

40 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 SoftStart Each SMPS has an internalsoft-startcircuitthatlimitstheinrushcurrentduringstartup.Thislimitsinputvoltage dropswhen a batteryora high-impedancepower sourceisconnectedtotheinputoftheconverter.The soft-start system progressivelyincreasesthe ON-time from a minimum pulse-widthof 30 ns as a functionof the output voltage.This mode of operationcontinuesfor140 µs afterenable.Ifthe outputvoltagedoes not reach its targetedvalueby thistime,such as inthe case of heavy load,the soft-starttransitionsto a second mode of operation.The converterthenoperatesina current-limitmode, specificallytheP-MOS currentlimitissettohalf thenominallimitand theN-channelMOSET remainson untiltheinductorcurrentisreset.Afteran additional100 µs,thedeviceramps up tofullcurrentlimitoperation,providingtheoutputvoltagerisesabove approximately0.7 V.Therefore,thestart-uptimedepends primarilyon theoutputcapacitorand loadcurrent. InductorSelection Allstep-downconvertersare designedtooperatewithan effectiveinductancevaluefrom 0.30to1.30µH and withoutputcapacitorsfrom4 to15 µF.The outputcapacitormaximum valueisnormallyused duringthestart-up phase,when the capacitorisstillunbiased.The internalcompensationisoptimizedto operatewithan output filterofL = 1 µH and CO = 10 µF.Largerorsmallerinductorvaluescan be used tooptimizetheperformanceof thedeviceforspecificoperationconditions. The inductorvalueaffectsthefollowing:

Peak-to-peakripplecurrent
PWM-to-PFM transitionpoint
Outputvoltageripple
Efficiency The selectedinductormust be ratedforitsDC resistanceand saturationcurrent.The ripplecurrentof the inductordecreaseswithhigherinductanceand increaseswithhigherVIorVO. Inhigh-frequencyconverterapplications,theefficiencyismostlyaffectedby theinductorAC resistance(quality factor)and,toa smallerextent,by theinductorDCR value.To achievehigh-efficiencyoperation,specialcare must be takentoselectinductorsfeaturinga qualityfactorabove 20 attheswitchingfrequency.Increasingthe inductorvalueproduceslowerRMS currents,butdegradesthetransientresponse.For a givenphysicalinductor size,increasedinductanceusuallyresultsinan inductorwithlowersaturationcurrent. The totallossesofthecoilconsistofboththelossesintheDC resistanceand thefollowingfrequency-dependent components:
The lossesinthecorematerial(magnetichysteresisloss,especiallyathighswitchingfrequencies)
Additionallossesintheconductorfromtheskineffect(currentdisplacementathighfrequencies)
Magneticfieldlossesoftheneighboringwindings(proximityeffect)
Radiationlosses Output CapacitorSelection SMPS advanced fast-responsevoltagemode controlallowsthe use of tinyceramic capacitors.Ceramic capacitors,withlow ESR values,providethelowestoutputvoltageripple.The outputcapacitorrequireseitheran X7R oran X5R dielectric. NOTE Aside from theirwide variationincapacitanceovertemperature,Y5V and Z5U dielectric capacitorsbecome resistiveathighfrequencies. Atnominalloadcurrent,thedeviceoperatesinPWM mode and theoveralloutputvoltagerippleisthesum ofthe voltagestepcaused by the outputcapacitorESL and the ripplecurrentflowingthroughthe outputcapacitor reactance. At lightloads,thedeviceoperatesinpower-savemode and theoutputvoltagerippleisindependentoftheoutput capacitorvalue.The outputvoltagerippleissetby theinternalcomparatorthresholdsand propagationdelays. Copyright© 2010–2011,Texas InstrumentsIncorporated 41

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com InputCapacitorSelection Because thebuck converterhas a pulsatinginputcurrent,a low ESR inputcapacitormust preventlargevoltage transientsthatcan cause misbehaviorofthedeviceorinterferenceswithothercircuitsinthesystem.Althougha 2.2-µF capacitorissufficientformost applications,a 4.7-µF capacitorisrecommended toimproveinputnoise filtering. CAUTION Exercisecautionwhen usingceramicinputcapacitors.When a ceramiccapacitoris used attheinputand thepower isbeingsuppliedthroughlongwires,such as froma walladapter,a loadstepattheoutputcan induceringingattheVIN pin.Thisringing can coupletotheoutputand can be mistakenas loopinstabilityor even damage the part.Inthiscircumstance,additionalbulkcapacitance(electrolyticortantalum)must be placed between CI and the power source lead to reduce ringingthatcan occur between theinductanceofthepower sourceleadsand CI. VCORE1, VCORE2, VCORE3 The TWL6030 deviceincludesthreeSMPS converters(VCORE1, VCORE2, and VCORE3) intendedtoprovide threeindependentcore voltagedomains to the hostprocessor.AllthreeSMPSs are buck converterswitha configurableoutputvoltage.Defaultoutputvoltageat power up is 0.95 V (EPROM settings).These three convertersare SmartReflexclass3 compliant;theiroutputvoltagesare independentlycontrolledusing the SmartReflexI2C dedicatedinterface(SR-I2C)orcontrolI2C (CTL-I2C)thruregisters. VMEM The TWL6030 deviceincludesan SMPS buck converterVMEM dedicatedtomemory supply.For example,the outputvoltageofthisSMPS can be 1.8V,1.35V,or1.2V. V2V1 One SMPS V2V1 isdedicatedtostepthebatteryvoltagedown toa preregulatedvoltageofeither1.8V or2.1V, essentiallytosupplytheTWL6040 (audio)devicebutalsoas an inputforsome LDOs (forexample,VCXIO and VDAC) toimproveoverallplatformpower efficiency. V1V29, V1V8 V1V29 operatesata fixedoutputvoltagetosupplyan externalmodem or an RF transceiverand/or1.2-VI/Os. V1V8 SMPS isdedicatedtoa 1.8-Vgeneral-purposesupply(standardI/Os,externalperipheral,etc.). When used as system1.8-VI/Os,theTWL6030 deviceI/Osupply(VIOball)must be connectedtoV1V8. LDO REGULATORS AllLDOs are integratedso thattheycan be connectedto an internalpreregulator,to an externalbuck boost SMPS, ortoanotherpreregulatedvoltagesource. AllLDOs outputvoltagescan be selected,regardlessoftheLDO inputvoltagelevelVIN.There isno hardware protectiontopreventsoftwarefrom selectingan improperoutputvoltageiftheVIN minimum levelislowerthan TDCOV (totalDC outputvoltage)+ D V (dropoutvoltage).Insuch conditions,theoutputvoltagewouldbe lowerand nearlyequaltotheinputsupply.Forexample,inelectricaltables,onlythepossibleinputsupplies,whichfulfillthe electricalperformancesinalltheirranges,arementionedateach selectedoutput.Softwaremust notselectthe 2.5-VoutputvoltageiftheVBAT supplyisused as theinputvoltageand VBAT islowerthanTDCOV + D V. The regulatoroutputvoltagecannotbe modifiedon thefly,fromthe1.0–2.1V voltagerangetotheother2.2–3.3 V voltagerangeand viceversa.The regulatormust be restartedinthesecases. Ifan LDO isnotneeded and notturned-onby softwareor a switch-onsequence,theexternalcomponents can be removed.The TWL6030 deviceisnotdamaged by thisconfiguration,and theotherfunctionsdo notdepend on theunmounted LDOs and continuetowork.

42 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 LDOs are controlledby I2C access and theiroutputvoltagecan be selectedina wide range of values.The followingequationdescribestherelationshipbetween theLDO outputvoltageand theregistervalue. Absolutevoltagevalue= 1.0V + 0.1V × (binaryvalue– 00000001) (2) NOTE

This formulaappliesto allgeneral-purposesLDOs, forallcodes from 00000001 to 00011000.
Fortheremainingcodes,itisspecifieddedicatedoutputvoltages: – 00000000 setstheoutputvoltageto0 V. – 00011001 to00011110 codes arereserved. – 00011111 code setstheoutputvoltagesat2.75V. Table9.LDO Output VoltageSelectionCode CODE VOUT (V) CODE VOUT (V) CODE VOUT (V) CODE VOUT (V) 00000000 0 00001000 1.7 00010000 2.5 00011000 3.3 00000001 1.0 00001001 1.8 00010001 2.6 00011001 Reserved 00000010 1.1 00001010 1.9 00010010 2.7 00011010 Reserved 00000011 1.2 00001011 2.0 00010011 2.8 00011011 Reserved 00000100 1.3 00001100 2.1 00010100 2.9 00011100 Reserved 00000101 1.4 00001101 2.2 00010101 3.0 00011101 Reserved 00000110 1.5 00001110 2.3 00010110 3.1 00011110 Reserved 00000111 1.6 00001111 2.4 00010111 3.2 00011111 2.75 NOTE
Depending on theoutputvoltageselectioncode selected,thecoresectionoftheLDO issuppliedeitherby theVBAT level(associatedVDD_B# ball)orby theLDO_IN input supply
For allcodes intherangeof[1.0-2.1]V,theVBAT batterylevelisused tosupplythe LDO coresection
For allothercodes,from2.2V up to3.3V,theLDO_IN power sourceisused tosupply theLDO coresection
When SoftwaredisablestheLDO, theregulatordoes notpresentany leakage,even if thereis0V attheLDO_IN inputsupplyballand theoutputvoltageselectedis≥ 2.2V
DisablingtheLDO does notinteracton thecoresupplyswitchselection,onlylinkedto theoutputvoltagecode
The outputvoltageselection,whichalsoaffectsthecoresupplyswitchcontrol,has to be programmed beforetheregulatorturnon event
The regulatoroutputvoltagecannotbe modifiedon thefly,fromthe[1.0-2.1]Vvoltage range to the other[2.2- 3.3]Vvoltagerange and vice-versa.The regulatormust be restarted
TWL6030 does notpreventSW forenablingtheLDO, even iftheLDO_IN inputsupply isnotpresent VANA The VANA voltageregulatorisdedicatedto supplythe analogfunctionsof the TWL6030 device,such as the GPADC, gas gauge,and otheranalogcircuitry. VANA can be enabledand disabledindividuallyor when associatedwitha power group.Thispower resource controloptimizestheoverallSLEEP statecurrentconsumption.Thisregulatorcan be used atplatformlevelto supplyotherapplications,providedtheydo notgeneratenoisetothesupplylineand themaximum currentisless than15 mA. Copyright© 2010–2011,Texas InstrumentsIncorporated 43

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com VRTC The VRTC regulatorsuppliesalways-onfunctions,such as RTC and wake-up functions.Thispower resourceis activeas soon as a validenergysourceispresent. Thisresourcehas two modes:

Normal mode when suppliedfrommain batteryand abletosupplyalldigitalpartoftheTWL6030
Backup mode when suppliedfrom eithera backup batteryor a main batteryand able to supplyonly always-onparts VRTC suppliesthedigitalpartoftheTWL6030 device.InBACKUP state,theVRTC regulatorisinlow-power mode (VBRTC) and issuppliedfroma backup batteryormain battery;thedigitalactivityisreducedtotheRTC partsonlyand maintainedinretentionregistersofthebackup domain.The restofthedigitalisunderresetand theclocksaregated. InWAIT-ON state,theturn-oneventsand detectionmechanism arealsoadded tothepreviousRTC currentload and stillsuppliedon VRTC orVBRTC. InACTIVE state,VRTC switchesautomaticallyintoACTIVE state(insideanalogbackup batteryIP).The resetis releasedand theclocksareavailable. InSLEEP state,VRTC iskeptactive.The resetisreleasedand onlythe32-kHzclockisavailable.Still,toreduce power consumption,VBRTC can be used insteadofVRTC. VAUX1, VAUX2, VAUX3, VMMC, VUSIM The VMMC LDO isa programmable linearvoltageconverterused topower a multimediacard(MMC) slot.On top of the normal controlby the power controller,itcan be turnedoffwhen card removal isdetected(the VMMC_AUTO_OFF bitintheMMCCTRL register).VMMC isbased on thesame GPLDO architectureas theone used fortheVAUX regulators. VoltageregulatorVUSIM isdedicatedtosupplyremovableUSIM memory. Inadditiontothenormalcontrolby the power controller,itcan be turnedoffwhen card removal isdetected(theVSIM_AUTO_OFF bitin the SIMCTRL register). The TWL6030 device includesthreegeneral-purposeresources(VAUX1, VAUX2, and VAUX3) to supply externalperipherals,such as camera sensors,displaydrivers,memories (embedded multimediacards[eMMCs]), and others.When notused as a supply,VAUX3 can delivera PWM supplytodrivea vibratormotor. VCXIO, VDAC, VPP, VUSB The VCXIO and VDAC regulatorssupplynoise-sensitivefunctions;forexample,theVCXIO suppliesthePLLs and MIPI® D-PHY; and VDAC can be used to supplythe videoDAC. Both LDOs can be preregulatedby the V2V1 SMPS. VUSB suppliestheUSB PHY fromthePMID node oftheUSB chargerorfrombattery. VPP suppliesthehostprocessoreFuse circuitry.The defaultvalueis1.9V outputsupply. BACKUP BATTERY CHARGER The TWL6030 deviceprovidesa backup mode inwhich a backup batteryisused topower theRTC and other secure registerswhen no otherenergy source is available.The backup batteryis optionaland can be nonrechargeableor rechargeable.The rechargeablebatterycan be charged from the main batteryusingthe backup batterycharger. The backup batterychargerincludestwo controlloops(CC/CV).A currentlooplimitsthechargingcurrentwhen backup batteryvoltageislow and a voltageloopthatgraduallyreducesthechargingcurrentas backup battery voltageapproaches itsfinalvalue.The charge currentlimitis fixedand the end of charge voltageis programmable. The backup batterychargerisenabledby softwareand thechargingstartsifthemain batteryvoltageis100 mV above backup batteryvoltage;chargingisstoppedwhen backup batteryvoltageequalseithertheselectedend of thechargevoltagelevelorthemain batteryvoltage,ifitisbelow theend ofthechargelevelprogrammed. The backup batterycharge cannot startifmain batteryvoltageislowerthan VBATMIN_LO. The backup battery switchcontrolswhen thesystementersinbackup mode (suppliedby thebackup battery).

44 Copyright© 2010–2011,Texas InstrumentsIncorporated

I_lim VBA T VBACKUP Voltage selection Vref TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Figure6 shows a blockdiagramofthebackup batterycharger. Figure6. Block Diagram oftheBackup BatteryCharger POWER MANAGEMENT The power-management system can independentlydrivethe power stateof threedifferentsubsystems or a combinationofthethree.The power-management state-machinemanages thestateofthedifferentresources includedintheTWL6030 devicedependingon system activityand energyavailability.Itensuresthedetectionof externalor internaltriggeringevents thatinitiatea change of system power state.Itcontrolsthe transition sequences requiredto change the system from currentpower stateto a new power stateby configuringthe resourcesaccordingtothedesiredfinalpower state.Configurationregistersare accessiblethroughapplication software by the general-purposeI2C interface(CTL-I2C).Figure 7 shows a block diagram of the power-management system. Copyright© 2010–2011,Texas InstrumentsIncorporated 45

SR_SDA SR_SCLK FSM Phoenix group Commands controller APE group Modem group Periph group Software commands I C control2 SDA SCLK VAC_DET VBUS_DET THERM_DET MBAT_PLUG BBAT_PLUG NRESWARM Sequence tables Sequence arbitration Hardware groups commands BOOT[3:0] PREQ3PREQ2CPREQ2BPREQ2A PREQ1 TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure7. Power Management Architecture

46 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Resources A resourceisan elementthatprovidestherequirementstoa system orsubsystemtooperate.Typicalresources aresupplies,clocks,resets,references,and bias.Each resourcecan be addressedwithitsuniqueI2C address orwiththeI2C-sharedaddresses(broadcast). Two configurableattributescan be associatedtoeach resource:

A subsystemgroupattribute(GRP) specifyingtowhichsubsystemgrouptheresourceisassociated
A resource categoryattribute(CAT) specifiesthe categoryof the resource among power-providers, power-referencesorclocks,resets,and comparators.Thisattributeishardcoded. Each resourcecan be associatedto one or more subsystems.Resource attributescan be hard coded or configurable.The stateofeach grouptowhichtheresourcebelongsisstoredinthegroupstateregister.A state arbitrationismade todefinethecurrentstateofsharedresources.The resourcestateversusgroupstatecan be remapped.Forexample,a resourcecan be setON orOFF when thegroupstateisSLEEP. Table10 liststhedifferentresourceoperatingmodes. Table10.Resource OperatingModes RESOURCE MODE Power on OFF: Disabled AUTO: Enabled,adaptstoloadcurrent FORCE: Forcedtoactivemode REGEN1/REGEN2/SYSEN signals DISABLE: Logiclow ENABLE: Logichigh SMPS regulators OFF: Disabled AUTO: Enabled(PFM/PWM operation) FORCED PWM: Enabled,forcedtooperateinPWM mode Main band gap OFF: Disabled ON ACCURATE: Enabled,highon accuracy LOW POWER: Enabled,loweraccuracy,lowpower FAST: Enabled,filteringbypassed(usedonlyduringBOOT or WAKEUP) Comparators OFF: Disabled ON: Enabled Thermalshutdown ACTIVE: Enabled OFF: Disabled System reset ACTIVE: NRESPWRON signalactive(logichigh) RELEASED: NRESPWRON signalinactive(logiclow) Clocksand PWM1/PWM2 drivers DISABLE: Signaldeliveryisgated. ACTIVE: Signalisdelivered. Configurationregistersareintendedforresourceconfiguration,whilestateregistersareintendedtomanage the resourcestatetransition;finally,SmartReflexregistersare intendedtoprovidedynamic voltagecontrolthrough the SR-I2C. Configurationand stateregisterscontributeto determineresourcebehavior.The stateregister definesto which statethe resourcemust switchand the timingforthe transition.The configurationregister definestheresourcebehaviorina definedstate.Althoughbothtypesofregisterscan be accessedby theFSM and the CTL-I2C,itispreferableto reserveI2C access to configurationregistersand FSM access to state registers.SmartReflexregistersare accessed exclusivelythroughtheSR-I2C inapplicationsusingSmartReflex capability. These registerscan be accessedindifferentways:individualaccessallowstheregisterstobe accessedthrough theirphysicaladdress(ID),and broadcastmessages are interpretedby individualresourcesinfunctionoftheir configuration. Copyright© 2010–2011,Texas InstrumentsIncorporated 47

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Groups Group Definition The ensemble ofresourcesassociatedwitha subsystemisa group.A subsystemisan enginerunninga specific applicationinan independentway.IntheTWL6030 device,fourgroupsaredefined:one foreach subsystemand one forthedeviceitself:

Group 1:Applicationprocessorgroup(APP)
Group 2:Peripheralsgroup—connectivitydevices(CON)
Group 3:Cellularmodem group(MOD)
Group 4:Phoenixpower devicegroup The power resourcescan be allocatedto any of the fourgroups by hardware or software,dependingon the resources. NOTE
The Phoenixpower devicegroup(group4)includestheresourcescommon toallothergroups. Group 4 isnotconsidereda groupby itself,as aregroups1,2,and 3,withalloftheassociated registerbits.
Ifa resourceisnotused,itmust be unassignedfromitsdefaultassociatedgroups.
A SLEEP-to-ACTIVE transitionwakes up allassignedresourcesofa group.
ModifyingthedefaultvalueoftheCFG_TRANS registerallowsa specificresourceofone group toactdifferentlyfromtheotherresourcesofthesame group. Table11.Groups and Resources Association RESOURCE GROUP1 (APP) GROUP2 (CON) GROUP3 (MOD) GROUP4 (PHOENIX) SMPS REGULATOR RESOURCES V1V29 Yes (software) Yes (software) Yes (software) V1V8 Yes (software) Yes (software) Yes (software) V2V1 Yes (software) Yes (software) Yes (software) VCORE1 Yes (software) Yes (software) Yes (software) VCORE2 Yes (software) Yes (software) Yes (software) VCORE3 Yes (software) Yes (software) Yes (software) VMEM Yes (software) Yes (software) Yes (software) LDO REGULATOR RESOURCES VANA Yes (hardware) VAUX1 Yes (software) Yes (software) Yes (software) VAUX2 Yes (software) Yes (software) Yes (software) VAUX3 Yes (software) Yes (software) Yes (software) VCXIO Yes (software) Yes (software) Yes (software) VDAC Yes (software) Yes (software) Yes (software) VMMC Yes (software) Yes (software) Yes (software) VPP Yes (software) Yes (software) Yes (software) VRTC Yes (hardware) VUSB Yes (software) Yes (software) Yes (software) VUSIM Yes (software) Yes (software) Yes (software) CLOCK RESOURCES CLK32DAO Yes (hardware) CLK32KG Yes (software) Yes (software) Yes (software) CLK32KAUDIO Yes (software) Yes (software) Yes (software) Clockresources

48 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table11.Groups and Resources Association(continued) RESOURCE GROUP1 (APP) GROUP2 (CON) GROUP3 (MOD) GROUP4 (PHOENIX) OTHER EXTERNAL CONTROLLED RESOURCES REGEN1 Yes (software) Yes (software) Yes (software) REGEN2 Yes (software) Yes (software) Yes (software) SYSEN Yes (software) Yes (software) Yes (software) INTERNAL RESOURCES NRESPWRON Yes (hardware) BIAS Yes (hardware) RC6MHZ Yes (hardware) TMP Yes (hardware) VBATMIN_HI Yes (software) Yes (software) Yes (software) Power StatesofGroups and Subsystem Groups

NO SUPPLY state(Phoenixgrouponly): – Description:The systemisnotpowered by any energysource. – Condition:VUPR > VPOR
BACKUP state(Phoenixgrouponly): – Description:The systemispowered onlyby a backup battery. – Activity:Minimum supplyisavailabletomaintainonlythekeep-alivefunctionsinthePhoenixpower device group,such as RTC and othercriticaldataregistersand no otheractivityinthesystem.
WAIT-ON/OFF state(Phoenixgroupand subsystemgroups): – Description:The systemispowered by a validenergysource. – Activity:Minimum supplyisavailabletomaintainonlythekeep-alivesupplyfortheRTC and othercritical data registers.Power-management controllerresetis releasedand the Phoenix power devicegroup acceptsand treatstriggeringevents(WAIT-ON);allothergroupsareintheOFF state.
ACTIVE state(allgroups): – Description:The systemispowered by a validenergysource. – Activity:The Phoenixgroup isACTIVE. The resourcesrequiredforthegroup runningtheapplicationare enabledand therequiredpower suppliesare activefullcurrentcapable(theothergroupscan remainin SLEEP orOFF state).The systemresetisreleased.
SLEEP state(allgroups): – Description:The system ispowered by a validenergysource.The Phoenixpower devicegroupswitches toSLEEP statewhen allothergroupsareinSLEEP state. – Activity:Resources associatedwiththe group are configuredin low-powermode to maintaingroup context. NO SUPPLY and BACKUP areglobalstates;thatis,theycorrespondtoa uniquestateofthepower resources. ACTIVE, WAIT-ON, and SLEEP are not globalstatesand can be dividedin substates;each substate correspondstoa differentstateconfigurationofthepower resources. Transitionsfrom the currentpower stateto the nextpower stateare initiatedby triggeringevents.Triggering eventscan resultfrom useraction,system activity,or a change inenvironmentalconditions.Triggeringevents areenabledordisabled,dependingon thetriggeringconditions. Subsystem Hardware Commands Partial-onor partial-offeventscoming from subsystems (ACTIVE or SLEEP) are transmittedto the TWL6030 device using hardware signals(PREQ1, PREQ2A, PREQ2B, PREQ2C, PREQ3). The FSM conveys this informationtotheresourcesofthesubsystem group toseteach resourceina statebased on thesubsystem state. Each subsystemisassociatedwithatleastone hardwaresignal:
Group 1:Applicationprocessorgroup(APP) → PREQ1 Copyright© 2010–2011,Texas InstrumentsIncorporated 49

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com

Group 2: Peripheralsgroup—connectivitydevices(CON) → LogicalOR between PREQ2A, PREQ2B, and PREQ2C
Group 3:Cellularmodem group(MOD) → PREQ3 PREQ signalscan be masked by registerbitsPREQ2A, PREQ2B, and PREQ2C sharingthe same mask bit. PREQ1, PREQ2A, PREQ2B, PREQ2C, and PREQ3 are suppliedon the VIO voltagedomain. The default polarityofthesignalsisactivehigh(groupisactive)and itcan be selectedby theregisterbit. SmartReflexSoftwareCommands Only SMPS SmartReflex-compliantresourcescan be accessed by the SR-I2C. In additionto hardware commands, SmartReflex-compliantpower resourcesreceiveadditionalcommands with the SR-I2C. These commands affectthevoltagesettingoftheSMPS, dependingon therelatedvoltagedomain state.The slewrate ofvoltagechanges iscontrolledwitha stepregister.For non-SmartReflexsupplies,thevoltageregisterisused forvoltageselection(forsupplieshavingprogrammable outputvoltages).A SmartReflexcommand does not change thestateofthegroup. Boot Pins The TWL6030 devicehas fourinputballs(Boot[3:0])toselectbootsequence executedatstartup.These balls providean indicationon thefollowingparameterstoselectthecorrectvalueforthesupplyvoltagesand detection thresholds:
BOOT0: Batterychemistry(cut-offvoltage)
BOOT1: LPDDR2 (voltage/sequence)
BOOT2: eMMC (voltage)
BOOT3: Platform(sequence) Table12.BOOT[3:0] BOOT STATE EFFECT Highthresholdsareselectedfor0 VBATMIN_LO and VBATMIN_HI. BOOT0 Low thresholdsareselectedfor1 VBATMIN_LO and VBATMIN_HI. OMAP4430 PMIC: S4A LPDDR2 memories areused.VMEM suppliestheLPDDR2 core at1.35V.0 OMAP4460/4470 PMIC: VMEM isnot controlledby startupsequence. BOOT1 OMAP4430 PMIC: S4B LPDDR2 memories areused.VMEM suppliestheLPDDR2 core at1.2V.1 OMAP4460/4470 PMIC: VMEM isturnedON by startupsequence.Outputvoltageis1.2V 0 VAUX1 isused tosupplyeMMC at2.8V. BOOT2 1 VAUX1 isused tosupplyeMMC at1.8V. VAUX1 isdisabledduringpower-up0 sequence (pulldownasserted). VAUX1 isenabledduringpower-upBOOT3 sequence (BOOT2 configuringthevoltage).1 Forexample,see theOMAP4 power-up sequence. NOTE
OMAP4430 PMIC partnumbers areTWL6030B107, TWL6030B1AE, and TWL6030B1A0.
OMAP4460/4470 PMIC partnumbers areTWL6030B1A4, TWL6030B1AF, and TWL6030B1AA. BatteryComparator Thresholds Threethresholdsofbatteryvoltageconditionthesystemstatetransitions:

50 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011

POR – Releasedwhen theenergysourcecan supplythedigitalresources – POR thresholdistheminimum voltagebelowwhichtheTWL6030 deviceisreset.
VBATMIN_LO – Thresholdofhardwareswitch-off – Two values,dependingon thebatterytechnology,arestoredinEPROM and selectedby bootmode. – The comparatorfalling-edgethreshold(VBATMIN_LO) isconfigurablefrom 2.00 to 3.100 V in 50-mV steps. – The equivalentcomparatorhysteresisrangeisfrom150 to500 mV.
VBATMIN_HI – Thresholdofswitch-on – Checked as conditiontoinitiateany sequence toACTIVE state – Two values,dependingon thebatterytechnology,arestoredinEPROM and selectedby bootmode. – The comparatorrising-edgethreshold(VBATMIN_HI) isconfigurablefrom2.50to3.55V in50-mV steps. – The equivalentcomparatorhysteresisrangeisfrom150 to500 mV. – For correctsystem behavior,theVBATMIN_HI thresholdvaluemust notbe programmed higherthanthe defaultchargingvoltage.Otherwise,the TWL6030 devicedoes not switchon aftera chargerplugwith empty battery. Depending on thebatterytechnologyused,thePhoenixpower devicemust be configuredappropriatelywiththe batterychemistryBOOT pin.The correspondingEPROM bitsof the main batterycomparatorsthresholdsare loadedduringthePhoenixpower devicestart-upsequence:
The comparatorrisingedge threshold(VBATMIN_HI) isconfigurablefrom2.50to3.550V in50-mV steps.
The comparatorfallingedge threshold(VBATMIN_LO) isconfigurablefrom2.00to3.100V in50-mV steps.
The equivalentcomparatorhysteresisrangeisthusfrom150 to500 mV in50-mV steps. The EPROM bitsstoredare:
Risingedge 16-stepcode forthecurrentbatterygeneration(6bits)
Risingedge 16-stepcode forthenextbatterygeneration(6bits)
Fallingedge 23-stepcode forthecurrentbatterygeneration(6bits)
Fallingedge 23-stepcode forthenextbatterygeneration(6bits) Table13 liststheparametersfortherisingedge oftheVBATMIN_HI threshold. Table13.VBATMIN_HI Threshold PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltagethreshold <001010> 2.460 2.500 2.580 V Voltagethreshold <001011> 2.510 2.550 2.630 V Voltagethreshold <001100> 2.560 2.600 2.680 V Voltagethreshold <001101> 2.610 2.650 2.730 V Voltagethreshold <001110> 2.655 2.700 2.785 V Voltagethreshold <001111> 2.705 2.750 2.835 V Voltagethreshold <010000> 2.755 2.800 2.885 V Voltagethreshold <010001> 2.805 2.850 2.940 V Voltagethreshold <010010> 2.855 2.900 2.990 V Voltagethreshold <010011> 2.905 2.950 3.040 V Voltagethreshold <010100> 2.955 3.000 3.090 V Voltagethreshold <010101> 3.000 3.050 3.145 V Voltagethreshold <010110> 3.050 3.100 3.195 V Voltagethreshold <010111> 3.100 3.150 3.245 V Voltagethreshold <011000> 3.150 3.200 3.300 V Voltagethreshold <011001> 3.200 3.250 3.350 V Copyright© 2010–2011,Texas InstrumentsIncorporated 51

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Table13.VBATMIN_HI Threshold(continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltagethreshold <011010> 3.250 3.300 3.400 V Voltagethreshold <011011> 3.295 3.445 3.455 V NOTE

Minimum valuesaredefinedat–[1.50,1.75]%ofthenominalvalue.
Maximum valuesaredefinedat+[3.00,3.25]%ofthenominalvalue.
There isno hysteresisimplementedbetween therisingand fallingedges ofthebattery monitoringcomparator.
The defaultvalueisgenerally3.200V nominal(seetheVBATMIN_HI_THRESHOLD register).
For a correctsystem behavioral,the VBATMIN_HI thresholdvalue must not be programmed above 3.350V nominal(3.455V maximum); otherwisethePhoenixpower devicewillnot switchon aftera chargerplug,batterycharged up to VOREGmin =
Itis possibleto configurethe VBATMIN_HI thresholdwith the same values as VBAT_MONITORING, ifitfitsthesystemrequirements. Table14 liststheparametersforthefallingedge oftheVBATMIN_LO threshold. Table14.VBATMIN_LO Threshold PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltagethreshold <000000> 2.265 2.300 2.370 V Voltagethreshold <000001> 2.015 2.050 2.115 V Voltagethreshold <000010> 2.065 2.100 2.165 V Voltagethreshold <000011> 2.115 2.150 2.215 V Voltagethreshold <000100> 2.165 2.200 2.270 V Voltagethreshold <000101> 2.215 2.250 2.320 V Voltagethreshold <000110> 2.265 2.300 2.370 V Voltagethreshold <000111> 2.310 2.350 2.425 V Voltagethreshold <001000> 2.360 2.400 2.475 V Voltagethreshold <001001> 2.410 2.450 2.525 V Voltagethreshold <001010> 2.460 2.500 2.580 V Voltagethreshold <001011> 2.510 2.550 2.630 V Voltagethreshold <001100> 2.560 2.600 2.680 V Voltagethreshold <001101> 2.610 2.650 2.730 V Voltagethreshold <001110> 2.665 2.700 2.785 V Voltagethreshold <001111> 2.705 2.750 2.835 V Voltagethreshold <010000> 2.755 2.800 2.885 V Voltagethreshold <010001> 2.805 2.850 2.940 V Voltagethreshold <010010> 2.855 2.900 2.990 V Voltagethreshold <010011> 2.905 2.950 3.040 V Voltagethreshold <010100> 2.955 3.000 3.090 V Voltagethreshold <010101> 3.000 3.050 3.145 V Voltagethreshold <010110> 3.050 3.100 3.195 V

52 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 NOTE

Minimum valuesaredefinedat–[1.50,1.75]%ofthenominalvalue.
Maximum valuesaredefinedat+[3.00,3.25]%ofthenominalvalue.
An hysteresisisimplementedbetween therisingand fallingedges,varyingfrom 100 mV (VBAT = 2.050V nominal)to600 mV (VBAT = 3.100V nominal).
The analogIP duplicatesthe VBATMIN_LO defaultvalue:<000000> and <000110> selectioncodes areidentical(2.300V nominal).
Because VBAT minimum levelis definedas 2.3 V throughthe Phoenix power IC specification,allcodes between <000001> and <000101> must not be used forthe correctoperationofthedevice. Reset Signals,Reset Triggers,Reset Domains Thissectiondescribesthedifferentresettriggersand thesignalsrelatedtoresets.
Power-on reset:Itistriggeredwhen a low batteryand a low backup batteryconditionoccurs.Thisactivates a POR thatremains activeuntila validenergy source is detected.The POR releaseinitiatesthe boot sequence oftheTWL6030 device.A delayedversionofPOR isused inthechargerand releasedduringboot sequence when theresourcesrequiredby thechargerareavailable.Duringa POR, theTWL6030 deviceisin a NO SUPPLY state.
Warm reset(NRESWARM) :The TWL6030 devicedetectsa requestfora warm reseton theNRESWARM ball.The effectofthewarm resetistorestartthesystem withoutturningoffthesupplies.Aftera warm reset, the system isconfiguredas itisaftera firstswitch-on(defaultconfiguration),exceptthatthe statesof all resourcesare unchanged and allsupplyvoltagevaluescan be preserved,dependingon the warm reset sensitivitybitvalue(WR_S SMPS_CFG_VOLTAGE/LDO_CFG_VOLTAGE): – Allresourcesnotincludedintheswitch-onsequence keep thestate(ON orOFF) theyhave justbeforethe warm reset. – Depending on thesensitivitybit,thoseresourceseitherkeep thevaluetheyhad beforethewarm resetor aresettotheirdefaultvalue. – Allresourcesincludedinthestart-upsequence arerestartedinany case. Duringthepower-onsequence,theTWL6030 deviceignoresthewarm resetuntilthehostprocessorreleases it. Warmreset affectsthe POWER and CHARGER registers.Registersforothermodules likethe USB, FUEL GAUGE, GPADC, and PWM arenotaffectedby warmreset
Softwarereset:A coldresetcan be initiatedby softwarethroughtheI2C controlinterface.The effectofthis softwarereset(theSW_RESET bitin the PHOENIX_DEV_ON register)forcesthe TWL6030 deviceto performa switch-offsequence (go to the WAIT-ON/OFF state).Thisisfollowedby a switch-onsequence (WAIT-ON toACTIVE).
Long key press:The longkey presson PWRON generatesa reset,thusforcingtheTWL6030 devicetogo intoWAIT-ON/OFF state.The 10-secondlengthisnotconfigurable.
Primary watchdog reset:The TWL6030 deviceincludesa primarywatchdog timer,whichgeneratesa reset of the system in case of a softwareanomaly (no response,infiniteloop)(theDEVOFF_WDT bitin the PHOENIX_LAST_TURNOFF_STS register).The primary watchdog PRIMARY_WATCHDOG_CFG is programmable from 1 to 127 seconds witha defaultvalueof 32 seconds.In case the primarywatchdog expires,itgeneratesa resetforcingtheTWL6030 devicetogo intotheWAIT-ON/OFF state.The watchdog is initializedto itsdefaultvalue when the system is in WAIT-ON/OFF stateand startswhen leavingthe WAIT-ON/OFF statetotheACTIVE/SLEEP states.Softwarecannotdisabletheprimarywatchdog,which is possibleonlythroughEPROM fortestingpurposes.
Thermal shutdown :Ifthedietemperaturegetstoohigh,thethermalshutdown generatesa reset,forcingthe TWL6030 device into the WAIT-ON/OFF state (the DEVOFF_TSHUT bit in PHOENIX_LAST_TURNOFF_STS). See alsothe associatedthermalshutdown registers:TMP_CFG_GRP, TMP_CFG_TRANS, TMP_CFG_STATE, and TMP_CFG.
NRESPWRON :The NRESPWRON outputsignalistheresetsignaldeliveredtothehostprocessorattheend ofthepower-onsequence.Itisreleasedwhen allTWL6030 supplyvoltages(coreand I/Os)arecorrectlyset up. In addition,the NRESPWRON signalcan be gated untilthe 32-kHz crystaloscillatorbecomes stable (configuredthroughan EPROM bit).The polarityoftheNRESPWRON signalisactivelow. Copyright© 2010–2011,Texas InstrumentsIncorporated 53

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com

PWRON :The PWRON ballisconnectedtoa push buttontocontrolsystem power on/off.An internalpullup on thebatterydomain isimplementedon thisinput.Threetimersareassociatedwiththisinputduration: – A shorttimerof15 ms toconfirmthekey pressdetection.Thisconfirmationinitiatesa power-onsequence orgeneratesan interrupt,dependingon thesystemstate. – A longtimer,programmablefrom50 ms to1.55seconds,thatmeasures thekey press.A registerbitisset ifthekey pressdurationexceedsthetimerduration. – A verylongtimerof 10 seconds thatcauses a hardware switch-offof the system PWRON detectionis performedon fallingand risingedges (oneinterruptline,1 interruptstatusbit).The polarityofthePWRON signalisactive-low(keypressed).
RPWRON : Similarto PWRON, RPWRON controlssystem power on/off.An internalpullupon the battery domain isimplementedon thisinput.A shorttimerof15 ms isimplementedtoconfirmdetection.Confirmation initiateseithera power-onsequence ora generationofan interrupt,dependingon thesystemstate.Detection ofRPWRON isperformedon fallingand risingedges.The polarityofRPWRON isactivelow(keypressed).
REGEN1, REGEN2 :The power-management FSM controlstheseoutputsignals.These ballsare activated duringthe power-on/offsequences.The timingof activationdepends on the power sequence (EPROM). REGEN1 and REGEN2 can be used tocontroltwo differentexternalpower supplies.The polarityofthese signalsisactivehigh.
SYSEN : This outputsignalis controlledby the power-management FSM and is activatedduringthe power-on/offsequences.The timingofactivationdepends on thepower sequence.SYSEN can be used to controlan externalpower supplyora slavePM device.The polarityofSYSEN isactivehigh. Power State-Machine The TWL6030 FSM controlsbootsequences,Phoenixgroupstatechanges,and subsystemsgroupinitialization. The power sequencingis made throughbroadcastcommands (severalresourcesaccessed simultaneously throughbroadcastcommands or individualaccess to a resource.The power sequences are storedin a hard-codedtable(EPROM). The FSM reactson events,whichinitiatespower statetransitions.
Hardware events – Startingevents(goingintoACTIVE state) – Power on button(PWRON ball) – Remote power on (accessories)(RPWRON ball) – Batteryplug(VBAT ball) – VAC detection – USB VBUS detection – USB ID detection – RTC alarm – Stoppingevents(goingtoOFF state) – ShortPWRON key press(interrupttohostIC,whichinitiatesswitch-off) – Long PWRON key press(hardwareswitch-off) – Remote power on (RPWRON) (interrupttohostIC,whichinitiatesswitch-off) – Primarywatchdog(hardwareswitch-off) – Thermalshutdown(hardwareswitch-off) – Backup events(goingintoNO SUPPLY orBACKUP state) – Removal ofmain and/orbackup battery – Low main and/orbackup battery
Softwareevents – Stoppingevents(goingtoOFF state) – Group DEVOFF instruction(allgroupsareOFF) – Softwarereset(SW_RESET) (goingtoOFF stateand thenrestarttoACTIVE) Internalhardware monitorsthe differentenergy sources (main and backup) and chargingsources (VAC or VBUS). A setofcomparatorsisdedicatedtoenergysourceselectiontogeneratean uninterruptedpower supply (UPR) whichexistsas soon as a validenergysourceispresent.The backup batteryisconsideredtobe a valid energysourceafterthefirstpower up ofthedevice.POR isreleasedwhen UPR risesabove toPOR threshold

54 Copyright© 2010–2011,Texas InstrumentsIncorporated

VBATMIN_HI VRTC VBACKUP VSHUNT_MIN VBATMIN_LO VPOR VBATMIN_HI VAC VBUS VBATMIN_LO BG VREF POR TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 and the voltageregulatorVBRTC providea supply forthe digitalcontrol,the 32-kHz oscillatorsand the low-powerband gap.When themain batteryvoltagerisesabove theVBATMIN_LO threshold,thedigitalcontrol enablesthechecksofthestartupevents.When a startupeventisdetected,a finalcheckofthebatteryvoltageis done versusthe VBATMIN_HI thresholdto pursue the power-up sequence.When the system isactive,the comparatoris availableto perform checks on batteryvoltage.Itthen compares batteryvoltageversus a programmable value and generatesinterruptswhen voltagerisesabove and drops below the programmed threshold.The comparator can be programmed from 2.3 to 4.6 V levelin 50-mV steps.Hysteresisis implementedbetween therisingand fallingedges,varyingfrom100 mV (VBAT = 2.3V) to600 mV (VBAT = 4.6 V). NOTE

UPR = VBAT if:(VBAT > VBATMIN_LO) + (VBAT > VBACKUP) . (VCHARGER < VCHARGERmin)
UPR = VBACKUP if:{[(VBAT< VBATMIN_LO) .(VBAT < VBACKUP - 0.1V)].(VCHARGER < VCHARGERmin)} .PORZ
UPR = VCHARGER if:(VBAT < VBATMIN_LO) .(VCHARGER > VCHARGERmin) Figure8 shows a blockdiagramoftheanalogpower control. Figure8. Block Diagram oftheAnalog Power Control The bootsequence isshown inFigure9.Thismonitoringvalidatesthecurrentstateand thetransitionsbetween thestates. Copyright© 2010–2011,Texas InstrumentsIncorporated 55

VUPR>VPOR VBAT<VBATMIN_LO VBAT>VBATMIN_LO or VSHUNT>VSHUNT_MIN VBAT>VBATMIN_LO or VSHUNT>VSHUNT_MIN VUPR<VPOR VUPR<VPOR Load boot mode (Boot pins) ENABLE VBRTC RELEASE POR NO SUPPLY SET BCI RESET WAIT-ON LOW SUPPLY VBAT>VBATMIN_LO RELEASE BCI RESET If under reset BACKUPLoad trim data (EPROM) VBAT>VBATMIN_HI Backup condition Backup condition Backup condition Backup condition TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure9. Boot Sequence NOTE

Backup conditionmeans VBAT < VBATMIN_LO and VSHUNT < VSHUNT_MIN.
The systemisinNO SUPPLY statewhen VUPR < VPOR. Figure10 shows a diagramofthepower-statetransition.

56 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Figure10. Power-StateTransitionDiagram

Power-ontransitions:T1 – System isinNO SUPPLY orBACKUP state.Connectionofa validenergysourceinitiatesthetransitionto Copyright© 2010–2011,Texas InstrumentsIncorporated 57

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com WAIT-ON state. – Triggeringevent:VBAT > VBATMIN_LO – Insertionofa chargedmain battery – Prechargeisactive,main batteryvoltagerises – Condition:VUPR > VPOR

Power-offtransition:T2 – The systemisinany state.Removal ofallenergysourcesinitiatesa transitiontoNO SUPPLY state. – Triggeringevent:VUPR < VPOR – Main batterydischargeorremoval – Backup batterydischargeorremoval – Chargerunplugged – Condition:No more validenergysource
Switch-ontransition:T3 – The system is in WAIT-ON state,able to accept a hardware switch-oncondition,which initiatesa transitiontoACTIVE state. – Triggeringevent: – Push buttonpressedand released(PWRON) – Chargingsourceplug(USB orexternal) – RTC alarm – Accessoryplug(RPWRON) – Insertionofa chargedmain batteryorbatterychargerunning(enabledby default) – Softwarereset(followingtransitionT4) – USB ID pluginsertion(disabledby default) – Condition:VBAT > VBATMIN_HI and no thermalshutdownactive
Switch-offtransition:T4 – System ispowered and inACTIVE orSLEEP state.A hardwareconditionmay initiatea transitiontoreach WAIT-ON state. – Triggeringevent: – Group DEVOFF command (software)(ifallothersubsystemsgroupsareOFF) – Thermalshutdown – Primarywatchdogtimerexpired – Softwarereset(followedby transitionT3) – Long key press(10seconds)on PWRON
Sleep-ontransition:T5 – System ispowered and inACTIVE state.A hardwareconditioninitiatesa transitiontoSLEEP state. – Triggeringevent:Subsystem groupsleepcommand (hardware)(PREQ# balls) – Condition:AllothersubsystemgroupsareSLEEP orOFF.
Sleep-offtransition:T6 – System ispowered and inSLEEP state.A hardwareconditioninitiatesa transitiontoACTIVE state. – Triggeringevent: – Subsystem groupactivecommand (hardware)(PREQ# balls) – Warm reset(reinitializationoftheTWL6030 device)
Activeresettransition:T7 – System is powered and in ACTIVE state.A hardware conditioninitiatesa reset,system remains in ACTIVE state. – Triggeringevent:Warm reset(reinitializationoftheTWL6030 device)
Backup-ontransition:T8 – System ispowered and in ACTIVE, SLEEP, or WAIT-ON state.The detectionof a low main battery initiatesthetransitiontoBACKUP state. – Triggeringevent:Batteryvoltage< VBATMIN_LO (discharge/removal)

58 Copyright© 2010–2011,Texas InstrumentsIncorporated

CHRG_CSIN VBUS detector OVV detector USB PHY 0.6 V 100 /c109A 0.32 V 2 V VUSB DP DM USB charger detection control Accessory charger adapter detection and ID detection ID Attach detection protocol Thermal protector TWL6030 power IC USB OTG Charging control and watchdog Battery temp BSI CHRG_PMID CHRG_CSOUT CHRG_PGND CHRG_SW CHRG_BOOT CHRG_VREF CHRG_LED_TEST USB PHY USB LDO CHRG_AUXPWR CHRG_DET_N_PROG TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 – Condition:VUPR > VPOR BATTERY CHARGING The TWL6030 devicehas an integratedswitch-modechargerto charge the batteryfrom the USB connector. Figure11 shows a blockdiagramoftheUSB chargingelectronics. Figure11. Block Diagram oftheBatteryCharger The main featuresofthechargerare:

High-efficiencybatterychargerfromtheUSB connector
Interface to support external customer-specificcharger and to monitor (through the CHRG_EXTCHRG_STATZ pin)thestatusoftheexternalchargepath(VAC)
Built-ininputcurrentlimiting
Chargingsourcevoltageoperatingrange:4.0to6.3V
Integratedpower FETs up to1.5A chargingcurrent
Toleratea voltagefrom–0.3to20 V on chargerinputrelatedballs
Programmable chargeparameters: Copyright© 2010–2011,Texas InstrumentsIncorporated 59

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com – Inputcurrentlimit – Fast-charge/terminationcurrent – Charge voltage – Inputvoltagecollapse – Safetytimer – Terminationenable

Synchronousfixed-frequencyPWM controlleroperatingat3 MHz with0% to99.5% duty-cycle
High-accuracyvoltageand currentregulation
Automatichigh-impedancemode forlowpower consumption
Safetytimerwithresetcontrol
Reverseleakageprotectionpreventsbatterydrainage
Thermalregulationand protection
I/Oovervoltageprotection
OutputforchargingLED indicator
Automaticchargecurrentsetting(preventingchargeinputfromcollapsing)as chargetimeoptimization
Boostmode operationforUSB OTG supply(VBUS supplyat5 V/200mA current) The TWL6030 devicesupportsa wide varietyofrechargeablelithium-basedbatterytechnologies.Recent battery technologies,such as Li-SiAnand LiFePo4, presenta flatdischargeregionin the range of 3.2–3.3 V; technologiessuch as LiCoO2 and LiNiMnCoO2 presenta flatdischargeregioninthe range of 3.6–3.7 V. To support the differentbatterychemistrieseffectively,the TWL6030 device has programmable VBATMIN thresholds. The charging procedure consistsof hardware-controlledpreconditioningand prechargingphases and software-controlledfull-chargingphase.The chargeralsoperformsmonitoringfunctions:
AC chargerdetection
VBUS detection
Batterypresencedetection
VBUS overvoltagedetection
Batteryovervoltagedetection
Batteryend-of-chargedetection
Thermalprotection
Watchdogs Charging Phases Preconditioning Preconditioningisautomaticallyenabledas soon as thechargingsourceisdetectedand operatesina constant currentchargingmode. During preconditioningthe batteryvoltageis below 2.1 V (VBAT_SHORT) and the chargingcurrentislimitedto30 mA (IBAT_SHORT). Inthismode, thechargeruses a linearchargingoperation mode. This phase detectsa defective(shorted)battery.As soon as the batteryvoltageisabove 2.1 V, a prechargingphase isenteredautomatically. Precharge Phase (Hardware Controlled) The prechargingphase isenteredwhen batteryvoltageisabove 2.1V (VBAT_SHORT) and thechargingsource isdetected.Ifthechargingsourcecollapsesduringtheprechargephase,theprechargecurrentisautomatically reduced to a valuethatkeeps the inputvoltagehigh enough to ensure properoperationof the precharge circuitry. The TWL6030 devicesupportstwo prechargingmodes:
Slow constantcurrentprechargingfor2.1V < VBAT < 3.54V (VBUS currentislimitedto92 mA from USB standarddownstream port)
Fastconstantcurrentprechargingfor2.1V < VBAT < 3.54V (VBUS currentislimitedto470 mA and battery chargingcurrentsettodefaultchargingcurrentvaluewhen USB chargingportdetected)

60 Copyright© 2010–2011,Texas InstrumentsIncorporated

VBAT_SHORT VBATMIN_LO VBATMIN_HI VBAT_MAX Battery pre- conditioning 30 mA VPRCH_MAX System active and battery full-charge Battery precharge Input: 92/470 mA limitation Output: Default 3.54 V/ 500 mA TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Full-ChargePhase (SoftwareControlled) Full-chargecan startonlywhen the batteryvoltageisabove VBATMIN_HI, because thisphase isunder the controlofthehostprocessor,and itstopswhen thebatteryvoltageisbelow VBATMIN_LO. Duringthisphase, thefollowingresourcesareavailabletocontrolthechargeprocess.

Charge currentsetpointregisterVICHRG3:0
Charge voltagesetpointregisterVOREG[5:0] (constantvoltagemode)
End ofchargecurrentsetpointregisterVITERM[2:0](minimum currentwhen inconstantvoltagemode)
InputlimitcurrentsetpointregisterCIN_LIMIT[3:0](maximum currentdrawn fromchargingsource)
InputvoltagesetpointregisterBUCK_VTH[2:0] (VBUS voltagecollapsinglevel)
Charge watchdogsetpoint(programmableup to127 s,32 s by default) Ifthechargingsourcecollapsesduringthefull-chargephase,thefull-chargecurrentisautomaticallyreducedtoa valuekeepingtheinputvoltagehigherthanthepresetvalue,toensureproperoperationofthechargecircuitry. Ifthechargingcurrentterminationisenabled,thechargingisstoppedifthecurrentdecreasesbelow thepreset limitduringconstantvoltagecharging.Thisindicatestheend ofthechargeperiod. Figure12 shows thebatterythresholds. Figure12. BatteryThresholds Charger ControllerOperation IfVAC orVBUS isdetectedwhen thebatteryvoltageisabove VPRCH_MAX, chargingisenabledby thecharger controller,butgatedby theUSB chargerand VAC chargerbecause thevoltageisabove thedefaultcharging Copyright© 2010–2011,Texas InstrumentsIncorporated 61

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com voltage.The TWL6030 deviceinitiatesstartupand indicatesthereasonforthestartupina register.Ifthebattery voltageis between VBATMIN_HI and VPRCH_MAX, chargingis startedand the TWL6030 deviceinitiates startup.IfthebatteryvoltageisbelowVBATMIN_HI, chargingisstartedand theTWL6030 deviceinitiatesstartup when thebatteryvoltagecrossestheVBATMIN_HI level.Ifthedeviceisalreadypowered on when thechargeris attached,theTWL6030 deviceonlygeneratesan interruptforthesoftware. The simplifiedstatetransitionsduringchargingarepresentedinTable15.The gatingofthechargingmeans that thechargingisdisabledbutcontinuesifthereasonforthegatingdisappears.The chargingterminationmeans thatthe chargingisstopped.To continuecharging,the chargermust reconnector softwaremust enablethe chargingby writinga softwarebit.The WD column indicatesthe operationof chargingwatchdog.The INT column indicatesthegenerationoftheinterrupt,R signifyingrisingedge and F signifyingfallingedge.Inaddition, the interruptgenerationcan be masked fordifferentreasonsby registerbits.The REGISTER RESET column indicateswhichregistergroupsarereset. During startupcharging,the chargingstate-machinecontrolsthe charginguntilsoftwaretakes controlover chargingby updatingwatchdogoperationorby changingtheUSB charging-relatedcurrentorvoltagevalues. The defaultwatchdog timesareselectableby EPROM bits.The watchdog timeduringfullchargeisselectedby registerbits. Table15.SimplifiedStateTransitionsDuring Charging PRECONDITIONING FULL CHARGE REGISTEOR PRECHARGE COMMENTSNRESPWRON = 1 R RESETNRESPWRON = 0 BIT/SIGNALREASON WD INT WD INTPARAMETER VBUS_DET WaitingforCharger Charging HWVAC_DET No software SW mode Yes None Chargerinsertioninsertion enabled mode(rising) enable Charger Charging Charging Chargerinsertion,VBUS_DETinsertion(other source continues softwareselectstheVAC_DET Run No Run Yes Noneone already selectedby fromthe priorityifNRESPWRON(rising)attached) priority firstone = 1. IfNRESPWRON = 0,VBUS charger POOR_SRC Gated Run No Gated Run R/F None VAC chargerisenabledundervoltage after2.5s,ifattached. IfNRESPWRON = 0,VBUS charger VBUS_OVP Gated Run No Gated Run R/F None VAC chargerisenabledovervoltage after2.5s,ifattached. VBUS charger TH_SHUTD Gated Run No Gated Run R/F Noneovertemperature Batteryinvalid BAT_TEMP_ Gated Run No Gated Run R/F Nonetemperature OVRANGE Batterypack removal detected.Ifbattery GPADC_IN0 voltagefallsbelowBRIComp = 1 Gated Run No Gated Run Yes (1) Nonelinefloating VBATMIN_LO, NRESPWRON issetto low. SUSPEND AppliestoVBUS chargerSuspend bit N/A Gated Run No None_BOOT = 1 only VBUS End-of-chargeindication;termination VITERM [2:0] Gated Run No Gated Run Yes None disabledby defaultbycurrenttriggers TERM = 1 EPROM.(enabledby bit) (1) BATREMOVAL also.

62 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Table15.SimplifiedStateTransitionsDuring Charging (continued) PRECONDITIONING FULL CHARGE REGISTEOR PRECHARGE COMMENTSNRESPWRON = 1 R RESETNRESPWRON = 0 BIT/SIGNALREASON WD INT WD INTPARAMETER Charging Softwarechecksthe source reasonand determines changed after theoperation.The error 2.5s ifthe can be: otherone is Gated by -VAC overvoltageErrorinexternal CHRG_VAC_S available; Run No external Run Yes None -SLEEP statecharging TATZ = 1 otherwise, charger -Bad adaptor chargingis -Batteryovervoltage gatedby the -Thermalshutdown external -Timerfault charger. -No battery Charger VBUS_DET orremoval(one ChargeVAC_DET Terminated No Terminated Yes Chargerremovalcharger group(falling)attached) Charger Chargingremoval(both VBUS_DET or continues To continuechargingchargers ChargeVAC_DET fromthe Run No Terminated Yes fromtheothercharger,attached,the group(falling) remaining softwaremust enableit.enabledone is chargerremoved) Charger removal(both VBUS_DET orchargers Charging ChargingVAC_DET Run No Run Yes Noneattached,the continues continues(falling)enabledone is removed) The reasonscan be: -Shutdown (software initiated) -Softwarereset -Batteryvoltage NRESPWRON NRESPWRON droppingbelowN/A Terminated No Allfallingedge (falling) VBATMIN_LO -Primarywatchdog expiration -TWL6030 thermal shutdown -Long key press Primary SetsNRESPWRON towatchdog N/A N/A lowexpires 32-kHzcrystal Terminated No Terminated No Alloscillatorstops Charging Chargewatchdog Terminated No Terminated Yes groupexpires Batteryvoltage VBATMIN_LO SetsNRESPWRON todroppingbelow N/A(falling) lowVBATMIN_LO TWL6030 SetsNRESPWRON tothermal THPROT = 1 N/A lowshutdown Isloadersoftware Warm reset NRESWARM N/A Terminated No All executedhere?Limit registerreset. Watchdog insoftwareWDG_RST orWatchdog reset N/A Continued WDT[6:0] No None mode. SoftwaretakesWDT [6:0] controlovercharging. Copyright© 2010–2011,Texas InstrumentsIncorporated 63

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Table15.SimplifiedStateTransitionsDuring Charging (continued) PRECONDITIONING FULL CHARGE REGISTEOR PRECHARGE COMMENTSNRESPWRON = 1 R RESETNRESPWRON = 0 BIT/SIGNALREASON WD INT WD INTPARAMETER VBUS VICHRG [3:0] Watchdog insoftware current/voltage orVOREG N/A Continued Run No None mode. Softwaretakes settingchange [5:0] controlovercharging. Enablecharging EN_CHARGE ChargingN/A WDT[6:0] No Noneby software R = 1 enabled Disable EN_CHARGE Chargechargingby N/A Terminated NoR = 0 groupsoftware AnticollapseLoop The analog anticollapseloop operatesso thatthe inputvoltageismonitoredcontinuouslyand the charging currentissetby analoglooptomaintainthedefinedinputvoltage. BatteryTemperature Measurement The batterytemperatureismeasured usingan externalNTC resistor.The measurement isenabledbeforethe chargingstartsand thetemperatureisconstantlymonitoredduringcharging.Ifthebatterytemperatureisoutside thevalidrange,thechargingisgated;ifthetemperaturereturnsinsidethevalidrange,thechargingcontinues.If a batterydies,the batterytemperatureismonitoredso thatthe chargingdoes not startifthe temperatureis outsidethevalidrange.The gatingofthechargingcan be disabledwithan EPROM bitifneeded. The module isenabledifVBUS or an externalchargerisdetected.An interruptisalwaysgeneratedwhen the batterytemperaturecrossesthetemperaturelimitsinbothdirections.The interruptgenerationcan be masked if needed. Figure13 shows thebatterytemperaturemeasurement circuitry.

64 Copyright© 2010–2011,Texas InstrumentsIncorporated

GPADC_IN1 GPADC GPADC_VREF1 VREF_ADC GPADC_GND VBG Mux Register (loaded from EPROM) and decoding MuxRatio-TLO RX RY TLO THI RTH Ratio-THI TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Figure13. BatteryTemperature Measurement Because theNTC characteristicishighlynonlinear,itiscombined withtwo resistorsallowinglinearizationofits characteristicand making the sensitivityof the system more constantover a wide temperaturerange.The resultingvoltageatGPADC_IN0 can be measured usingtheGPADC and isalsomonitoredby two comparators thatenablethechargeofthebatteryonlywhen thetemperatureiswithina specifiedwindow,typically0°C to 60°C. ResistorsR X and R Y areused tosetthedesiredtemperaturethresholdlevels. Charging Watchdog The chargingwatchdog timedepends on thechargingcontrolmode and on theUSB chargerdetectionresult. Duringhardware-controlledcharging,thewatchdogtimefortheUSB chargingportisapproximately6 minutesfor theUSB standarddownstream portand approximately14 minutesfora customer-specificcharger.Longervalues can be selectedwiththeEPROM bit:11 minutesinsteadof6 minutesand 29 minutesinsteadof14 minutes. Charger sourcedependency on WDG valuescan be enabledand disabledby EPROM. Ifdisabled,the WDG valueisalwayssetas fortheUSB standarddownstream portand forthecustomer-specificcharger(longerWDG value).Duringsoftware-controlledcharging,softwarecan selectthe watchdog time up to 127 seconds.The transitionfrom hardware-controlledchargingtosoftware-controlledchargingoccurswhen softwareupdatesthe WDG_RST, WDT[6:0],VICHRG[3:0],or VOREG[5:0] bits.The differentwatchdog timesare summarized inthe followingtable. Copyright© 2010–2011,Texas InstrumentsIncorporated 65

GP ADC_IN0 VBRIRef IBRI BA TREMOV AL VRTC TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com EPROM WATCHDOG TIME (CHARGING CHARGING CHARGING EPROM SOURCE SOURCE CONTROL (WDG VALUE) MIN MAX DEPENDENCY)

1 USB chargingport Hardware 0 5 min 4 s 5 min 36 s

1 Others Hardware 0 13 min 13 s 14 min 15 s

1 USB chargingport Hardware 1 10 min 10 s 11 min 12 s

1 Others Hardware 1 26 min 26 s 28 min 29 s

0 Hardware 0 13 min 13 s 14 min 15 s

0 Hardware 1 26 min 26 s 28 min 29 s

SoftwareAll X 0 127 s(programmable) LimitRegisters Duringfull-chargephase,softwaresetsthechargingvoltageand current.However, theTWL6030 devicelimits thecurrentand voltagetoa levelthatisdefinedinthelimitregisters.The limitregistersintheTWL6030 device must be writtenjustafterthestartup.Softwaremust check thebatterytypeand definethemaximum charging currentand voltageforthe batterybeing used, writethe limitvalues,and lockthe limitregisterswiththe LOCK_LIMIT registerbit,so thatthesecannotbe changed when thedeviceispowered on.The limitvaluesare resetduringpower offby theNRESPWRON signaland theymust be writtenby softwareduringeverypower up. Thisensuresthatthird-partysoftwareora viruscannotseta chargingcurrentorvoltagethatistoohigh. BatteryPresence Detector The TWL6030 device supportsbatterydetection.The presence of the batterycan be detectedwith the GPADC_IN0 inputsignal.The interfacehas two differentfunctions:

Detectbatteryremoval/presence
Measure thesizeoftheresistorconnectedtotheGPADC_IN0 lineinthebatterypack usingtheGPADC Batterypack removalisdetectedby a comparatorthatmonitorsGPADC_IN0. The batterypack must have a pulldownresistor(RBRI) and the TWL6030 devicehas a currentsource(IBRI) inthe line.Ifthe batterypack is removed, GPADC_IN0 risesabove the comparatorthresholdlevel,the batteryremoval isdetected,and the TWL6030 devicesends an indicationto the hostprocessor.In addition,batterychargingisterminatedifthe batteryisnot present.Batteryremovalisdetectedwitha comparatorand a currentsourceissuppliedon the VRTC supplydomain.Thissupplyscheme allowsthedetectionina dead batterycase configuration,because the VRTC can be suppliedfrom theVBUS or VAC lines.The batterypresencedetectionmodule isenabledduring thechargingand duringtheACTIVE and SLEEP states. Figure14 shows a blockdiagramofthebatterypresencedetectionmodule. Figure14. BatteryPresence Detector IndicatorLED Driver The TWL6030 devicehas an indicatorLED driverthatindicateschargingisongoingduringhardware-controlled

66 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 charging.Duringhardware-controlledcharging,the LED driverisenabledonlyifthe USB chargeror external chargingIC ischargingthe battery,and itisturnedoffifthe batteryisnot charged (forexample,because of chargerovervoltage).The supplyforthechargingindicatorLED driverisgeneratedfrom CHRG_PMID or VAC, dependingon theactivechargingpath.The CHRG_PMID pinisused insteadoftheVBUS lineso thattheLED indicatorcurrentisincludedintotheVBUS inputcurrentlimit. Duringpower on,softwarecan controltheindicatorLED regardlessofthecharging.The supplyfortheLED can be selectedas CHRG_PMID, VAC, orCHRG_LED_IN. The currentlevelcan alsobe selectedand thedimming functioncan be used.Dimming isdone witha 128-Hz PWM signal,whichhas 255 linearsteps.The LED output pinhas a selectablepulldownwhen themodule isdisabled;thepulldownisenabledby default. BOOST mode For OTG operation,the TWL6030 devicecan supplyVBUS (5 V) inboostmode. In thismode, the TWL6030 devicedeliversup to200 mA currenttotheUSB connector.Boostmode can be enabledthroughregisteraccess by writingOPA_MODE intheCHARGERUSB_CTL1 register.InVBUS supplygenerationmode, theTWL6030 devicecan detecta shortcircuitinthe VBUS line.Ifa shortcircuitisdetected,the VBUS voltagegeneration stopsand an interruptisgeneratedtothehostprocessor. Supported Batteries TWL6030 supportsthefollowingbatterytechnologies:

Li-Ion
Li-Ionpolymer
Cobalt-Ni-Manganese
LiCoO2
LiNiMnCoO2
Li-SiAn
LiFePo4 Recent batterytechnologysuch as Li-SiAnand LiFePo4 presentsa flatdischargeregionintherangeof3.2–3.3 V; technologiessuch as LiCoO2 orLiNiMnCoO2 presentsa flatdischargeregionintherangeof3.6–3.7V. This resultsin differentVBATMIN thresholds,depending on the type of batteryused in the system. As a consequence,theVBATMIN thresholdsareprogrammable. Supported Charging Sources The followingchargersaresupportedwiththeintegratedswitch-modechargerfromtheUSB connector:
Dedicatedchargingport
Chargingdownstream port
Chargerfull-fillingspecificationYD/T 1591-2006 To configurethe chargerforproperoperationmode depending on the chargingsource characteristics,the chargingsource type must be detectedand identified.The detectionof the chargerattachedto the USB connectorismade insidetheTWL6030 deviceby detectinga voltagegreaterthanVINmin on chargerinput. To minimizethecapacitanceofthedatalines,thetypeofthechargerconnectedtotheUSB connectorcan be identifiedby theUSB PHY, and theinformationofthemaximum currentdrawn fromthechargingsourcemust be transmittedtotheTWL6030 devicewitha dedicatedsignal.The TWL6030 deviceenablesdetectionby delivering VUSB supply.The chargerdetectioncircuitrymust delivera CMOS level(VUSB) signaltotheTWL6030 device, CHRG_DET_N, by defaulta highlogiclevelindicatingthatUSB chargingportisdetected.The polarityof the chargerdetectionsignalcan be selectedwithan EPROM bit.The identificationoftheaccessorychargeradapter (ACA) occursintheTWL6030 device. The TWL6030 devicecan be interfacedwithan ACA (externaltotheterminal)tosupportthechargingfromthe USB chargerand USB communicationtootherUSB devicesfromtheUSB port.See theUSB OTG sectionfora descriptionofACA detection. Copyright© 2010–2011,Texas InstrumentsIncorporated 67

I C CHRG_EXTCHRG_ENZ VAC detector External charging IC BQ24156 Charging control and watchdog Battery temp BDET Control and watchdog Application processor INT CHRG_EXTCHRG_STATZ NRESPWRON TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Support forExternalCharging IC The TWL6030 devicecan be interfacedwithan auxiliarystand-alonechargerdevicetosupportthefollowinguse cases:

Simultaneousbatterycharge from a non-USB charger(differentconnector)and OTG operatingmode (the TWL6030 deviceinternalUSB chargerused as VBUS supply)
ChargingfromthesourcesnotconnectedtoUSB connector Figure15 shows an example ofan externalchargingIC supportedby theTWL6030 device. Figure15. ExternalCharger Interface The externalchargingIC isenabled with1.8-VCMOS levelsignal,CHRG_EXTCHRG_ENZ. Low logiclevel indicatesthatchargingisenabled.ChargingstatusisindicatedwiththeCHRG_EXTCHRG_STATZ signal.The externalchargingIC pullsthesignaldown duringcharging. The integratedUSB chargercan be associatedwithan externalVAC (wall)charger.For thatreason,VAC wall chargerinputisconnectedtotheTWL6030 devicetodefinethechargepriorities:
When theVBUS isdetectedand theVAC isnotdetected,theUSB chargestarts.
When theVAC isdetectedand theVBUS isnotdetected,theexternalchargingstarts.
When theVBUS and VAC are detected,theUSB chargestartsonlyiftheCHRG_DET_N pinissethighso theUSB chargehas a 475-mA inputcurrentlimitation. – When CHRG_DET_N = 0 (100-mA inputcurrentUSB limitation),theVAC wallchargerisexpectedtobe better(orequivalent)and thusischosen as thedefaultchargepath. – When CHRG_DET_N = 1 (500-mA inputcurrentUSB limitation),theprechargeassociatedwitha USB is expectedtobe sufficientforbattery-levelquickrecoveryiftheUSB chargepathischosen. Ifthereisfaultconditionon a chargerduringhardware-controlledchargingand thefaultconditioncontinuesat least2.5s,thechargingsourceischanged forlower-prioritycharger.The change intolower-prioritychargeronly preventstheinfiniteloopingbetween chargers.Ifonlyone chargerisattached,thechargerisnotdisabledinfault conditionand ifthefaultconditiondoes notdisappear,thechargingisterminatedwhen thewatchdogexpires. USB OTG The TWL6030 devicesupportstheBatteryChargingSpecificationRevision1.1and bothOTG 1.3and OTG 2.0 standards.The OTG revisionnumber ishardwarepredefinedby an EPROM bit.

68 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 The TWL6030 deviceembeds allhardware analogmechanisms associatedto VBUS and ID lines.The other aspectsoftheOTG system,such as theOTG controller(hardware/software)ortheUSB dataline(DP/DM) with HNP and SRP signaling,are embedded in the USB PHY, which can be eitherintegratedintoapplication processoror thereisstand-aloneUSB OTG PHY. Equally,theotheraspectsofBatteryChargingSpecification Revision1.1relativetoDP and DM pinsareembedded intheUSB PHY. The TWL6030 devicesupportsthefollowingfunctions:

OTG Revision1.3: – USB VBUS detections(comparatorsand associatedinterrupts): – OTG A-device(VA_VBUS_VLD, VA_SESS_VLD) – OTG B-device(VB_SESS_VLD, VB_SESS_END) – OTG A-device5-V VBUS power supplyprovider – OTG B-deviceUSB SessionRequestProtocol(SRP) – VBUS pulsingmethod: – VBUS chargemode (VBUS_CHRG_VBAT, VBUS_CHRG_PMID) – VBUS dischargemode (VBUS_DISCHRG) – USB ID detections(comparatorsand associatedinterrupts): – OTG A-device(ID_GND) – OTG B-device(ID_FLOAT)
OTG Revision2.0: – USB VBUS detection(comparatorsand associatedinterrupts): – OTG A-device/OTGB-device(VOTG_SESS_VLD) – OTG A-device(VA_VBUS_VLD) – OTG A-device5-V VBUS power supplyprovider – Embedded attachdetectionprotocol(ADP) mechanism (comparatorsand associatedinterrupts): – OTG A-device/OTGB-deviceADP probing: – VBUS chargemode (VBUS_IADP_SRC) – VBUS dischargemode (VBUS_IADP_SINK) – VBUS probemeasurement (VADP_PRB) – OTG B-deviceADP sensing(VADP_SNS) – USB ID detections(comparatorsand associatedinterrupts): – OTG A-device(ID_GND) – OTG B-device(ID_FLOAT)
BatteryChargingSpecificationRevision1.1: – USB ID detectionsforACA (comparatorsand associatedinterrupts): – OTG A-device(ID_GND) – ACA pulldown,OTG A-device(ID_A) – ACA pulldown,OTG B-devicecannotconnect(ID_B) – ACA pulldown,OTG B-devicecan connect(ID_C) – OTG B-device(ID_FLOAT) – ID ACA mechanism availableinbothprecharge(hardware)and SLEEP/ACTIVE states(software)
TWL6030 additionalfeatures: – VBUS wake-up detection(VBUS_WKUP) (maskable/risingedge) – VBUS overvoltagedetection(alwayson,combined withchargerIP) – VBUS precharge(combinedwithchargerIP) – ID wake-up detection(ID_WKUP) (programmable,disabledby default) – ID pulldown(ID_GND_DRV), pullups(ID_PU_220K,ID_PU_100K) – ID currentsources(ID_SRC,ID_WKUP_SRC) – GPADC VBUS monitoring(VBUS_MEAS) – GPADC ID monitoring(ID_MEAS) Copyright© 2010–2011,Texas InstrumentsIncorporated 69

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com There aretwo typesofVBUS and ID comparators,referredtothroughoutthissectionas wake-up (normallyused inTWL6030 SLEEP state)and activecomparators(generallyactivatedinTWL6030 ACTIVE state).Use ofthese comparatorsisnotexclusivetoTWL6030 SLEEP and ACTIVE states,butcan alsoserveinadditionaluse cases. Indeed,thewake-up comparatorstargetlow power consumption,whereas theactivecomparatorsare intended foraccurateleveldetection:

The wake-up comparatorsoperateinTWL6030 PRECHARGE, WAIT-ON, SLEEP and ACTIVE states.These comparatorscan wake up thedevicefroma SLEEP statebutcan alsoswitchon thedevicefroma WAIT-ON state.VBUS wake-up comparatorcan alsostarttheprecharge,providingthatallotherprechargingconditions aremet.
The activecomparatorsoperateinTWL6030 SLEEP and ACTIVE states.When operatinginSLEEP state,all requiredpower and clockresourcesshouldremainactive.ID activecomparators,used forACA detection,are automaticallyenabledinprechargemode; VBUS activecomparatorsremainoff. Table16.OTG IPFeaturesvs RegisterBits/Modes/Supplies FUNCTION/FEATURE REGISTER/REGISTER OTG TWL6030 SUPPLIES BIT REV. MODE/STATE NEEDED Vendor ID USB_VENDOR_ID_LSB – ACTIVE VRTC USB_VENDOR_ID_MSB ProductID USB_PRODUCT_ID_LSB – ACTIVE VRTC USB_PRODUCT_ID_MSB SRP – Pulsingmethod VBUS_CHRG_VBAT 1.3 ACTIVE VRTC VBUS chargeon VBAT VBAT SRP – Pulsingmethod VBUS_CHRG_PMID 1.3 ACTIVE VRTC VBUS chargeon PMID CHRG_PMID SRP – Pulsingmethod VBUS_DISCHRG 1.3 ACTIVE VRTC VBUS discharge ADP – Probing VBUS_IADP_SRC 2.0 ACTIVE VRTC VBUS charge VANA ADP – Probing VBUS_IADP_SINK 2.0 ACTIVE VRTC VBUS discharge VBUS detection VBUS_ACT_COMP 1.3 SLEEP VRTC

2.0 ACTIVE VANA

VBUS wake-up detection AlwaysenabledifVBUS – PRECHARGE/OFF VRTC orVAC ispresent SLEEP/ACTIVE VBUS GPADC VBUS_MEAS – ACTIVE VRTC measurement VANA ID 220-kΩ pullupon ID_PU_220K – ACTIVE VRTC VUSB VUSB ID 100-kΩ pullupon ID_PU_100K – ACTIVE VRTC VUSB VUSB ID grounddrive ID_GND_DRV ACTIVE VRTC ID 16-µA sourcecurrent ID_SRC_16U BC PRECHARGE VRTC

1.1 SLEEP/ACTIVE VUSB

ID 5-µA sourcecurrent ID_SRC_5U – ACTIVE VRTC VUSB ID detection ID_ACT_COMP BC PRECHARGE VRTC ID wake-up detection ID_WK_UP_COMP – OFF VRTC SLEEP/ACTIVE ID GPADC measurement ID_MEAS – ACTIVE VRTC VANA

70 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 NOTE

The VBUS and ID wake-up comparatorsarea starteventconditionwhen theTWL6030 deviceis in WAIT-ON state.IfVBUS wake-up enable isfixed,ID wake-up enable isconfigurableand disabledby default.Those comparatorscan alsomake theTWL6030 deviceleaveSLEEP state and enterACTIVE state.An interruptisalwayssenttothehostprocessor,butonlyifthemasks arenotapplied.
InPRECHARGE state,theVBUS wake-up comparator,theVUSB regulator,theID comparators, and the16-µA currentsourceare enabledautomaticallyby bothOTG and PM state-machines. The ACA identificationisrequiredby thechargerFSM fortheallowedcurrentchargeswhether an ACA isattachedornot.
The OTG_REV bitunlocksthe respectiveVBUS detectionfeaturesand associatedelectrical parametersspecifictoeach OTG revision1.3and revision2.0(seetheVBUS_ACT_COMP bit).
For allUSB OTG registers,two informativeadditionalrows (OTG 1.3/OTG 2.0)describeifthe bitshave an applicationuse foreach OTG revision.
AllTWL6030 OTG registersare unlockedand operateeitherwitha read/write(R/W) access or witha read/set/clear(R/S/C)process.
VBUS_ACT_COMP (USB_VBUS_CTRL_SET/USB_VBUS_CTRL_CLR) istheonlyR/W bitthat relieson the OTG_REV EPROM value.This bitenables the needed VBUS comparators, reducingthe power consumptionof the OTG VBUS analogsection.Therefore,alldeactivated comparatorshave theircorrespondingsourceand latchregistersfixedat0.
For some oftheanalogelectricalparametersthatare notbackward-compatiblebetween OTG revision1.3 and OTG revision2.0 but also are not manageable through the OTG_REV preselectionbit,itisassumed throughoutthissectionthatthe OTG revision2.0 characteristic limitssupersedetheOTG revision1.3electricallimitsand,thus,OTG 2.0isthereference.
OTG revision1.3 devices have justemerged on the electronicmarket and should be outnumberedshortlyby OTG revision2.0devices.
In addition,the USB-IF consortiumsuggestsa fast-forwardtransitionto OTG revision2.0 to solvecurrentincompatibilitiesand limitationsbetween OTG revision1.3devices.
Allelectricalparametricdeviationsfrom OTG revision1.3are explicitlyhighlightedthroughthis section.
The fulllistofnonbackward-compatibleelectricalparametersisavailableon theUSB-IF website inthedeveloperforumsection. ID Line The USB BatteryChargingSpecificationdescribesthe operationof ACA detection.Thisrefersto detectionof externalRID_A, RID_B, and RID_C resistorson ID pin.ID ground®ID_GND )and ID float®ID_FLOAT )arerelatedto the connectionsof the USB OTG standardplugs.Note thatwhen any one of the RID_A, RID_B, or RID_C resistancesispresentedattheID pin,thisimpliesthatVBUS supplyisprovidedby theACA. Thus afterwake up from VBUS or ID plugdetection(due to VBUS or ID wake-up comparatorscontrolledby ID_WK_UP_COMP, VBUS_WK_UP_COMP registerbits),softwarecan then enablethe ID activecomparatorsto correctlyidentify whichofthedifferentRID valuesispresent.Inaddition,an interruptisgeneratediftheresistanceon theID ball changes. During hardware-controlledcharging,the TWL6030 devicemonitorsifan ACA is connected and sets the correspondingVBUS inputcurrentlimit. The followingpullupand pulldownresistorsand currentsourcescan be connectedtotheID line:
ID_PU_220K registerbitenablesan ID 220-kΩ pulluptoVUSB supply.
ID_PU_100K registerbitenablesan ID 100-kΩ pulluptoVUSB supply.
ID_GND_DRV registerbitenablesan ID 10-kΩ pulldown.
ID_SRC_16U registerbitenablesan ID 16-µA currentsourceon VUSB supply.
ID_SRC_5U registerbitenablesan ID 5-µA currentsourceon VUSB supply.
ID_WK_UP_COMP enablesan ID 9-µA currentsource(IID_WK_SRC )on VRTC supply. Copyright© 2010–2011,Texas InstrumentsIncorporated 71

VID_COMP1 Comp #4 Comp #3 Comp #2 Comp #1 RID ID VUSB ID_SRC_16UA Decoder/Debounce ID_GND ID_A ID_B ID_C ID_FLOAT VID_COMP2 VID_CMP4 VID_COMP3 OTG_ID TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com The ID wake-up comparatorisused when theTWL6030 deviceisinWAIT-ON orSLEEP state.Itallowsthestart up oftheTWL6030 devicewhen a USB cableA-plugisattached;thatis,when a pulldownresistortoground (ROTG_A) ispresenton theID line. Four comparators,suppliedby the VUSB regulator,are implementedto evaluatethe externalID resistance. Additionallogicbetween thosecomparatorsallowsthegenerationoffivedebounced interrupts(withfixed30-ms debouncing)as shown inFigure16. Figure16. ID ResistanceDetection Interruptsaregeneratedbased on theconditionslistedinTable17. Table17.InterruptGenerationConditions GENERATED INTERRUPT ID PIN LEVEL ID_GND ID_C ID_B ID_A ID_FLOAT VID < VID_CMP1 1 0 0 0 0 VID_CMP1 < VID < VID_CMP2 0 1 0 0 0 VID_CMP2 < VID < VID_CMP3 0 0 1 0 0 VID_CMP3 < VID < VID_CMP4 0 0 0 1 0 VID > VID_CMP4 0 0 0 0 1 Itispossibletouse theGPADC tomonitorthevoltageon theID line(channel14).A 6.875-Vmaximum voltage on theID linecorrespondstoa 1.25-Vmaximum dynamic attheinputstageoftheGPADC converter,allowinga 6.0-Vmaximum measurement. VBUS Line The VBUS wake-up comparatorisused when theTWL6030 deviceisinPRECHARGE, WAIT-ON, SLEEP, or ACTIVE state.ItallowsstartupoftheTWL6030 devicewhen a USB cableplugisattached;thatis,when a VBUS voltagelevelof3.6V minimum ispresenton theVBUS line. The VUSB regulatorcan be enabledordisabledby theVBUS wake-up comparatoruntilthefirstI2C writeaccess to the VUSB resourcestateregister(VUSB_CFG_STATE). Note thatthe VUSB regulatoriscontrolledby the VBUS wake-up comparatoronlywhen theNRESPWRON signalislow.

72 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 The ACA comparatorsand 16-µA currentsourcecan be enabledordisabledby theVBUS wake-up comparator untilthe firstI2C writeaccess to the OTG correspondingregisters.Note thatACA featureiscontrolledby the VBUS wake-up comparatoronlywhen NRESPWRON signalislow. The followingpullupand pulldownresistorsand currentsinks/sourcescan be connectedtotheVBUS line:

VBUS_CHRG_VBAT bitenablesa VBUS 2-kΩ pulluptotheVBAT supply.
VBUS_CHRG_PMID bitenablesa VBUS 2-kΩ pulluptotheCHRG_PMID supply.
VBUS_DISCHRG bitenablesa VBUS 10-kΩ pulldown.
VBUS_IADP_SRC bitenablesa VBUS 1.4-mA currentsourceon theVANA supply.
VBUS_IADP_SINK bitenablesa VBUS 1.5-mA currentsink.
RA_BUS_IN resistorispresentpermanentlyand isa combinationofallparallelresistorbridgesimplemented on VBUS inthevariousIPssuch as backup battery,OTG, and charger.
RVBUS_LKG representstheTWL6030 internalleakage. RelatedtotheOTG 1.3revision,fourcomparatorssuppliedon theVANA regulatorare implementedtodetect VBUS linevoltagelevel. In the OTG 2.0 revision,onlyone comparatorisrequiredforthe sessionvaliddetection(VOTG_SESS_VLD) suppliedalsoon theVANA domain.InadditiontheVA_VBUS_VLD comparatorcan be used todetecta possible VBUS short-circuitcondition. The TWL6030 deviceembeds theOTG 2.0optionalfeaturesrelatedtotheVBUS ADP probingand sensing,via two additionalcomparatorssuppliedon VANA (VADP_PRB, and VDAP_SNS). Seven comparatorsallowdetectionofthefourOTG 1.3and thethreeOTG 2.0debounced interrupts:
VA_VBUS_VLD (OTG 1.3/OTG 2.0)– fixed30 ms debouncing
VB_SESS_VLD (OTG 1.3)– fixed30 ms debouncing
VA_SESS_VLD (OTG 1.3)– fixed30 ms debouncing
VB_SESS_END (OTG 1.3)– fixed30 ms debouncing
VOTG_SESS_VLD (OTG 2.0)– fixed30 ms debouncing
VADP_PRB (OTG 2.0)– fixed2x 30 µs debouncing
VADP_SNS (OTG 2.0)– fixed2x 30 µs debouncing Itispossibleto use the GPADC to monitorthe voltageon the VBUS line(channel10).A 6.875-Vmaximum voltageon theVBUS linecorrespondstoa 1.25-Vmaximum dynamicattheinputstageoftheGPADC converter, allowinga 6.0-Vmaximum measurement.Formore information,see GENERAL-PURPOSE ADC . NOTE
Ifthesystemswitchesoff,VUSB stayson ifVBUS isstillconnected.
When NRESPWRON isreleased,onlysoftwareaccessesenabletheregulator,ifnotpreviously enabledby theVBUS wake-up comparatorinPRECHARGE state.
The VUSB regulatorisa dualinputsupplyLDO. The VUSB regulatorenableisindependentof theovervoltagecondition.
When a VBUS overvoltageconditionoccurs,the CHRG_PMID inputswitchis automatically opened,protectingtheVUSB LDO frompossibleovervoltagestresses.
When neitherthe VBAT nor PMID inputsupplyisselected,the VUSB LDO cannot outputa propervoltage,even ifitscontrolenableisset(seetheVUSB_CFG_TRANS register).
Softwareshould keep monitoringthe VBUS overvoltageconditionand turnoffthe VUSB regulatorwhen necessary.
The VBUS detectionmechanism worksonlywhen VANA supplyispresent: – TWL6030 SLEEP state– VANA shouldremainactive. – TWL6030 ACTIVE state– VANA isalwayson.
For ADP detection,softwarecan use the TWL6030 embedded mechanism or directlyuse the outputofthecomparatorswiththeirassociatedinterrupts. Copyright© 2010–2011,Texas InstrumentsIncorporated 73

VBUS_IADP_SRC VBUS VADP_PRB Time interval measurement Upper limit Lower limit VBUS_IADP_SINK ADP probing and sensing control 32.768-kHz crystal clock ADP interrupt ADP_MODE[1:0] T_ADP_HIGH[7:0] T_ADP_LOW[7:0] T_ADP_RISE[7:0] VADP_SNS TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com ADP on VBUS Line The ADP featureallowsthedevicetodetectwhen a remotedeviceisattachedordetached.The ADP detectsthe change in VBUS capacitancethatoccurs when two devicesare attachedor detached.The capacitanceis detectedby firstdischarging(VBUS_IADP_SINK) theVBUS lineand thenmeasuringthetimeittakesforVBUS tochargetoa VADP_PRB voltagelevelwitha VBUS_IADP_SRC currentsource.The change inthecapacitance isdetectedby lookingfora change intheT_ADP_RISE chargetime.ThisoperationiscalledADP probing,which isallowedonlyforan A-device. Ifan A-deviceisattachedtoa B-device,and bothsupportADP features,theA-deviceperformsADP probingand theB-deviceperformsADP sensing.DuringADP sensing,theB-devicesearchesforADP probingactivityon the VBUS line.IfADP probingactivityisdetected,theB-devicedeterminesthattheA-deviceisstillattached. As shown inFigure17,theADP module has timingregisterbits(T_ADP_HIGH, T_ADP_LOW, T_ADP_RISE), controllogic,a currentsource(VBUS_IADP_SRC), a currentsink(VBUS_IADP_SINK), and two comparators: ADP probing(VADP_PRB) and ADP sensing(VADP_SNS). Figure17. AttachDetectionProtocolScheme Figure18 shows theADP timingdiagram.

74 Copyright© 2010–2011,Texas InstrumentsIncorporated

VADP_PRB VADP_SNS VADP_DSCHRG T_ADP_SINK TA_ADP_PRB or TB_ADP_PRB T_ADP_RISE Time SWCS045-018 32.768-kHz crystal clock ADP interrupt ADP_MODE[1:0] 00 01 Comp (VADP_SNS) T_ADP_SNS TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Figure18. ADP Timing Diagram ADP_MODE[1:0] OPERATION 00 ADP digitalmodule isdisabled. 01 ADP digitalmodule isenabled. 10 ADP probingmode as an A-deviceisenabled. DuringADP sensingmode, the VADP_SNS comparatorisused.The digitalmodule monitorsthe comparator outputtoensurethatittogglesand thetimedurationbetween therisingedge ofthecomparatoroutputsignalis shorterthanT_ADP_SNS. Ifthereisno new risingedge withintheT_ADP_SNS period,themodule generates an ADP interrupt. Figure19 shows theADP sensingtimingdiagram. Figure19. ADP Sensing Timing Diagram DuringADP probing,theVADP_PRB comparatorisused.The timeintervalmeasurement counterisreset,the comparatorisenabledand theVBUS_IADP_SINK currentsinkisturnedon forT_ADP_SINK. The T_ADP_SINK timeislongenough todischargetheVBUS voltagebelow VADP_DSCHG (guaranteedby design).Afterthat,the currentsinkisturnedoff,thecurrentsourceVBUS_IADP_SRC isturnedon,and thetimeintervalmeasurement counterstartsto count32.768-kHzcrystalclockcycles.When the VBUS voltagereachesVADP_PRB or the countervaluereaches255 cycles,the currentsourceisturnedoff,the timeintervalmeasurement counteris stopped,and thecomparatorisdisabled.Ifthemeasured timeintervalvalueislowerthanT_ADP_LOW[7:0] or higherthan T_ADP_HIGH[7:0],an interruptisgenerated.Softwaresetsthe limitvaluesso thatthe operation fulfillsrequirementsoftheOTG 2.0specification.Figure20 shows theADP probingtimingdiagram. Copyright© 2010–2011,Texas InstrumentsIncorporated 75

32.768-kHz crystal clock ADP interrupt ADP_MODE[1:0] 00 10/11 EnaComp VBUS_IADP_SINK VBUS_IADP_SRC Comp (VADP_PRB) T_ADP_SINK T_ADP_RISE Asynchronous T_ADP_SINK TA_ADP_PRB or TB_ADP_PRB 00 10/11 >T_ADP_HIGH or 255*Tclk TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure20. ADP Probing Timing Diagram GAS GAUGE The gas gauge, alsocalledthe currentgauge, measures the currentfrom the batteryor the currentintothe battery.An analog-to-digitalconverter(ADC) (Coulomb counter)isrequiredto measure the voltageover the externalRsense sense resistor.Thisresistorisconnectedto the negativesideof the battery.The integration periodoftheADC isprogrammable from 3.9to250 ms. The gas gauge works continuously,which means that the new measurement startsimmediatelyafterthe previousresultbecomes available.The averagingand the compensationaredone by theTWL6030 digitalmodule butrequiressoftwarecontrols. The main featuresofthegas gauge are:

Currentrange:±6.2A(with10-mΩ sense resistor)
ADC clockfrequency:32.768kHz
Data size:13 resultbits+ 1 signbit,2’s complement format(with250-ms integrationperiod)
Integrationperiods:250 ms (default),62.5ms, 15.6ms, 3.9ms
Batterydischarginggivesnegativeresult(signbit= 1)
Externalsense resistorisneeded (willbe connectedthenegativesideofbattery) Figure21 shows a blockdiagramofthegas gauge.

76 Copyright© 2010–2011,Texas InstrumentsIncorporated

Rs /c68/c83Coulomb counter 13 bits Digital filter 13 bits+Sign1 bit Accumulator Calibration Integrator Sample counter Registers Digital control Autocalibration switches Analog Digital GGAUGE_RESP GGAUGE_RESN TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Figure21. Gas Gauge Block Diagram Autocalibration Autocalibrationisenabledby software.Duringautocalibration,thegas gauge performseightmeasurements so thattheinputsfortheADC areshort-circuited.The resultindicatestheoffseterrorofthegas gauge.The resultis storedintheCC_OFFSET[9:0] registerbitsand thecompletionofthemeasurement procedureisindicatedwith theCC_AUTOCAL interrupt.Softwaremust read theoffseterrorresultand use thattocompensate theactual measurement results.The CC_CAL_EN bitselfclearswhen thecalibrationcompletes.The gas gauge must be enabled whilecalibrationruns.The temperaturevariationchanges the offseterror,so the recalibrationis preferredduringoperation. Auto-Clearand Pause The auto-clearfunctionisused inthesequence ofchangingfromone integrationperiodtoanotherone.Before changingthe integrationperiod,the CC_PAUSE bitmust be setto 1. Settingthe CC_AUTOCLEAR bitto 1 clears the CC_OFFSET[9:0], CC_SAMPLE_CNTR[23:0], and CC_ACCUM[31:0] registers.The CC_AUTOCLEAR bitisself-clearedonce theregistersarereset. SettingtheCC_PAUSE bitto1 keeps theanalogfromupdatingtheintegrator,accumulator,and sample counter registers.The integratorcontinuestorun.Ifan integrationperiodends whiletheCC_PAUSE bitis1,thevalue thatisnormallywrittentotheseregistersislostbecause thenextintegrationperiodstartsautomatically. Dithering The FGDITHS bitissetto1 toenableditheringintheADC, whichkeeps idletonesfrombeinggeneratedwitha DC inputvalue.The FGDITHS bitisnotaffectedby theCC_AUTOCLEAR bit.Use theFGDITHR bittodisable thedithering.The ditheringfeaturestatusisavailableintheFGDITH_EN bit. OperationwithSoftware Softwaremust firstsetthecorrectintegrationperiod,enablethegas gauge,and performthecalibrationtoderive theoffseterrorand use theerrortomake correctionstothemeasurement results.The gas gauge entersnormal operationautomaticallywhen calibrationcompletes.Afterthat,softwarecan read the sample counterand accumulatorresultsand calculatetheenergyaccordingly. To recordthecurrentconsumptionwaveform,softwaremust seta timeroftheintegrationperiodtoread every integrationsample result.IntegrationregisterCC_INTEG[13:0]alwaysstorestheresultofthelastmeasurement. Copyright© 2010–2011,Texas InstrumentsIncorporated 77

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com GENERAL-PURPOSE ADC The GPADC consistsof a 10-bitADC combined witha 17-inputanalogmultiplexer.The ADC implementation consistsofa successiveapproximationconversion.The GPADC enablesthehostprocessortomonitora variety ofanalogsignalsusinganalog-to-digitalconversionon theinputsource.Aftertheconversioncompletes,thehost processorreadstheresultsoftheconversionthroughtheI2C interface. The GPADC supports17 analoginputs:7 oftheseinputsare availableon externalballsand theremainingare dedicatedtointernalresourcemonitoring.Three oftheseven externalinputsareassociatedwithcurrentsources or referencevoltagesallowingmeasurements of resistiveelements (batterytype and temperatureor other thermalsensor).The referencevoltagesare availablewhen the GPADC isenabled.The referencevoltage GPADC_REF4 can be disabledby registerbit. GPADC_IN0 isassociatedwitha currentsourceof7 µA. An additional15-µA currentsourcecan be enabledby registerbit.A comparatorconnectedtothisinputisintendedtodetectthepresenceor absence ofthebattery (resistancetoground< 130 kΩ).The detectionresultisavailableattheBATREMOVAL ball. GPADC_IN1 and GPADC_IN4 are associatedwitha voltagereferenceequal to the ADC referenceand are intendedto measure temperaturewith an NTC sensor.In addition,a detectionmodule is connected to GPADC_IN1 topermanentlymonitorthetemperatureand gatethechargeforthebattery. The monitoredinternalanalogparametersare:

Main batteryvoltage(VBAT)
Backup batteryvoltage(VBKP)
VAC/VBUS chargingsourcevoltage
Main batterychargecurrent(ICHG)
Thermalmonitoringmechanisms (HOTDIE1, HOTDIE2)
USB OTG ID voltagelevel The threeexternalinputsassociatedtothecurrentsourcesare:
GPADC_IN0: Main batterytypedetection(identificationresistorinbatterypack)
GPADC_IN1: Main batterytemperaturemeasurement (thermistorinbatterypack)
GPADC_IN4: Otherresistivesensor The conversionrequestsare initiatedby thehostprocessor,eitherby softwarethroughtheI2C or by hardware througha dedicatedexternalballGPADC_START. This lastmode is usefulwhen real-timeconversionis required.An interruptsignalisgeneratedattheend-of-sequenceoftheconversions. Therearetwo kindsofconversionrequests:
Real-timeconversionrequest(SRT)
Asynchronousconversionrequest(SW) Real-TimeConversion Request (SRT) The GPADC isactivatedwhen GPADC_START isasserted.When thisoccurs,theGPADC digitalcontrolfetches the real-timeselectionregisterto determinewhich channelsmust be sampled and converted.A sequence of conversionconsistsof 1 to 17 channelsto convertand processesallqueued, selectedchannelsone after another,startingwithchannel0 and endingwithchannel16.At theend ofeach conversion,theGPADC writes the conversionresultintothe correspondingresultsregister.An INT interruptisgeneratedat the end of the sequence ofconversions. Ifa GPADC_START real-timerequestoccurswhilea software-initiatedconversionsequence isrunning,the ongoing software conversionis aborted,the real-timeconversionsequence is started,and a new software-initiatedconversionisrescheduledattheend oftheGPADC_START sequence. Asynchronous Conversion Request (SW) Software can also requireconversionsasynchronouslywith respect to the GPADC_START ball for general-purposeuse.These conversioncasesarenotcriticalintermsofstart-of-conversionpositioning.

78 Copyright© 2010–2011,Texas InstrumentsIncorporated

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 General-purposeconversionsdo not requirea resultgranularityin time lower than the durationof the all-channelsconversionsequences.While requiringa general-purposeconversion,thereisno need to specify channels:allchannelsare converted.Thisrequestisactivewhen a writeaccess to the togglebitSP1 inthe GPADC registeroccurs, and an INT interruptis generated after the conversion sequence. A GPADC_START-initiatedconversion(SRT) has a higherprioritythanthesoftware-initiatedconversions. Ifa softwarerequestoccurswhilea GPADC_START-initiatedsequence (SRT) isrunning,thesoftwarerequestis placedon holdand theongoingreal-timesequence continuesuntilitcompletesand theconverteddataisstored inthe real-timededicatedregisters.An INT interruptisthen generatedand sentto the processor.The digital controlexecutesthesoftwarerequestwhen thereal-timesequence ofconversionscompletes.An INT interruptis thengenerated. Channels description The differentADC channelsaresummarized inthefollowingtable. CH TYPE POWER DOMAIN SCALER OPERATION

0 External VRTC No Batterytype,resistorvalue

1 External VRTC No Batterytemperature,NTC resistorvalue

2 External Special 1.875/1.25V Audioaccessory/generalpurpose

3 External VANA No Generalpurpose

Temperaturemeasurement/general4 External VANA No purpose

5 External VANA No Generalpurpose

6 External VANA No Generalpurpose

7 Internal 5/1.25V or6.25/1.25V Main battery 8 Internal 6.25/1.25V Backup battery 9 Internal 11.25/1.25V Externalchargerinput 10 Internal 6.875/1.25V VBUS 11 Internal 1.875/1.25V VBUS chargingcurrent

12 Internal No Dietemperature

13 Internal No Dietemperature

14 Internal 6.875/1.25V USB ID line 15 Internal 6.25/1.25V Testnetwork 16 Internal 4.75/1.25V Testnetwork NOTE

Channel11 scalar(ICHG)isplacedintheanalogchargerand alwaysenabled.
Channel 11 operationalamplifierand path switchis locatedin the analog GPADC and controllablewiththeGPADC_SCALER_EN_CH11 registerbit.
VANA must be on toavoidleakageon GP inputs3,4,5,and 6.
Itiscurrentlynotpossibletomeasure GPADC_IN2 up to1.25V, withoutenablingthescalarfirst (upto1.875V). The followingequationprovidestherelationshipbetween TWL6030 IC diejunctiontemperatureand theGPADC registersreaddata:Tj(°C) = (GPADC 10CODE –671)× 0.465+ 27 withthefollowingparameters:
GPADC 10CODE isthedecimalcode readfromtheGPADC register.
671 isthedecimalcode readfromtheGPADC registerwhen thejunctiontemperatureis27°C.

VAUX3_IN (from the battery) TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com VIBRATOR DRIVER AND PWM SIGNALS Vibrator InsteadofusingtheVAUX3 LDO fora genericvoltagesupply,itcan be used as a vibratormotor driver.The outputvoltageofthisregulatorisprogrammable,based on a nominal4-Hz cycle.A 16-Hz inputclockisreceived from theclockgenerator(32.768-kHzcrystalclockresynchronizedon theRC 6-MHz clock).The outputvoltage levelisthroughregistersand theLDO can provideup to200 mA. The dutycycleof the nominal4-Hz frequencyiscontrolledthroughregisterand can be 25%, 50%, 75%, and 100%. Thisvibratordriverallowsa softturnon (500µs maximum) and turnoff(2ms maximum). Figure22 shows a blockdiagramofthevibratormotordriver. Figure22. Block Diagram ofVibratorMotor Driver PWMs The PWM1 and PWM2 digitaloutputsprovidePWM signalson the 1.8-VI/Odomain.Those outputscan be activealsowhen thesystemisinSLEEP state.The currentdrivecapabilityofeach PWM bufferis4 mA. Each of the PWMx ON/OFF positionsisdeterminedby the registervalues(PWMxON, PWMxOFF) withinthe range0–127 or0–63. The number ofclockcyclesina PWM periodhas two availablevalues:

64 clockcycles
128 clockcycles ThisiscontrolledwiththePWMx_LENGTH bitinthePWMxON register. The clockisreceivedonlywhen thecontrolbitPWMxEN issetintheTOGGLE3 register.Thisclockenableis necessaryforcurrentsavingwhen PWM isnotused. To geta cleanOFF state(withreseton registerswhen PWM isdisabled),firstthePWMxR bitmust be setand thentheclockcan be disabledwithPWMxEN.

PWM1ON = 0x05 PWM1OFF = 0x7C PWM2OFF = 0x7F 0 1 2 3 4 5 I28 CLK 0 1 2 3 PWM2ON = 0x02 SWCS045-028 124 125 126 127 OFF ON OFFOFF OFF ON TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 NOTE

The PWMx output signalis constantlyON by settingPWMxON[6:0] equal to PWMxOFF[6:0].
The followingconditionsareprohibited: – PWMx_ON[6:0] > PWMx_OFF[6:0] – 00H ON timingsetting Figure23. PWM Timings With 128 Clock Cycles Setting When a new ON/OFF change isappliedduringblinking:
Ifthe PWM periodisprogrammed on 64 clockcyclesand changed to get 128 clockcycles,the ongoing countergoes up to128,and thenextPWM periodsis128 clockcycles.
IfthePWM periodisprogrammed on 128 clockcycles,changed toget64 clockcycles,and thecounteris below64,thePWM periodstopsat64 clockcycles.The nextperiodsare64 clockcycles.
IfthePWM periodisprogrammed on 128 clockcycles,changed toget64 clockcycles,and thecounteris above 64,thePWM periodisaborted.The nextperiodsare64 clockcycles. DETECTION FEATURES The TWL6030 devicesupportsthefollowingdetectionfunctions:
Detectionof SIM card insertion/extractionwith debouncing capability,automaticpower shutdown on extractiondetection(configurable)
Detectionof MMC card insertion/extractionwith debouncing capability,automaticpower shutdown on extractiondetection(configurable)
Detectionofbatterypresence/removal Cards Detection:SIM/MMC The TWL6030 deviceprovidestheregulatedsupplyvoltage(VUSIM) fortheSIM cardand VMMC fortheMMC cardand thecircuitrytodetecttheinsertionorextractionoftheSIM cardorMMC card.An interruptisgenerated when thereisa plug/unplugdetection.When the SIM card or MMC card isinserted,a mechanicalcontact connected to the TWL6030 device terminalSIM or MMC is trippedand afterdebouncing an interruptis generated.The SIM cardand MMC cardpresencedetectionlogicmust be activeeven when thesystemisinidle mode, and thenthedebouncinglogic(programmable)isbased on the32-kHz low-activityclock.The signalfrom SIM or MMC is preprocesseddepending on the detectionsystem and on the internalpullup/pulldown Copyright© 2010–2011,Texas InstrumentsIncorporated 81

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com configuration.When a cardinsertionisdetected,theregulatorVUSIM or VMMC must be enabledby software. When a card is extracted,the correspondingregulatoris turnedoffautomatically.This functionalityis still configurable(enabledordisabled)by software.The SIM orMMC cardplugisdetectedfromany stateofthechip (WAIT-ON, SLEEP, or ACTIVE). Both carddetectionsare alwaysenabledand theirrespectiveinterruptcan be masked orunmasked. BatteryRemoval Detection The TWL6030 deviceprovidesthemeans todetectthepresenceorremovalofthebattery.The presenceofthe batteryisdetectedby a comparatorassociatedwitha currentsourceconnectedtotheGPADC_IN0 by sensing thevoltageon thisball(resistortoground or open circuitR > 130 kΩ).The BATREMOVAL signalisactivated when thepresenceor removalofthebatteryisdetected.Debouncing occurson thebatterydetectioncircuitry. Thisdebouncingcan be bypassed by a registerbit(thedefaultvalueisbypass).Batterydetectioncircuitrycan be enabledor disabledby a registerbit.The batterydetection(defaultconfiguration)can be combined withthe SIM detection.Depending on thestateof2 registerbits,theBATREMOVAL ballindicatesthepresenceofthe batteryonly,thepresenceofSIM only,orthepresenceofbothSIM and battery.By default,the2 registerbitsare settoindicatethebatterypresenceonly. The polarityisdefinedas following:

Highlevel:Batteryand/orSIM present
Low level:Batteryand/orSIM removed THERMAL MONITORING A thermalprotectionmodule monitorsthetemperatureofthedevice.Itgeneratesa warningtothesystem when excessivepower dissipationoccursand shutsdown theTWL6030 deviceifthetemperaturerisestoa valueat whichdamage can occur. Thus,therearetwo protectionlevels:
Hot-die(HD) function,whichsends an interrupttosoftwaretoclosethenoncriticalrunningtasks
Thermalshutdown(TS)function,whichdirectlystartstheTWL6030 deviceswitch-off The silicontechnologyused tobuildtheTWL6030 devicesupportsa maximum operatingtemperatureof150 °C. Regardingpackagingtechnology,a continuousoperationabove 125°C would requirespecialpackagingand must be avoidedtomeet 100k hourslifetime. By default,thermalprotectionisalwaysenabledexceptinBACKUP orOFF state.Itisnotpossibletodisableit by softwareintheSLEEP state. The TWL6030 deviceintegratestwo hardware detectionmechanisms to monitorand alertsoftwarethatthe junctiontemperatureisrisingand must takeactionto reduce consumption.Those mechanisms are placedon two oppositesidesofthechipand closetotheLDOs and SMPSs. Even iftherearetwo identicalthermalfeature instanceson the chip,itis always consideredby the specificationto be unique.In additionto those HD detections,another HD featureis embedded in the charger:The chargerHD is specifiedin BATTERY CHARGING and does notbehave exactlythesame way as describedinHot-DieFunction. Differentthresholdsare implemented.When a thresholdisreached,an interruptisissued.To avoidparasitic interrupt,debouncingisimplementedwithintheHD detectionfunction. The TWL6030 deviceintegratesa thermalshutdown mechanism to shutdown the devicewhen the junction temperaturereaches a certainlevelto avoid irreversibledie damage. The risingand fallingtemperature thresholdshave a differenceof 10°C minimum. The HD providessome interruptmechanism and threshold registerstoselectthetemperatureinterruptlevel. Hot-DieFunction The HD detectormonitorsthetemperatureofthedieand providesa warningtothehostprocessorthroughthe interruptsystem when temperaturereachesa criticalvalue.The thresholdvaluemust be setbelow thethermal shutdownthreshold.Hysteresisisadded totheHD detectiontoavoidthegenerationofmultipleinterrupts. The integratedHD functionprovidesan earlywarningovertemperatureconditiontothehostPM software.This monitoringsystemisconnectedtotheinterruptcontroller(INTC)and can send an interruptwhen thetemperature ishigherthantheprogrammed threshold.

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 The TWL6030 deviceallowstheprogrammingoffourjunction-temperaturethresholdstoincreasetheflexibilityof thesystem:innominalconditions,thethresholdtriggeringtheinterruptcan be setfrom117°C to130°C. The HD hysteresisis10°C minimum intypicalconditions. When an interruptistriggeredby thepower-management software,immediateactionmust be takentoreduce theamount ofpower drawn fromtheTWL6030 device(forexample,noncriticalapplicationsmust be closed). The interruptgenerationisdebounced toavoidparasiticinterrupt. Thermal Shutdown The thermalshutdown detectormonitorsthe temperatureon the die.Ifthe junctionreachesa temperatureat whichdamage can occur,a switch-offtransitionisinitiatedand a thermalshutdown eventiswrittenintoa status register. To avoidinterruptsat restart,the system cannot be restarteduntilthe die temperaturefallsbelow the HD threshold. The thermalshutdown monitorfunctionisintegratedtogeneratean immediate,unconditionalTWL6030 device switch-offwhen an overtemperatureconditionexists.Thisfunctionmust be distinguishedwiththeearlywarning providedtosoftwareby theHD monitorfunction. In the TWL6030 device,the threshold(Tj rising)of the thermalshutdown is 148°C nominal.The thermal shutdown hysteresisis10°C intypicalconditions.The resetgenerationisdebounced.The thermalshutdown functioncan be masked onlyinSLEEP state(theTMP_CFG_TRANS register)and intestmode. CONTROL INTERFACE (I2C ,MSECURE, INTERRUPTS) I2C interfaces The TWL6030 deviceprovidestwo serialcontrolinterfaces:One isthegeneral-purposeI2C interface(CTL-I2C) forread-and-writeaccesstotheconfigurationregistersofallsystem resources,and theotheristheserialcontrol interface(SR-I2C)dedicatedtoSmartReflexapplications,such as dynamic voltagefrequencyscaling(DVFS) or adaptivevoltagescaling(AVS). BothcontrolinterfacescomplywiththeHS-I2C specificationand supportthefollowingfeatures:

Mode: Slaveonly(receiverand transmitter)
Speed – Standardmode (100kbps) – Fastmode (400kbps) – High-speedmode (limitedto2.4Mbps maximum)
Addressing:7-bitmode addressingdevice They do notsupportthefollowingfeatures:
10-bitaddressing

D A D D A D D A D D A D D A D D A D D D W A C K DAD: Device address RAD: Register address DAT: Data R A D R A D R A D R A D D D A D R A D A K D A T D A SDA SCL Slave drives SDA Master drives SDA S T A R T D A D D A D D A D D A D D A D D A D A C K D A D W R I T E R A D R A D R A D R A D R A D R A D R A D R A D A C K D A T D A T D A T D A T D A T D A T D A T D A T A C K S T O P SWCS045-023 SDA SCL D A D S T A R T D A D D A D D A D D A D D A D A C K D A D W R I T E R A D R A D R A D R A D R A D R A D R A D R A D A C K D A D D A D D A D D A D D A D D A D D A D D A D R E A D A C K S T A R T D A T D A T D A T D A T D A T D A T D A T D A T A C K S T O P SWCS045-024 SDA SCL D A D S T A R T D A D D A D D A D D A D D A D A C K D A D W R I T E R A D R A D R A D R A D R A D R A D R A D R A D A C K D A T D A T D A D D A T D A T D A T D A T D A T A C K D A T D A T D A T D A T D A T D A T D A T D A T A C K S T O P TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Single-ByteAccess A writeaccessisinitiatedby a firstbytethatincludestheaddressofthedevice(7MSBs) and a writecommand (LSB),a second bytethatprovidestheaddress(8bits)oftheinternalregister,and thethirdbytethatrepresents thedatatobe writtenintheinternalregister. A readaccessisinitiatedby:

A firstbyte,includingtheaddressofthedevice(7MSBs) and a writecommand (LSB)
A second byte,providingtheaddress(8bits)oftheinternalregister
A thirdbyte,includingagaintheaddressofthedevice(7MSBs) and thereadcommand (LSB) The devicerepliesby sendinga fourthbyterepresentingthecontentoftheinternalregister. Figure24 shows a writeaccesssingle-bytetimingdiagram. Figure24. I2C WriteAccess SingleByte Figure25 shows a readaccesssingle-bytetimingdiagram. Figure25. I2C Read Access SingleByte Multiple-ByteAccess toSeveralAdjacentRegisters A writeaccessisinitiatedby:
A firstbyte,includingtheaddressofthedevice(7MSBs) and a writecommand (LSB)
A second byte,providingthebase address(8bits)oftheinternalregisters The followingN bytesrepresentthedatatobe writtenintheinternalregister,startingatthebase addressand incrementedby one ateach databyte. Figure26 shows a multiple-bytewriteaccess. Figure26. I2CWrite Access MultipleBytes A readaccessisinitiatedby:
A firstbyte,includingtheaddressofthedevice(7MSBs) and a writecommand (LSB)
A second byte,providingthebase address(8bits)oftheinternalregister
A thirdbyte,includingagaintheaddressofthedevice(7MSBs) and thereadcommand (LSB)

D A D S T A R T D A D D A D D A D D A D D A D A C K D A D W R I T E R A D R A D R A D R A D R A D R A D R A D R A D A C K A C K D A D D A D D A D D A D D A D D A D D A D D A D R E A D D A T D A T D A T D A T D A T D A T D A T D A T S T O P A C K A C K S T A R T D A T D A T D A T D A T D A T D A T D A T D A T TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 The devicerepliesby sendinga fourthbyterepresentingthecontentoftheinternalregisters,startingatthebase addressand nextconsecutiveones. Figure27 shows a multiple-bytereadaccess. Figure27. I2C Read Access MultipleBytes Secure Registers Some registersof the TWL6030 devicecan be protectedby restrictingtheiraccess inwritemode to software runninginthesecuremode ofthehostreadaccesstoprotectedregisters.Secure accessisenabledordisabled by theMSECURE controlsignal. The followingcomponents oractionscan be protected:

AllRTC registers
64 bitsofgeneral-purposememory (8x 8)inthebackup domain named VALIDITY The readaccessesareindependenttotheMSECURE value. When MSECURE islogicallevel1,allreadand writeaccessesareauthorized;when MSECURE islogicallevel 0,onlyreadaccessesareauthorized. Thissecurityfeature(MSECURE detection)isenabledand disabledby an EPROM bit. Interrupts The INT signal(activelow)warns thehostprocessorofany eventoccurringon theTWL6030 device.The host processorthenpoolstheinterruptfrom theinterruptstatusregisterthroughI2C toidentifytheinterruptsource. Each interruptsource can be individuallymasked throughthe interruptmask lineregistersand mask status registers. Ifinterruptsoccurwhilethestatusregistersare notcleared,thestatusregistersare notupdatedimmediately. Instead,theinterruptsareheldpendingina second stageofshadow registers,waitingforallpreviousinterrupts tobe clearedfirst.When theinterruptlinegoes low again,operatedjustafterthefirstsetofinterruptsclear,all statusregistersareupdatedwiththosependinginterruptsources,coming directlyfromtheshadow registers. To clearbothinterruptsand registerstatus,a writeinthestatusregistersmust be done.Each writehas thesame effect(interruptlinegoes highand allstatusregistersare cleared).Thisimpliesthatthe interruptsubroutine acquiresthethreestatusregistersbeforeacknowledgingtheinterrupttoavoidlosingany interruptsources. NOTE
An interruptassociatedwitha functionshould be masked beforeenablingor disablingthe feature;otherwise,itmightgeneratea falseinterruptdirectlylinkedtothestatechange ofthe featureand notrelatedtoan externaldetectionevent(forexample,BAT_VLOW interruptwith VBATMIN_HI comparator).
INT isalwaysactivelow.
When a TWL6030 interruptoccurs: – Softwareshouldfirstreadallstatusregisters,INT_STS_A, INT_STS_B, and INT_STS_C. – Executethesubroutinesrelatedtothereadinterrupts. – Cleartheinterruptstatusofallstatusregisters Copyright© 2010–2011,Texas InstrumentsIncorporated 85

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Table18.Interruptmapping # REG BIT SECTION INTERRUPT DESCRIPTION PWRON detection:Power-onbuttonpressedand released.Detection 00 A 0 PM PWRON performedon fallingand risingedges.InterruptsentinSLEEP or ACTIVE only,notinWAIT-ON. RPWRON detection:Remote power-onsignalchange.Interruptsentin01 A 1 PM RPWRON SLEEP orACTIVE only,notinWAIT-ON. Batteryvoltagelow:Batteryvoltagedecreasingand crossing02 A 2 PM BAT_VLOW VBATMIN_HI

03 A 3 RTC RTC_ALARM RTC alarmevent:Occursatprogrammed determinatedateand time

RTC periodicevent:Occursatprogrammed regularperiodoftime04 A 4 RTC RTC_PERIOD (everysecond orminute) Thermalmonitoring Atleastone ofthetwo embedded thermalmonitoringmodules detects05 A 5 HOT_DIEand shutdown a dietemperatureabove theHD detectionthreshold. Atleastone ofthefollowingpower resourceshas itsoutputshorted:

06 A 6 SMPS/LDO VXXX_SHORT V1V29, V1V8, V2V1, VCORE1, VCORE2, VCORE3, VMEM, VANA,

VAUX1, VAUX2, VAUX3, VCXIO, VDAC, VPP, VUSB 07 A 7 LDO VMMC_SHORT VMMC power resourcehas itsoutputshorted. 08 B 0 LDO VUSIM_SHORT VUSIM power resourcehas itsoutputshorted.

09 B 1 Detection BAT Batterydetectionplug/unplug

10 B 2 Detection SIM SIM cardplug/unplug

11 B 3 Detection MMC MMC cardplug/unplug

12 B 4 Reserved

End ofconversion:Completionofa realtimeand a GP software113 B 5 GPADC GPADC_RT_SW1_EOC (SW1) conversioncycle;resultavailable End ofconversion:Completionofa GP software2 (SW2) conversion14 B 6 GPADC GPADC_SW2_EOC cycle;resultavailable 15 B 7 Gas gauge CC_AUTOCAL Calibrationprocedurefinishedand theresultisavailableintheregister.

16 C 0 OTG ID_WKUP ID wake-up event(fromWAIT-ON/SLEEP states)

17 C 1 OTG VBUS_WKUP VBUS wake-up event(fromWAIT-ON/SLEEP states)

18 C 2 OTG ID ID eventdetectioninSLEEP/ACTIVE states

19 C 3 OTG VBUS VBUS eventdetectioninSLEEP/ACTIVE states

Interruptsourcecan be:

Chargerpluginsertionand removaldetection: – VAC_PLUG – VBUS_PLUG

20 C 4 Charger CHRG_CTRL • Watchdogs 32mn /32s interrupts:

– FAULT_WDG

Batteryinterrupts: – BAT_REMOVED – BAT_TEMP_OVRANGE

21 C 5 Charger EXT_CHRG Externalchargerfault(CHRG_EXTCHRG_STATZ)

Interruptsourcecan be:

CHARGERUSB_FAULT

22 C 6 Charger INT_CHRG • CHARGERUSB_THMREG

CHARGERUSB_STAT
CURRENT_TERM

23 C 7 Reserved

4.0ms Startup event 10.6 / 11.2ms Disable VPP, VAUX1, VAUX2, VAUX3, VMMC, VUSIM, VUSB if not already disabled. Shutdown event 550us 550us 550us 550us 550us 550us 550us 550us 550us 550us 550us 640us 7.2/7.8ms Enabled if BOOT3 =’1' 550us Disabled if BOOT3 = ’1'550us Can be max. 300ms if main battery and backup battery are empty 0/550us 550us TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Defaultboot sequences TWL6030B107 boot sequence ThisdeviceisOMAP4430 companion chip. Figure28. OMAP4430 DefaultStart-upand Shut-down Sequences Copyright© 2010–2011,Texas InstrumentsIncorporated 87

4.0ms Startup event 10.1 / 10.6ms Shutdown event 550us 550us 550us 550us 550us 550us 550us 550us 550us <10ms TBD Enabled if BOOT3 =’1' 550us TBDus Can be max. 300ms if main battery and backup battery are empty Other Regulators 550us Enabled if BOOT1 =’1' Disabled if BOOT1 =’1' 550us Disable VCORE3, VPP, VAUX2, VAUX3, VMMC, VUSIM, VUSB, VMEM (if BOOT1=’0') in sequence TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com TWL6030B1A4 boot sequence ThisdeviceisOMAP4460 companion chip. Figure29. OMAP4460 DefaultStart-upand Shut-down Sequences

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 RECOMMENDED EXTERNAL COMPONENTS MODULE COMPONENT (1) #(2) MANUFACTURER PART NUMBER VALUE PACK (3) SIZE (mm) INPUT POWER SUPPLIES EXTERNAL COMPONENTS PM/VBAT VDD tank 1 Murata GRM188R60J106ME84L 10 µF 603 1.6x 0.8x 0.8 capacitor(4) PM/VBAT VDD tank 2 Taiyoyuden JMK107BJ106 10 µF 603 1.6x 0.8x 0.8 capacitor(4) Backup Capacitor 1 SeikoInstruments XH414H-IV01E 0.08F ø4.8,1.4 Backup Capacitor 2 Matsushita(MEC) EECEP0E223AN 0.022F CRYSTAL OSCILLATOR EXTERNAL COMPONENTS 32 kHz Crystal 1 Citizen CM519 32.768kHz 3.2x 1.5x 0.9 32 kHz Crystal 2 Microcrystal CC7V-T1A 32.768kHz 32 kHz Crystal 3 Epson FC135 32.768kHz 32 kHz Crystal 4 NDK NX3215SA 32.768kHz 3.2x 1.5x 0.8 32 kHz Supplydecoupling 1 Murata GRM155R61A105KE15D 1 µF 402 1 x 0.5x 0.5 32 kHz Supplydecoupling 2 Taiyoyuden JMK105BJ105MV-F 1 µF 402 1 x 0.5x 0.5 32 kHz Crystaldecoupling 1 Murata GRM1555C1H220JZ01 22 pF 402 1 x 0.5x 0.5 32 kHz Crystaldecoupling 2 AVX 04025A120JAT2A 12 pF 402 1 x 0.5x 0.5 BANDGAP EXTERNAL COMPONENTS Bandgap Biasresistor 1 Rohm 0W06 1M 50ppm 1 M Ω 402 1 x 0.5x 0.5 Bandgap Biasresistor 2 Vishay 1 M Ω 603 1.6x 0.8x 0.8 Bandgap Capacitor 1 Murata GRM155R61C104K 100 nF 402 1 x 0.5x 0.5 Bandgap Capacitor 2 KEMET C0402C104K8PAC 100 nF 402 1 x 0.5x 0.5 GAS GAUGE EXTERNAL COMPONENTS Gas Gauge Resistor 1 Cyntec RL3720T-R010-FN 10 m Ω 815 GPADC EXTERNAL COMPONENTS GPADC NTC resistor 1 Murata NCL15WB473F03RC 47 kΩ 402 1 x 0.5x 0.5 I2C EXTERNAL COMPONENTS I2C interfacePullupresistor 1 SMPS EXTERNAL COMPONENTS SMPS Inputcapacitor 1 Murata GRM155R60J225ME15D 2.2µF 402 1 x 0.5x 0.5 SMPS Inputcapacitor 2 Taiyoyuden JMK105BJ225MV-F 2.2µF 402 1 x 0.5x 0.5 SMPS Inputcapacitor 3 Murata GRM155R60J475M 4.7µF 402 1 x 0.5x 0.5 SMPS Inputcapacitor 4 Taiyoyuden JMK107BJ475KA-T 4.7µF 603 1.6x 0.8x 0.8 SMPS Inputcapacitor 5 Murata GRM155R60J335UE97 4.7µF 402 1 x 0.5x 0.5 SMPS Outputcapacitor 1 Murata GRM188R60J106ME84L 10 µF 603 1.6x 0.8x 0.8 SMPS Outputcapacitor 2 Murata GRM188R60J106UE82J 10 µF 603 1.6x 0.8x 0.8 SMPS Ferritebead 1 Murata BLM18SG700TN1D – 603 1.6x 0.8x 0.8 SMPS Ferritebead 2 Murata BLM15PD121SN1 1300 mA 402 1 x 0.5x 0.5 SMPS Ferritebead 3 Murata BLM18KG221SN1 2200 mA 603 1.6x 0.8x 0.8 SMPS 0.8A Filterinductor 1 Murata LQM21PN1R0MC0 1 µH 805 2 x 1.25x 0.55 (volume minimization) SMPS 0.8A Filterinductor 2 TDK MLP2520S1R0M 1 µH 1008 2.5x 2 x 1 (performance maximization) (1) Component minimum and maximum tolerancevaluesareprovidedintheelectricalparameterssectionforeach IP. (2) The # column referstothefirst(1),second (2),and third(3)sourcesuppliers,forwhichtheIPsareeithersimulatedorcharacterized. (3) The PACK column describestheexternalcomponent package type. (4) The VDD tankcapacitorsfiltertheVBAT/VDD_B [i]inputvoltageoftheLDO and SMPS corearchitectures. Copyright© 2010–2011,Texas InstrumentsIncorporated 89

SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com SMPS 1.0 Filterinductor 1 Murata LQM2MPN1R0NG0 1 µH 806 2 x 1.6x 1 A,1.2A (volume minimization) SMPS 1.2 Filterinductor 1 Murata LQM32PN1R0MG0 1 µH 1210 3.2x 2.5x 1 A,1.5A,2 (performance A maximization) SMPS 1.2 Filterinductor 2 TOKO DFE322512C H1R0N (under 1 µH 1210 3.2x 2.5x 1.2 A,1.5A,2 (performance development) A maximization) SMPS 1.2 Filterinductor 3 TOKO DFE252012C H1R0N (under 1 µH 1008 2.5x 2 x 1.2 A,1.5A,2 (volume development) A minimization) SMPS 2 A Filterinductor 1 Coilcraft EPL2010-681MLB 0.68µH 2 x 2 x 1 (volume minimization) LDO EXTERNAL COMPONENTS LDO Inputcapacitor 1 Murata GRM155R60J105KE19D 1 µF 402 1 x 0.5x 0.5 LDO Inputcapacitor 2 Taiyoyuden JMK105BJ105MV-F 1 µF 402 1 x 0.5x 0.5 LDO Inputcapacitor 3 KEMET C0402C105K9PAC7867 1 µF 402 1 x 0.5x 0.5 LDO Outputcapacitor 1 Murata GRM155R60J105KE19D 1 µF 402 1 x 0.5x 0.5 LDO Outputcapacitor 2 Taiyoyuden JMK105BJ105MV-F 1 µF 402 1 x 0.5x 0.5 LDO Outputcapacitor 3 KEMET C0402C105K9PAC7867 1 µF 402 1 x 0.5x 0.5 LDO Outputcapacitor 4 Murata GRM155R60J155ME80D 2.2µF 402 1 x 0.5x 0.5 CHARGER EXTERNAL COMPONENTS Charger Filterinductor 1 FDK MIPS2520D1R0 1 µH 2520 Charger Filterinductor 2 Taiyoyuden CKP25201R0M-T 1 µH 2520 Charger Filterinductor 3 Taiyoyuden CKP2520D1R0 1 µH 2520 Charger Sense resistor 1 Panasonic ERJ2BWFR068X 68 m Ω 402 1 x 0.5x 0.5 Charger Sense resistor 2 Rohm UCR01 68 m Ω 402 1 x 0.5x 0.37 Charger Sense resistor 3 Tyco Electronics 219-908 68 m Ω 2512 Charger CHRG_VREF 1 KEMET C0603C225K4PAC 2.2µF 603 1.6x 0.8x 0.8 capacitor Charger CHRG_VREF 2 Murata GRM188R61C225UAAG 2.2µF 603 1.6x 0.8x 0.8 capacitor Charger VAC decoupling 1 Murata GRM155R61C104K 100 nF 402 1 x 0.5x 0.5 Charger VAC decoupling 2 Taiyoyuden LMK105BJ104MV-F 100 nF 402 1 x 0.5x 0.5 Charger VBUS decoupling 1 Murata GRM155R60J475M 4.7µF 402 1 x 0.5x 0.5 Charger VBUS decoupling 2 Taiyoyuden JMK107BJ475KA-T 4.7µF 603 1.6x 0.8x 0.8 Charger VBUS decoupling 3 Panasonic ECJINB1C475M 4.7µF 603 1.6x 0.8x 0.8 Charger CHRG_PMID 1 Murata GRM155R60J475M 4.7µF 402 1 x 0.5x 0.5 capacitor Charger CHRG_PMID 2 Taiyoyuden JMK107BJ475KA-T 4.7µF 603 1.6x 0.8x 0.8 capacitor Charger CHRG_PMID 3 Panasonic ECJINB1C475M 4.7µF 603 1.6x 0.8x 0.8 capacitor Charger CHRG_CSIN 1 Murata GRM155R61C104K 100 nF 402 1 x 0.5x 0.5 capacitor Charger CHRG_CSIN 2 Taiyoyuden LMK105BJ104MV-F 100 nF 402 1 x 0.5x 0.5 capacitor Charger CHRG_CSOUT 1 Murata GRM188R60J106ME84L 10 µF 603 1.6x 0.8x 0.8 Charger CHRG_CSOUT 2 Taiyoyuden JMK107BJ106 10 µF 603 1.6x 0.8x 0.8 Charger CHRG_SW 1 Murata GRM155R61C103KA01D 10 nF 402 1 x 0.5x 0.5 capacitor Charger CHRG_SW 2 Taiyoyuden TMK105BJ103MV 10 nF 402 1 x 0.5x 0.5 capacitor Charger CHRG_AUXPWR 1 Murata GRM155R61A105KE15D 1 µF 402 1 x 0.5x 0.5

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 Charger CHRG_AUXPWR 2 Taiyoyuden JMK105BJ105MV-F 1 µF 402 1 x 0.5x 0.5 Charger CHRG_AUXPWR 3 KEMET C0402C105K9PAC7867 1 µF 402 1 x 0.5x 0.5 Charger LED 1 Osram LYL296 – Charger LED 2 Everlight 16S-216UTD/S559/TR8 2 mA 402 1 x 0.5x 0.35 Charger CHRG_BOOT 1 Murata GRM188R71H103KA01D 10 nF 603 1.6x 0.8x 0.8 Copyright© 2010–2011,Texas InstrumentsIncorporated 91

B 7,10 6,90 A7,10 6,90 6,00 TYP 0,40 0,40 T R P N M L K J H G E F D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bottom View Seating plane C0,31 0,21 0,15 0,05 C C M M A B 0,24 0,14 0,08 1,00 MAX SWCS045-002 TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com PACKAGE MATERIALS INFORMATION PACKAGE CHARACTERISTICS The package descriptionoftheTWL6030 PMU deviceispresentedas follows: PACKAGE (1) TWL6030 Type nFBGA Size(mm) 7 x 7 Substratelayers 2-layer Pitchballarray(mm) 0.4mm ViP (via-in-pad) No Arraygrid 16 x 16,depopulated Number ofballs 187 Thickness(mm; maximum height,includingballs) 1.0mm Maximum power dissipation(85°C ambienttemperature) 1.7W Others Green,ROHS compliant (1) MoistureSensitivityLevelTarget:JEDEC MSL3 @ 260°C The thermalresistancecharacteristicsforthe package used on the TWL6030 deviceisgiveninthe following table. PACKAGE POWER (W) R ΘJA (°C/W) R ΘJB (°C/W) R ΘJC (°C/W) BOARD TYPE nFBGA, 7mm x 7mm 1.7 31 19 12 1S2P

2.0±0.1 Do Ø1.55±0.05 4.0±0.1 P1 Ao F W Ø1.6±0.1 R 0.3 Typical Bo Ko BoCL Ko 0.30±0.05 SWCS045-031 TWL6030 www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 TAPE AND REEL INFORMATION Figure30. Tape and Reel Figure31. Tape Table19.Tape Dimensions A0 B0 K0 ±0.1 F P1 W ±0.3 Copyright© 2010–2011,Texas InstrumentsIncorporated 93

“C” (REF) ARBOR HOLE DETAIL “D” “B” C W2 (MEASURED AT HUB) N (HUB DIAMETER) A 1.8 W1 (MEASURED AT HUB) W3 (INCLUDES FLANGE DISTORTION AT OUTER EDGE) TWL6030 SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 www.ti.com Figure32. Reel Dimensions Table20.Reel Dimensions Material ESD Tape Material W1(+2.0/ W3(min/Hub size A(max) B(±0.5) C(±0.20) D(min) N W2(max)type type size color -0.0) max)

www.ti.com SWCS045C –SEPTEMBER 2010–REVISED JULY 2011 RevisionHistory The followingtablesummarizestheTWL6030 Data Sheetversions. Note:Numbering may varyfrompreviousverisons. Table21.RevisionHistory Version LiteratureNumber Date Notes * SWCS045 December 2009 See (1). A SWCS045A April2011 See (2). B SWCS045B June 2011 See (3). C SWCS045C July2011 See (4). (1) TWL6030 Data Sheet,(SWCS045) -initialrelease. (2) TWL6030 Data Sheet,(SWCS045A): (a) Added Figure1,TWL6030 BlockDiagram,Table2,BallDescription,FEATURES ,and APPLICATIONS . (b) Updated ELECTRICAL CHARACTERISTICS ,PACKAGE MATERIALS INFORMATION ,and Figure2,TWL6030 Package Top View BallMapping. (c)Updated RECOMMENDED EXTERNAL COMPONENTS . (d) Updated partnumbers,Table1,OrderingInformation. (e) Rewriteofallfunctionalblocks. (f)Updated figures. (3) TWL6030 Data Sheet,(SWCS045B): (a) Updated partnumbers,Table1,OrderingInformation. (b) Updated Figure1,TWL6030 BlockDiagram (c)Updated ballsN15, K13,B7 name fromSPARE toRESERVED. (d) Updated LDO REGULATORS description. (e) Updated Subsystem Hardware Commands description. (f)Updated Warmreset description. (g) Updated Table12,BOOT[3:0]. (h) Updated Figure11.Q1,Q2, and Q3 transistorsname added. (i)Updated listofGPADC internalmonitoredparametersinGENERAL-PURPOSE ADC . (j)Updated Interruptsfunctionalitydescription. (k)Updated Table18,Interruptmapping. (l)Updated ID Line,added Figure16 and Table17. (4) TWL6030 Data Sheet,(SWCS045C): (a) Remove Pulldown on NRESWARM inTable2 (b) Updated SMPS outputvoltageEquation1 (c)Added Defaultbootsequencessection (d) Remove prototypemark forTWL6030B1A4 inTable1 Copyright© 2010–2011,Texas InstrumentsIncorporated 95

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TWL6030B107CMR NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B107 TWL6030B107CMR.B NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B107 TWL6030B107CMRR NRND Production FCCSP (CMR) | 187 2500 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B107 TWL6030B107CMRR.B NRND Production FCCSP (CMR) | 187 2500 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B107 TWL6030B1A0CMR NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR - 6030B1A0 TWL6030B1A0CMR.B NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B1A0 TWL6030B1A0CMRR NRND Production FCCSP (CMR) | 187 2500 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR - 6030B1A0 TWL6030B1A0CMRR.B NRND Production FCCSP (CMR) | 187 2500 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B1A0 TWL6030B1A4CMR NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B1A4 TWL6030B1A4CMR.B NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B1A4 TWL6030B1A4CMRR NRND Production FCCSP (CMR) | 187 2500 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B1A4 TWL6030B1A4CMRR.B NRND Production FCCSP (CMR) | 187 2500 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 6030B1A4 TWL6030B1AACMR NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) - Call TI Level-3-260C-168 HR - 6030B1AA TWL6030B1AACMR.B NRND Production FCCSP (CMR) | 187 260 | JEDEC TRAY (5+1) - Call TI Level-3-260C-168 HR -40 to 85 6030B1AA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 23-May-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TWL6030B107CMRR FCCSP CMR 187 2500 336.6 336.6 31.8 TWL6030B1A0CMRR FCCSP CMR 187 2500 336.6 336.6 31.8 TWL6030B1A4CMRR FCCSP CMR 187 2500 336.6 336.6 31.8 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TWL6030B107CMR CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B107CMR.B CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B1A0CMR CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B1A0CMR.B CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B1A4CMR CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B1A4CMR.B CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B1AACMR CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 TWL6030B1AACMR.B CMR FCCSP 187 260 10 x 26 150 315 135.9 7620 11.8 10 10.35 Pack Materials-Page 3

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information