TWL1103T-Q1 TI | Alldatasheet
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Technical content
(TOP VIEW) PCMO PCMI DV SS DV DD SCL SDA NC NC PLLV DD EARV SS EAR1ON EARV DD EAR1OP EARV SS EAR2O AV DD 32 MBIAS MIC1P MIC1N MIC2P NC 1625 1234567 8 24 23 22 21 20 19 18 17 MIC2N REXT AVSS MCLK PLLVSS VSS RESET PWRUPSEL BUZZCON PCMSYN PCMCLK NC − No internal connection /C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Qualified for Automotive Applications /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C L = 200 pF, RL = 0) /C00682.7-V Operation /C0068Two Differential Microphone Inputs, One Differential Earphone Output, and One Single-Ended Earphone Output /C0068Programmable Gain Amplifiers for Transmit, Receive, Sidetone, and Volume Control /C0068Earphone Mute and Microphone Mute /C0068On-Chip I2C Bus, Which Provides a Simple, Standard, Two-Wire Serial Interface With Digital ICs /C0068Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-Law or A-Law) Data /C0068Available in a 32-Pin Thin Quad Flatpack (TQFP) Package /C0068Designed for Analog and Digital Wireless Handsets and Telecommunications
Applications
/C0068Dual-Tone Multifrequency (DTMF) and Single Tone Generator /C0068Pulse Density Modulated (PDM) Buzzer Output
description
The voice-band audio processor (VBAP) is designed to perform transmit encoding analog/ digital (A/D) conversion, receive decoding digital/analog (D/A) conversion, and transmit and receive filtering for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I 2C interface. The VBAP generates its own internal clocks from a 2.048-MHz master clock input. AVAILABLE OPTIONS /C0123 TA TQFP PBS PACKAGE /C0125 PART NO. TOP-SIDE MARKING −40°C to 105°C Tube Tape and Reel TWL1103TPBSQ1 TWL1103TPBSRQ1 TWL1103T TWL1103T † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Copyright 2008, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 VBAP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCMI (15) PCMSYN (18) PCMCLK (17) MIC1P (2) MIC1N (3) MIC2P (4) MIC2N (5) MIC Amplifier 1 g = 23.5 dB MIC Amplifier 2 g = 12 dB or 0 dB Analog Modulator TX Filter and PGA g = −10 dB to 0 dB PCM Interface Sidetone g = −24 dB to −12 dB RX Control g = −18 dB to 0 dB RX Filter and PGA g = −6 dB to +6 dB Digital Modulator and Filter Ear Amp1 Ear Amp2 DTMF Generator Control Bus I2C I/F REF PLL Buzzer Control Power SCL SDA MBIAS REXT MCLK RESET SSEARV DDEARV SSPLLV DDPLLV SSDV DDDV SSAV DDAV SSV PWRUPSEL (20) PCMO (16) EAR1OP (29) EAR1ON (27) EAR2O (31) BUZZCON (19) Volume and RESET (23) (32) (8) (13) (14) (25) (24) (28) (30, 26) (21) (22) (6) (1) (11) (12)
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description power on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low RESET terminal to guarantee reset upon power on. After the initial power-on sequence the TWL1103 can be functionally powered up and down by writing to the power control register through the I 2C interface. There is a hardwired selectable power-up terminal in default mode option. The PWRUPSEL function allows the VBAP to power up in the default mode and allows use without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. control interface The I 2C interface is a two-wire bidirectional serial interface that controls the VBAP by writing data to the six control registers: /C0068Power control /C0068Mode control /C0068Transmit PGA and sidetone control /C0068Receive PGA gain and volume control /C0068DTMF high tone /C0068DTMF low tone There are two power-up modes which may be selected at the PWRUPSEL terminal: /C0068The PWRUPSEL state (VDD at terminal 20) causes the device to power up in the default mode when power is applied. In the default mode, the I2C interface is not required, and the device may be used without an I2C interface. The programmable functions are fixed in the default modes. /C0068The PWRUPSEL state (ground at terminal 20) causes the device to go to a power-down state when power is applied. In this mode an I 2C interface is required to power up the device. phase-locked loop The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the 2.048-MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low- noise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of 0 dB or 12 dB.
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description (continued) analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either the 15-bit linear or 8-bit companded µ-law or A-law mode that is selectable through the I2C interface. The transmit PGA defaults to 0 dB. sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to −12 dB. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of −18 dB to 0 dB in 2 dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates in either the 15-bit linear or 8-bit µ-law or A-law companded mode, which is selectable through the I2C interface. The gain defaults to −1 dB representing a 3-dBm0 level for a 32-Ω load impedance and the corresponding digital full scale PCMI code. The gain may be set to −2 dB for the respective 3-dBm0 level for a 16-Ω load impedance. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones and single tone frequencies which are output to the following devices: 1) The buzzer driver, as a pulse density modulation (PDM) signal 2) The receive path digital/analog converter (DAC) for outputting through the earphone. There are 255 possible single tones. The tone integer value is determined by the following formula: Round (Tone Freq (Hz)/7.8135 Hz) The value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05). The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the high DTMF tone must be applied to the high-tone register and the low frequency tone to the low-tone register.
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION NAME µBGA PBS I/O DESCRIPTION AV DD A1 32 I Analog positive power supply AV SS J1 8 I Analog negative power supply BUZZCON F9 19 O Buzzer output, a pulse-density modulated signal to apply to external buzzer driver DV DD J6 13 I Digital positive power supply DV SS J7 14 I Digital negative power supply EAR1ON A6 27 O Earphone 1 amplifier output (−) EAR1OP A4 29 O Earphone 1 amplifier output (+) EAR2O A2 31 O Earphone 2 amplifier output EARV DD A5 28 I Analog positive power supply for the earphone amplifiers EARV SS A3, A7 30, 26 I Analog negative power supply for the earphone amplifiers MBIAS B1 1 O Microphone bias supply output, no decoupling capacitors MCLK C9 22 I Master system clock input (2.048 MHz) (digital) MIC1P C1 2 I MIC1 input (+) MIC1N D1 3 I MIC1 input (−) MIC2P E1 4 I MIC2 input (+) MIC2N F1 5 I MIC2 input (−) PCMI J8 15 I Receive PCM input PCMO J9 16 O Transmit PCM output PCMSYN G9 18 I PCM frame synchronization PCMCLK H9 17 I PCM data clock PLLV SS A9 24 I PLL negative power supply PLLV DD A8 25 I PLL digital power supply PWRUPSEL E9 20 I Selects the power-up default mode REXT G1 6 I/O Internal reference current setting terminal—use precision 100-kΩ resistor and no filtering capacitors RESET D9 21 I Active low reset SCL J5 12 I I2C-bus serial clock—this input is used to synchronize the data transfer from and to the VBAP SDA J4 11 I/O I2C-bus serial address/data input/output—this is a bidirectional terminal used to transfer register control addresses and data into and out of the CODEC. It is an open-drain terminal and therefore requires a pullup resistor to VDD (typical 10 kΩ for 100 kHz) VSS B9 23 I Ground return for bandgap internal reference
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 85°C POWER RATING TA = 105°C POWER RATING PBS 680 mW 6.8 mW/°C 270 mW 134 mW recommended operating conditions (see Notes 1 and 2) MIN NOM MAX UNIT Supply voltage, AVDD , DVDD , PLLVDD , EARVDD 2.7 3.3 V High-level input voltage (VIH) 0.7 x VDD V Low-level input voltage (VIL) 0.3 x VDD V Load impedance between EAR1OP and EAR1ON-RL 16 32 Ω Load impedance for EAR2OP-RL 32 Ω Operating free-air temperature, TA −40 105 /C0095C NOTES: 1. To avo id possible damage and resulting reliability problems to these CMOS devices, the power-on initialization paragraph must be followed, described in the Principles of Operations. 2. Voltages are with respect to AVSS , DVSS, PLLVSS , and EARV SS.
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VDD = 2.7 V, TA = −40°C to 105°C (unless otherwise noted) supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Operating, EAR1 selected, MicBias disabled 6 7 mA Operating, EAR2 selected, MicBias disabled 5.4 6 mA IDD Supply current from VDD Power down, Reg 2 bit 7 = 1, MClk not present (see Note 3) 0.5 18 µA Power down, Reg 2 bit 7 = 0, MClk not present (see Note 3) 25 40 µA ton(i) Power-up time from power down 5 10 ms NOTE 3: V IH = VDD , VIL = VSS digital interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage, PCMO and BuzzCon IOH = −3.2 mA, VDD = 3 V 2 V VOL Low-level output voltage, PCMO and BuzzCon IOL = 3.2 mA, VDD = 3 V 0.8 V IIH High-level input current, any digital input VI = VDD 10 µA IIL Low-level input current, any digital input VI = VSS 10 µA C I Input capacitance 10 pF C o Output capacitance 20 pF R L Load impedance (BuzzCon) 5 kΩ microphone interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage at MIC1N, MIC2N See Note 4 −5 5 mV IIB Input bias current at MIC1N, MIC2N −600 600 nA C i Input capacitance at MIC1N, MIC2N 5 pF Vn Microphone input referred noise, psophometric weighted (C-message weighted is similar) Micamp 1 gain = 23.5 dB Micamp 2 gain = 0 dB 3.0 7.7 µVrms IO max Output source current MBIAS 1 1.2 mA V(mbias) Microphone bias supply voltage (see Note 5) 2.35 2.5 2.6 V MICMUTE −80 dB Input impedance Fully differential 35 60 100 kΩ NOTES: 4. Measured while MIC1P and MIC1N are connected together. Less than 5 mV offset results in 0 value code on PCMOUT. 5. Not a JEDEC symbol. speaker interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Earphone AMP1 output power (See Note 6) VDD = 2.7 V, fully differential, 16-Ω load, 3-dBm0 output, RGXPA = −2 dB 120.9 151.1 mW Earphone AMP1 output power (See Note 6) VDD = 2.7 V, fully differential, 32-Ω load, 3-dBm0 output, RGXPA = −1 dB 76.1 95.1 mW Earphone AMP2 output power (See Note 6) VDD = 2.7 V, single ended, 32-Ω load, 3-dBm0 output 10 12.5 mW VOO Output offset voltage at EAR1 Fully differential ±5 ±30 mV Maximum output current for EAR1(rms) 3-dBm0 input, 16-Ω load 86.9 108.6 IO max Maximum output current for EAR1(rms) 3-dBm0 input, 32-Ω load 48.7 60.8 mAIO max Maximum output current for EAR2 (rms) 3-dBm0 input 17.7 22.1 mA EARMUTE −80 dB NOTE 6: Maximum power is with a load impedance of approximately 12 Ω.
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VDD = 2.7 V, TA = −40°C to 105°C (unless otherwise noted) (continued) transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (see Notes 7 and 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmit reference-signal level (0 dB)Differential 175 mV pp Overload-signal level (3 dBm0) Differential, normal mode 248 mV ppOverload-signal level (3 dBm0) Differential, extended mode 63 mV pp Absolute gain error 0 dBm0 input signal, VDD = 2.7 V (minimum) −1 1 dB Linear mode gain error with input level MIC1N, MIC1P to PCMO at 3 dBm0 to −30 dBm0 −0.5 0.5Linear mode gain error with input level relative to gain at −10 dBm0 MIC1N, MIC1P to PCMO MIC1N, MIC1P to PCMO at −31 dBm0 to −45 dBm0 −1 1 dBrelative to gain at −10 dBm0 MIC1N, MIC1P to PCMO MIC1N, MIC1P to PCMO at −46 dBm0 to −55 dBm0 −1.2 1.2 dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter enabled (see Notes 7 and 8) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmit reference-signal level (0dB) Differential 175 mV pp Overload-signal level (3 dBm0) Differential, normal mode 248 mV ppOverload-signal level (3 dBm0) Differential, extended mode 63 mV pp Absolute gain error 0-dBm0 input signal, VDD = 2.7 V (minimum) −1 1 dB Linear mode gain error with input level MIC1N, MIC1P to PCMO at 3 dBm0 to −30 dBm0 −0.5 0.5Linear mode gain error with input level relative to gain at −10-dBm0 MIC1N, MIC1P to PCMO MIC1N, MIC1P to PCMO at −31 dBm0 to −45 dBm0 −1 1 dBrelative to gain at −10-dBm0 MIC1N, MIC1P to PCMO MIC1N, MIC1P to PCMO at −46 dBm0 to −55 dBm0 −1.2 1.2 dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit filter transfer, linear mode selected, transmit slope filter bypassed, external high pass filter bypassed (MCLK = 2.048 MHz) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMIC1 or fMIC2 <100 Hz −8.5 −6 fMIC1 or fMIC2 = 200 Hz −4.5 −3 Gain relative to input signal gain at 1020 Hz, internal high-pass fMIC1 or fMIC2 > 700 Hz to 3 kHz −0.5 0.5 Gain relative to input signal gain at 1020 Hz, internal high-pass filter disabled fMIC1 or fMIC2 = 3.4 kHz −1.5 0 dBfilter disabled fMIC1 or fMIC2 = 4 kHz −14 dB fMIC1 or fMIC2 = 4.6 kHz −35 fMIC1 or fMIC2 = 8 k Hz −47 Gain relative to input signal gain at 1020 Hz, internal high-passfMIC1 or fMIC2 <100 Hz −15 dBGain relative to input signal gain at 1020 Hz, internal high-pass filter enabled fMIC1 or fMIC2 = 200 Hz −5 dB
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VDD = 2.7 V, TA = −40°C to 105°C (unless otherwise noted) (continued) transmit filter transfer, linear mode selected, transmit slope filter selected (MCLK = 2.048 MHz) (see Note 9) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMIC1 or f MIC2 =100 Hz −27 dB fMIC1 or fMIC2 = 200 Hz −8 dB fMIC1 or fMIC2 = 250 Hz −4 dB fMIC1 or fMIC2 = 300 Hz −1.80 dB fMIC1 or fMIC2 = 400 Hz −1.50 dB fMIC1 or fMIC2 = 500 Hz −1.30 dB fMIC1 or fMIC2 = 600 Hz −1.1 dB fMIC1 or fMIC2 = 700 Hz −0.8 dB fMIC1 or fMIC2 = 800 Hz −0.57 dB fMIC1 or fMIC2 = 900 Hz −0.25 dB Gain relative to input signal gain at 1000 Hz, with slope filter selected fMIC1 or fMIC2 = 1000 Hz 0 dB Gain relative to input signal gain at 1000 Hz, with slope filter selected fMIC1 or fMIC2 = 1500 Hz 1.8 dB fMIC1 or fMIC2 = 2000 Hz 4.0 dB fMIC1 or fMIC2 = 2500 Hz 6.5 dB fMIC1 or fMIC2 = 3000 Hz 7.6 dB fMIC1 or fMIC2 = 3100 Hz 7.7 dB fMIC1 or fMIC2 = 3300 Hz 8.0 dB fMIC1 or fMIC2 = 3500 Hz 6.48 dB fMIC1 or fMIC2 = 4000 Hz −13 dB fMIC1 or fMIC2 = 4500 Hz −35 dB fMIC1 or fMIC2 = 5000 Hz −45 dB fMIC1 or fMIC2 = 8000 Hz −50 dB NOTE 9: The pass-band tolerance is ± 0.25 dB from 300 Hz to 3500 Hz. transmit idle channel noise and distortion, linear mode selected, slope filter bypassed PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmit idle channel noise TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0.0 dB −86.6 −78 dBm0 p MIC1N, MIC1P to PCMO at 3 dBm0 40 50 MIC1N, MIC1P to PCMO at 0 dBm0 50 65 MIC1N, MIC1P to PCMO at −5 dBm0 60 68 Transmit signal-to-total distortion ratio with 1020-Hz MIC1N, MIC1P to PCMO at −10 dBm0 55 70 dBTransmit signal-to-total distortion ratio with 1020-Hz sine-wave input MIC1N, MIC1P to PCMO at −20 dBm0 58 65 dBsine-wave input MIC1N, MIC1P to PCMO at −30 dBm0 50 60 MIC1N, MIC1P to PCMO at −40 dBm0 38 50 MIC1N, MIC1P to PCMO at −45 dBm0 30 45
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VDD = 2.7 V, TA = −40°C to 105°C (unless otherwise noted) (continued) transmit idle channel noise and distortion, linear mode selected, slope filter enabled PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmit idle channel noise TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0.0 dB −86.6 −78 dBm0 p MIC1N, MIC1P to PCMO at 3 dBm0 40 50 MIC1N, MIC1P to PCMO at 0 dBm0 50 65 MIC1N, MIC1P to PCMO at −5 dBm0 55 68 Transmit signal-to-total distortion ratio with 1020-HzMIC1N, MIC1P to PCMO at −10 dBm0 55 70 dBTransmit signal-to-total distortion ratio with 1020-Hz sine-wave input MIC1N, MIC1P to PCMO at −20 dBm0 58 65 dBsine-wave input MIC1N, MIC1P to PCMO at −30 dBm0 48 60 MIC1N, MIC1P to PCMO at −40 dBm0 38 50 MIC1N, MIC1P to PCMO at −45 dBm0 30 45 receive gain and dynamic range, EAR1 selected, linear or companded (µ-law or A-law) mode selected (see Note 10) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overload-signal level (3.0 dB) 16-Ω load RXPGA = −2.0 dB 3.93 VppOverload-signal level (3.0 dB) 32-Ω load RXPGA = −1.0 dB (default gain) 4.41 Vpp Absolute gain error 0-dBm0 input signal, VDD = 2.7 V (minimum) −1 1 dB Linear mode gain error with output level PCMIN to EAR1ON, EAR1OP at 3 dBm0 to −40 dBm0 −0.5 0.5 Linear mode gain error with output level relative to gain at −10 dBm0 PCMIN to EAR1ON, EAR1OP at −41 dBm0 to −50 dBm0 −1 1 dBrelative to gain at −10 dBm0 PCMIN to EAR1ON, EAR1OP at −51 dBm0 to −55 dBm0 −1.2 1.2 dB NOTE 10: RXPGA = -1 dB for 32 Ω default mode or RXPGA = -2 dB for 16 Ω, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP receive gain and dynamic range, EAR2 selected, linear or companded (µ-law or A-law) mode selected (see Note 11) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receive reference-signal level (0 dB) 0-dBm0 PCM input signal 1.1 Vpp Overload-signal level (3 dB) 1.6 Vpp Absolute gain error 0-dBm0 input signal, VDD = 2.7 V (minimum) −1 1 dB Linear mode gain error with output level relative to PCMIN to EAR2O at 3 dBm0 to −40 dBm0 −0.5 0.5 Linear mode gain error with output level relative to gain at −10 dBm0 PCMIN to EAR2O at −41 dBm0 to −50 dBm0 −1 1 dBgain at −10 dBm0 PCMIN to EAR2O at −51 dBm0 to −55 dBm0 −1.2 1.2 dB NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VDD = 2.7 V, TA = −40°C to 105°C (unless otherwise noted) (continued) receive filter transfer, linear mode selected (MCLK = 2.048 MHz) (see Note 11) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fEAR1 or fEAR2 <100 Hz −0.5 0.5 fEAR1 or fEAR2 = 200 Hz −0.5 0.5 Gain relative to input signal gain at 1020 Hz, internal fEAR1 or fEAR2 = 300 Hz to 3 kHz −0.5 0.5 Gain relative to input signal gain at 1020 Hz, internal high-pass filter disabled fEAR1 or fEAR2 = 3.4 kHz −1.5 0 dBhigh-pass filter disabled fEAR1 or fEAR2 = 4 kHz −14 dB fEAR1 or fEAR2 = 4.6 kHz −35 fEAR1 or fEAR2 = 8 kHz −47 Gain relative to input signal gain at 1020 Hz, internalfEAR1 or fEAR2 <100 Hz −15 dBGain relative to input signal gain at 1020 Hz, internal high-pass filter enabled fEAR1 or fEAR2 = 200 Hz −5 dB NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 12) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receive noise, (20 Hz to 20 kHz brickwall window)PCMIN = 0000000000000 −86 −83 dBm0 PCMIN to EAR1ON, EAR1OP at 3 dBm0 65 78 PCMIN to EAR1ON, EAR1OP at 0 dBm0 73 80 PCMIN to EAR1ON, EAR1OP at −5 dBm0 72 78 Receive signal-to-distortion ratio with 1020 Hz PCMIN to EAR1ON, EAR1OP at −10 dBm0 70 78 dBReceive signal-to-distortion ratio with 1020 Hz sine-wave input PCMIN to EAR1ON, EAR1OP at −20 dBm0 60 76 dBsine-wave input PCMIN to EAR1ON, EAR1OP at −30 dBm0 50 67 PCMIN to EAR1ON, EAR1OP at −40 dBm0 40 60 PCMIN to EAR1ON, EAR1OP at −45 dBm0 33 55 Intermodulation distortion, 2-tone CCITT method, CCITT G.712 (7.1), R2 50 dBIntermodulation distortion, 2-tone CCITT method, composite power level, −13 dBm0 CCITT G.712 (7.2), R2 54 dB NOTE 12: RXPGA = -1 dB for 32 Ω default mode or RXPGA = -2 dB for 16 Ω, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP. receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 11) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receive noise, (20 Hz to 20 kHz brickwall window) PCMIN = 0000000000000 −86 −82 dBm0 PCMIN to EAR2O at 3 dBm0 45 60 PCMIN to EAR2O at 0 dBm0 60 65 PCMIN to EAR2O at −5 dBm0 58 62 Receive signal-to-distortion ratio with 1020-Hz sine-wave inputPCMIN to EAR2O at −10 dBm0 55 60 dBReceive signal-to-distortion ratio with 1020-Hz sine-wave input PCMIN to EAR2O at −20 dBm0 53 60 dB PCMIN to EAR2O at −30 dBm0 52 58 PCMIN to EAR2O at −40 dBm0 44 57 PCMIN to EAR2O at −45 dBm0 33 52 Intermodulation distortion, 2-tone CCITT method, compositeCCITT G.712 (7.1), R2 50 dBIntermodulation distortion, 2-tone CCITT method, composite power level, −13 dBm0 CCITT G.712 (7.2), R2 54 dB NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VDD = 2.7 V, TA = −40°C to 105°C (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply voltage rejection, transmit channelMIC1N, MIC1P =0 V, VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz −80 −45 dB Supply voltage rejection, receive channel, EAR1 selected (differential) PCM code = positive zero, VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz −90 −45 dB Crosstalk attenuation, transmit-to-receive (differential) MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured differentially between EAR1ON and EAR1OP 70 dB Crosstalk attenuation, receive-to-transmitPCMIN = 0 dBm0, f = 300 to 3400 Hz measured at PCMO, EAR1 amplifier 70 dB DTMF generator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DTMF high to low tone relative amplitude (preemphasis) 1.5 2 2.5 dB MICBIAS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Load impedance 2.0 2.5 kΩ timing requirements clock MIN NOM MAX UNIT tt Transition time, MCLK 10 ns MCLK frequency 2.048 2.048 MHz MCLK jitter 37% Number of PCMCLK clock cycles per PCMSYN frame 256 256 tc(PCMCLK) PCMCLK clock period 156 488 512 ns Duty cycle, PCMCLK 45% 50% 68% transmit (see Figure 6) MIN MAX UNIT tsu(PCMSYN) Setup time, PCMSYN high before PCMCLK↓ 20 tc(PCMCLK) −20 ns th(PCMSYN) Hold time, PCMSYN high after PCMCLK↓ 20 tc(PCMCLK) −20 ns receive (see Figure 5) MIN MAX UNIT tsu(PCSYN) Setup time, PCMSYN high before PCMCLK↓ 20 tc(PCMCLK) −20 ns th(PCSYN) Hold time, PCMSYN high after PCMCLK↓ 20 tc(PCMCLK) −20 ns tsu(PCMI) Setup time, PCMI high or low before PCMCLK↓ 20 ns th(PCMI) Hold time, PCMI high or low after PCMCLK↓ 20 ns
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements (continued) I2C bus (see Figure 6) MIN MAX UNIT SCL Clock frequency 400 kHz tHIGH Clock high time 600 ns tLOW Clock low time 1300 ns tR SDA and SCL rise time 300 ns tF SDA and SCL fall time 300 ns thD:STA Hold time (repeated) START condition. After this period the first clock pulse is generated.600 ns tsu:STA Setup time for repeated START condition 600 ns thD:DAT Data input hold time 0 ns tsu:DAT Data input setup time 100 ns tsu:STO STOP condition setup time 600 ns tBUF Bus free time 1300 ns switching characteristics propagation delay times, CLmax = 10 pF (see Figure 5) MIN MAX UNIT tpd1 From PCMCLK bit 1 high to PCMO bit 1 valid 35 ns tpd2 From PCMCLK high to PCMO valid, bits 2 to n 35 ns tpd3 From PCMCLK bit n low to PCMO bit n Hi-Z 30 ns
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 1. I2C Bus Write to VBAP Figure 2. I2C Read From VBAP: Protocol A Figure 3. I2C Read From VBAP: Protocol B
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION register map addressing REG 07 06 05 04 03 02 01 00 Power control 00 Sidetone En TXEn RXEn MICSEL BIASEn RXEn EAROUT Sel PWRUP Mode control 01 Comp Sel TMEn PCMLB Comp En BUZZEn RXFLTR En TXFLTR En TXSLOPE En TXPGA 02 PD0 TP3 TP2 TP1 TP0 ST2 ST1 ST0 RXPGA 03 RP3 RP2 RP1 RP0 RV3 RV2 RV1 RV0 High DTMF 04 HIFREQ Sel7 HIFREQ Sel6 HIFREQ Sel5 HIFREQ Sel4 HIFREQ Sel3 HIFREQ Sel2 HIFREQ Sel1 HIFREQ Sel0 Low DTMF 05 LOFREQ Sel7 LOFREQ Sel6 LOFREQ Sel5 LOFREQ Sel4 LOFREQ Sel3 LOFREQ Sel2 LOFREQ Sel1 LOFREQ Sel0 register power-up defaults REG 07 06 05 04 03 02 01 00 Power control† 00 1 1 1 1 0 1 1 0 Power control‡ 00 1 0 0 1 1 0 1 1 Mode control 01 0 0 0 0 0 0 1 0 TXPGA 02 0 1 0 0 0 0 0 0 RXPGA 03 0 1 1 1 0 0 0 0 High DTMF 04 0 0 0 0 0 0 0 0 Low DTMF 05 0 0 0 0 0 0 0 0 † Value when PWRUPSEL = 0 ‡ Value when PWRUPSEL = 1
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 1. Power Control Register: Address {00} HEX
0 X X XXXXX Sidetone enabled
1 X X X X X X X Sidetone muted
Table 2. Mode Control Register: Address {01} HEX
1 X X 1 X X X X A-law companding mode selected
0 XX1X X XX µ-law companding mode selected
NOTES: A. This window is allowed for PCMSYN high. B. This window is allowed for PCMSYN low (th(PCMSYN) max determined by data collision considerations). C. Transitions are measured at 50%. Figure 4. Transmit Timing Diagram
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A. This window is allowed for PCMSYN high. B. This window is allowed for PCMSYN low. C. Transitions are measured at 50%. Figure 5. Receive Timing Diagram Figure 6. I2C Bus Timing Diagram
guarantee reset upon power on. All registers are set with default values upon external reset initialization. Table 3. Power-Up and Power-Down Procedures (VDD = 2.7 V, Earphone amplifier unloaded) remains powered up until the PCM data is completely transferred. 15-bit twos-complement format. can be used to capacitively connect a second microphone or an auxiliary audio circuit.
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 7. Typical Microphone Interface be selected by setting bit 6 of the power control register through the I2C interface. Table 4. Transmit Gain Control
to 6 dB in 1-dB steps through the I2C interface. The default receive channel gain is −1 dB. Table 5. Receive PGA Gain Control register. The default sidetone gain is −12 dB. Table 6. Sidetone Gain Control
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 7. rx Volume Control Muting can be selected by setting bit 3 of the power control register through the I2C interface. /C0068Companded mode: eight bits are received, the most significant (MSB) first. /C0068Linear mode: 15 bits are received, MSB first.
Table 8. Receive-Data Bit Definitions
1 CD7 LD14
2 CD6 LD13
3 CD5 LD12
4 CD4 LD11
5 CD3 LD10
6 CD2 LD9
7 CD1 LD8
8 CD0 LD7
dialing and provides the PDM output for the BUZZCON user-alert tone. There are 255 possible single tones. The integer value is loaded into either one of two 8-bit registers, high-tone register (04), or low-tone register (05).
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 9. Typical DTMF and Single Tone Control
/C0084/C0087/C0076/C0049/C0049/C0048/C0051/C0084/C0262/C0081/C0049 /C0086/C0079/C0073/C0067/C0069/C0262/C0066/C0065/C0078/C0068 /C0065/C0085/C0068/C0073/C0079 /C0080/C0082/C0079/C0067/C0069/C0083/C0083/C0079/C0082 /C0040/C0086/C0066/C0065/C0080/C0041 SGLS120B − APRIL 2002 − REVISED APRIL 2008 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION DTMF generator operation and interface (continued) Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the individual output ports. The values that determine the tone frequency are loaded into the tone registers (high and lo) as two separate values. The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in twos complement value into the the tone registers. There is a 2 dB difference in the resulting output of the two registers, the high-tone register having the greater result. The resulting range of a tone set into the low register value is +31 {1F}HEX to −32 {20}HEX for a range of six bits and is in twos complement format. The resulting range of a tone set into the high register value is +39 {27}HEX to −40 {D8}HEX in twos-complement format, as well. The maximum range is six bits having a maximum value of {31}HEX. The value {31} is represented as 011111. Two zeros are added to the leading side of the value and then the value is padded with seven LSB zeros to create a value of 000 1111 1000 0000. Because the maximum full scale value is 000 1111 1000 0000, the resulting output magnitude is 20 log (input value/maximum value) or 20 log (3968/16783) or −12.31 dB below full scale. This is the result when all gains are set at default. buzzer logic section The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver transistor. The PDM begins as a selected tone, is generated and passed through the receive D/A channel, and is fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the BUZZCON output. support section The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive internal counters, filters, and converters. Register control data is written into and read back from the VBAP registers via the control interface. I 2C-bus protocols The VBAP serial interface is designed to be I2C bus-compatible and operates in the slave mode. This interface consists of the following terminals: SCL: I2C bus serial clock— This input synchronizes the control data transfer from and to the CODEC. SDA: I2C bus serial address/data input/output— This is a bidirectional terminal that transfers register control addresses and data into and out of the codec. It is an open drain terminal and therefore requires a pullup resistor to V CC (typical 10 kΩ for 100 kHz). TWL1103 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode. For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are reserved for indicating the start and stop conditions. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted as a start or stop condition.
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 10. I2C Bus Conditions A Bus not busy Both data and clock lines remain at high. B Start data transferA high to low transition of the SDA line while the clock (SCL) is high determines a start condition. All commands must proceed from a start condition. C Stop data transfer A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition. All operations must end with a stop condition. for the duration of the high period of the clock signal. Each data transfer is initiated with a start condition and terminated with a stop condition. (microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit. the data line high to enable the master to generate the stop condition. A fixed PCMSYN rate of 8 kHz determines the sampling rate.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TWL1103TPBSQ1 Active Production TQFP (PBS) | 32 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 TWL1103T TWL1103TPBSQ1.B Active Production TQFP (PBS) | 32 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 105 TWL1103T TWL1103TPBSRQ1 Active Production TQFP (PBS) | 32 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 105 TWL1103T TWL1103TPBSRQ1.B Active Production TQFP (PBS) | 32 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 105 TWL1103T (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TWL1103TPBSQ1 PBS TQFP 32 250 10 X 25 150 315 135.9 7620 12.2 11.1 11.25 Pack Materials-Page 1
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