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Document overview
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Technical content
Features
- Software selectable analog input control allows for combinations of single ended CVBS, and differential CVBS
- Built-in analog antialias filter
- Two 10-bit ADCs and analog clamping circuit
- Fully programmable static gain or automatic gain control for the Y channel
- Programmable white peak control for the Y channel
- 4-H adaptive comb filter Y/C separation
- PAL delay line for color phase error correction
- Digital subcarrier PLL for accurate color decoding
- Digital horizontal PLL for sy nchronization processing and pixel sampling
- Advanced synchronization processing and sync detection for handling nonstandard and weak signal
- Automatic color cont rol and color killer
- Chroma IF compensation
- VBI slicer supporting industrial standard data services
- VBI data passthrough, raw ADC data output
- P r o g r a m m a b l e o u t p u t c r o p p i n g Video Processing
- Automatic Contrast Adjustment (ACA)
- RGB565
- Programmable hue, brightness, saturation, contrast and sharpness.
- Image enhancement with peaking and CTI MIPI Output
- MIPI 1.1 compliant unidirectional output format
- YUV 422 or RGB565 output format Digital Output
- Output voltage 1.8V to 3.3V with 3.3V tolerance Miscellaneous
- Low power consumption: 100mW typical
- Power save and Power-down mode
- Short-to-battery detection test
- S h o r t - t o - g r o u n d d e t e c t i o n t e s t
- Two-wire MPU serial bus interface
- Supports real time control interface
- Single 27MHz crystal for all operations
- Supports 24.54MHz and 29.5MHz crystal for high resolution square pixel format decoding
- 3 . 3 V t o l e r a n t I / O
- 1.8V/3.3V power supply
- 32 Ld QFN (WQFN with wettable flanks) MUX YIN0/ YIN1/YIN0- YIN2 / YIN2+ / DIAG0 YIN4 / YIN3 / YIN2- YIN5 / YIN4- YIN6 / YIN7 / YIN6- DIAG1 DIAG2 RSTB PDN SCLK SDAT STB/STG DETECTION I2C DETECTION OSC REGISTER FILES PLL ANTI-ALIASING FILTER AGC 10-bit ADC 4H COMB FILTER DECODER AUTOMATIC CONTRAST ADJUSTMENT FORMAT CONVERTER MIPI PROTOCOL CONTROLLER MIPI SEREALIZER MIPI D-PHY GP0 GP1 GP2 INTREQ MIPID- MIPID+ MIPICLK- MIPICLK+
FIGURE 1. TW9992 FUNCTIONAL BLOCK DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
2 FN8722.0 March 23, 2015 Intersil products are manufactured, assembled and tested utilizing ISO9001 or TS16949 quality systems as applicable noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html Submit Document Feedback