Logic IC

TW2984

Renesas Technology Corp

4-CH WD1 (960H)/D1 Compatible Video Decoders and Audio Codecs September 24, 2013

Manufacturer: Renesas Technology Corp

Document: 123 Pages / 3Mb

Request Quote Download Datasheet Read online HTML view

More from Renesas Technology Corp Browse T parts

Online Datasheet

Read TW2984 online.

TW2984 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 123

Technical content

Features

 WD1 (960H) and D1 compatible video decoding operation and it is programmable each channel  NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60) support with automatic format detection  Built-in analog anti-alias filter  Four 10-bit ADCs and analog clamping circuit for CVBS input  Fully programmable static gain or automatic gain control for the Y channel  Programmable white peak control for CVBS channel  4-H adaptive comb filter Y/C separation  PAL delay line for color phase error correction  Image enhancement with peaking and CTI  Digital sub-carrier PLL for accurate color decoding  Digital Horizontal PLL for synchronization processing and pixel sampling  Advanced synchronization processing and sync detection for handling non-standard and weak signal  Programmable hue, brightness, saturation, contrast, sharpness  Automatic color control and color killer  ITU-R 656 like YCbCr (4:2:2) output or time multiplexed output with 36/72/144MHz for WD1 or 27/54/108MHz for D1 format Audio Codec  Integrated five audio ADCs processing and one audio DAC  Provides multi-channel audio mixed analog output  Support I2S/DSP Master/Slave interface for record output and playback input  PCM 8/16-bit and u-Law/A-Law 8-bit for audio word length  Programmable audio sample rate that covers popular frequencies of 8/16/32/44.1/48kHz Miscellaneous  Two-wire MPU serial bus interface  Integrated clock PLL for 144/108MHz clock output  Power save and Power down mode  Low power consumption  Single 27MHz crystal for all standards and both WD1 and D1 format  3.3V tolerant I/O  1.0V/3.3V power supply  8mm x 8mm 68-pin QFN package

FIGURE 1. TW2984 BLOCK DIAGRAM

FN8583 Rev.0.00 Page 3 of 123 September 24, 2013

Ordering Information

(NOTE 1) PART MARKING PACKAGE (Pb-free) PKG. DWG. # TW2984-NA2-CR TW2984 NA2-CR 68 Lead QFN (8mm x 8mm) Q68.8x8B NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8583 Rev.0.00 Page 4 of 123 September 24, 2013 Table of Contents Two Channel ITU-R BT.656 Time-multiplexed Format with Four Channel 960H Time-division-multiplexed Format with 0x00(CH1)/0x10(CH2)/0x20(CH3)/0x30(CH4) – Video 0x01(CH1)/0x11(CH2)/0x21(CH3)/0x31(CH4) – 0x02(CH1)/0x12(CH2)/0x22(CH3)/0x32(CH4) – 0x03(CH1)/0x13(CH2)/0x23(CH3)/0x33(CH4) – 0x04(CH1)/0x14(CH2)/0x24(CH3)/0x34(CH4) – Chroma 0x05(CH1)/0x15(CH2)/0x25(CH3)/0x35(CH4) – Chroma 0x06(CH1)/0x16(CH2)/0x26(CH3)/0x36(Ch4) – Hue 0x07(CH1)/0x17(CH2)/0x27(CH3)/0x37(CH4) – Cropping 0x08(CH1)/0x18(CH2)/0x28(CH3)/0x38(CH4) – Vertical 0x09(CH1)/0x19(CH2)/0x29(CH3)/0x39(CH4) – Vertical 0x0A(CH1)/0x1A(CH2)/0x2A(CH3)/0x3A(CH4) – 0x0B(CH1)/0x1B(CH2)/0x2B(CH3)/0x3B(CH4) – 0x0C(CH1)/0x1C(CH2)/0x2C(CH3)/0x3C(CH4) – 0x0D(CH1)/0x1D(CH2)/0x2D(CH3)/0x3D(CH4) – Chip 0x0E(CH1)/0x1E(CH2)/0x2E(CH3)/0x3E(CH4) – Standard 0x0F(CH1)/0x1F(CH2)/0x2F(CH3)/0x3F(CH4) – Standard 0x57(CH1)/0X58(CH2)/0X59(CH3)/0X5A(CH4) – HBLEN60 0x69(CH1)/0X6A(CH2)/0X6B(CH3)/0X6C(CH4) – 0xA0(CH1)/0xA1(CH2)/0xA2(CH3)/0xA3(CH4) – NT50 .. 61 0xA4(CH1)/0xA5(CH2)/0xA6(CH3)/0xA7(CH4) – ID 0xAB(CH1)/0xAC)CH2)/0XAD(CH3)/0XAE(CH4) – Video 0xC4(CH1)/0xC5(CH2)/0xC6(CH3)/0xC7(CH4) – H

FN8583 Rev.0.00 Page 5 of 123 September 24, 2013 0xBD – Adjusted Analog Audio ADC Digital Input Value101 0xBE – Adjusted Analog Audio ADC Digital Input Value 101 0xBF – Adjusted Analog Audio ADC Digital Input Value 102 0xC0 – Adjusted Analog Audio ADC Digital Input Value 102 0xC1 – Adjusted Analog Audio ADC Digital Input Value 102 0x79 – Adjusted Analog Audio ADC Digital Input Value 102 0x7A – Adjusted Analog Audio ADC Digital Input Value 102 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA – 0xE1 – Audio Detection Period and Audio Detection 0xFA – Output Enable Control and Clock Output Control117

FN8583 Rev.0.00 Page 6 of 123 September 24, 2013 Pin Diagrams VDDV VDDAPLL2 VSS TEST5 SADD[1] VDDI8 SCLK SDAT11 ALINKI VDDO14 VSS VD[7] VSSA VSS IRQ VDDI VDDO ALINKO ADATP ASYNP ACLKP VSS ADATR ASYNR ACLKR VDDO VSS VD[0] VD[2] CLKNO VDDO XTO XTI VIN4 VSSV VIN3 VDDV VIN2 VSSV VIN1 VDDV VDDA AIN5 AIN4 AIN3 AIN2 AIN1 AINN VSSA VDDO VSSAPLL SADD[0] RSTB VSS

16 VDDI

VD[3] VD[1] VD[4] CLKPO VSS TW2984 68pin QFN (8x8mm) VDDA AOUT VD[5] VD[6] VSS VDDI ADATM

FN8583 Rev.0.00 Page 7 of 123 September 24, 2013 Pin Descriptions Analog Video/Audio Interface Pins NAME NUMBER TYPE DESCRIPTION VIN1 62 A Composite video input channel 1. VIN2 64 A Composite video input channel 2. VIN3 66 A Composite video input channel 3. VIN4 68 A Composite video input channel 4. AIN1 55 A Audio input channel 1. AIN2 56 A Audio input channel 2. AIN3 57 A Audio input channel 3. AIN4 58 A Audio input channel 4. AIN5 59 A Audio input channel 5. AINN 54 A Audio input negative control. AOUT 51 A Audio output. Digital Video/Audio Interface Pins NAME NUMBER TYPE DESCRIPTION 22, 23, 24, 25 O Video data output. ACLKR 37 IO Audio serial clock input/output of record. ASYNR 38 IO Audio serial sync input/output of record. ADATR 39 O Audio serial data output of record. ADATM 40 O Audio serial data output of mixing. ACLKP 42 IO Audio serial clock input/output of playback. ASYNP 43 IO Audio serial sync input/output of playback. ADATP 44 I Audio serial data input of playback. ALINKI 13 I Audio Multi-chip operation serial input. ALINKO 45 O Audio Multi-chip operation serial output.

FN8583 Rev.0.00 Page 8 of 123 September 24, 2013 System Control Pins NAME NUMBER TYPE DESCRIPTION RSTB 9 I System reset. XTI 30 I Crystal 27MHz connection or Oscillator clock input. XTO 31 O For crystal 27MHz connection. CLKPO 27 O 36/72/144MHz or 27/54/108MHz clock output. CLKNO 28 O 36/72/144MHz or 27/54/108MHz clock output. TEST 5 I Test pin. Connect to ground. SCLK 10 I Serial control clock line. SDAT 11 IO Serial control data line. SADD[1:0] 7, 6 I Serial control address. IRQ 48 O Interrupt request output. Power and Ground Pins NAME NUMBER TYPE DESCRIPTION VDDI 8, 16, 34, 47 P 1.0V Power for internal logic. VDDO 14, 26, 32, 36, 46 P 3.3V Power for output driver. VSS 4, 12, 15, 21, 29, 33, 35, 41, 49 G Ground for internal logic and output driver. VDDV 1, 61, 65 P 3.3V Power for analog video ADC. VSSV 63, 67 G Ground for analog video ADC. VDDA 50, 60 P 3.3V Power for analog audio. VSSA 52, 53 G Ground for analog audio. VDDAPLL 2 P 3.3V Power for clock PLL. VSSAPLL 3 G Ground for clock PLL.

TABLE 1. ABSOLUTE MAXIMUM RATINGS impact product reliability and result in failures not covered by warranty. device. Voltage on any signal pin that exceeds the ranges list in Table 1 can induce destructive latch-up. TABLE 2. CHARACTERISTICS

FN8583 Rev.0.00 Page 10 of 123 September 24, 2013 PARAMETER SYMBOL MIN (NOTE 3) TYP MAX (NOTE 3) UNITS VIN1, VIN2, VIN3, VIN4 Input Range (AC Coupling Required) 0.5 1.0 1.4 V AIN1, AIN2, AIN3, AIN4, AIN5 Input Range (AC Coupling Required) 0.21 1.4 2.4 V Ambient Operating Temperature TA -40 +85 °C Analog Video Supply Current Ivddv - 80 - mA Analog Audio Supply Current Ivdda - 21 - mA Clock PLL Supply Current Ivddapll - 5 - mA Digital I/O Supply Current Iddo - 28 - mA Digital Core Supply Current Iddi - 54 - mA DIGITAL INPUTS Input High Voltage (TTL) VIH 2.0 - 3.6 V Input Low Voltage (TTL) VIL -0.3 - 0.8 V Input High Voltage (XTI) VIH 2.0 - V DDO + 0.5 V Input Low Voltage (XTI) VIL - - 0.8 V Input High Current (VIN = V DD ) IIH - - 10 µA Input Low Current (VIN = VSS) IIL -10 - - µA Input Capacitance (f = 1 MHz, VIN = 2.4V) CIN - 5 - pF DIGITAL OUTPUTS Output High Voltage (IOH = –2mA) VOH 2.4 - VDDO V Output Low Voltage (IOL = 2mA) VOL - 0.2 0.4 V 3-State Current IOZ - - 10 µA Output Capacitance CO - 5 - pF ANALOG VIDEO INPUT Analog Pin Input Voltage Vi - 1 - Vpp Analog Pin Input Capacitance CA - 7 - pF VIDEO ADCS ADC Resolution ADCR - 10 - bits ADC Integral Non-Linearity AINL - 1 - LSB ADC Differential Non-Linearity ADNL - 1 - LSB ADC Clock Rate fADC - 27 - MHz Video Bandwidth (-3db) BW - 10 - MHz

FN8583 Rev.0.00 Page 11 of 123 September 24, 2013 PARAMETER SYMBOL MIN (NOTE 3) TYP MAX (NOTE 3) UNITS HORIZONTAL PLL Line Frequency (50Hz) fLN - 15.625 - kHz Line Frequency (60Hz) fLN - 15.734 - KHz Static Deviation fH - - 6.2 % SUBCARRIER PLL Subcarrier Frequency (NTSC-M) fSC - 3579545 - Hz Subcarrier Frequency (PAL-BDGHI) fSC - 4433619 - Hz Subcarrier Frequency (PAL-M) fSC - 3575612 - Hz Subcarrier Frequency (PAL-N) fSC - 3582056 - Hz Lock In Range fH 450 - - Hz CRYSTAL SPEC Nominal Frequency (Fundamental) - 27 - MHz Deviation (Note 2) - - 50 ppm Load Capacitance CL - 18 - pF Series Resistor (ESR) RS - 50 - Ω OSCILLATOR INPUT Nominal Frequency - 27 - MHz Deviation - - 50 ppm Duty Cycle - - 55 % NOTE: 1. Supply current measurement is based on 0x93[2:0] = 6 setting. These bits should be set to 6 after power- on and resets. Lower settings will increase power consumption. 2. Crystal deviation is based on normal operation condition. 3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN8583 Rev.0.00 Page 12 of 123 September 24, 2013 Serial Host Interface Timing PARAMETER SYMBOL MIN (NOTE 1) TYP MAX (NOTE 1) UNITS Bus Free Time between STOP and START tBF 740 ns SDAT Setup Time tsSDAT 74 ns SDAT Hold Time thSDAT 50 900 ns Setup Time for START Condition tsSTA 370 ns Setup Time for STOP Condition tsSTOP 370 ns Hold Time for START Condition thSTA 74 ns Rise Time for SCLK and SDAT tR 300 ns Fall Time for SCLK and SDAT tF 300 ns Capacitive Load for each Bus Line CBUS 400 pF SCLK Clock Frequency fSCLK 400 KHz NOTE: 1. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Serial Host Interface Timing Diagram Stop Start Data StopStart SDAT SCLK tBF thSTA tsSTOtsSTA tsSDAT tR tF thSDAT

FN8583 Rev.0.00 Page 13 of 123 September 24, 2013 CLKPO and Video Data Timing PARAMETER SYMBOL MIN (NOTE 2) TYP MAX (NOTE 2) UNITS Setup from CLKPO(x1) to Video Data(x1) 1a 8 10 ns Hold from CLKPO(x1) to Video Data(x1) 1b 15 17 ns Setup from CLKPO(x2) to Video Data(x2) 2a 6 8 ns Hold from CLKPO(x2) to Video Data(x2) 2b 3 6 ns Setup from CLKPO(x1) to Video Data(x2) 3a 8 10 ns Hold from CLKPO(x1) to Video Data(x2) 3b 2 4 ns Setup from CLKPO(x4) to Video Data(x4) 4a 2 3.5 ns Hold from CLKPO(x4) to Video Data(x4) 4b 3 4 ns NOTE: 1. CLKPO timing is related with CLKPO_DEL register value. The following timing diagram is illustrated in the case that the CLKPO_DEL is set to 0hex and CLKPO_POL is set to 0.CLKNO timing is inversed CLKPO timing as default setting. CLKPO_DEL/CLKNO_DEL can make more timings. 2. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 2a 2b 3a 3b CLKPO (x2) Data Output (x2) CLKPO (x1) 4a 4b CLKPO (x4) Data Output (x4) 1a 1b Data Output (x1)

FN8583 Rev.0.00 Page 14 of 123 September 24, 2013 Digital Serial Audio Interface Timing PARAMETER SYMBOL MIN (NOTE 2) TYP MAX (NOTE 2) UNITS ASYNR, ADATR, ADATM Propagation Delay TA_pd 1.0 4 ns ACLKP High Pulse Duration TA_hw 27 ns ACLKP Low Pulse Duration TA_lw 54 ns ASYNP, ADATP Setup Time TA_su 26 ns ASYNP, ADATP Hold Time TA_h 25 ns NOTE: 1. TA_lw Min value and TA_su Min value are Fs=48KHz mode only.If Fs < 48KHz, these Min values are more bigger. High period of ACLKR/ACLKP is 36MHz one clock period. 2. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. ACLKR ASYNR tA_pd ADATR ADATM (A) RECORD AND MIX AUDIO(MASTER MODE) ACLKP ASYNP tA_su ADATP tA_htA_hw tA_lw (B) PLAYBACK AUDIO(MASTER MODE)

FN8583 Rev.0.00 Page 15 of 123 September 24, 2013 Analog Audio Parameters PARAMETER SYMBOL MIN (NOTE 4) TYP MAX (NOTE 4) UNITS ANALOG AUDIO INPUT CHARACTERISTICS AIN1-5 Input Impedance RINX 9.5 kΩ Interchannel gain mismatch 0.2 dB Input voltage range 0 1.4 2.4 Vpp Full scale input voltage (peak to peak) (Note 1) ViFULL 0.21 1.4 2.4 Vpp Interchannel Isolation (Note 2) 85 dB ANALOG AUDIO OUTPUT CHARACTERISTICS AOUT Output Load Resistance RLAO 300 ohm AOUT Load Capacitance CLAO 1 nF AOUT Offset Voltage VOSAO 300 mV Full Scale Output Voltage (Note 3) VoFULL 1.0 1.4 Vpp NOTE: 1. Tested at input gain of 0 dB, Fin = 1kHz. 2. Tested at input gain of 0 dB, Fs=8kHz and 16kHz. 3. Tested at output gain of 0 dB, Fout = 1kHz. 4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN8583 Rev.0.00 Page 16 of 123 September 24, 2013 Video Decoder VIDEO DECODER OVERVIEW The TW2984 is a low power NTSC/PAL video decoder chip that is designed for video surveillance applications. It consumes very low power in a typical composite input application. The available power down mode further reduces the power consumption. It uses the 1.0V for digital supply voltage and 3.3V for I/O and analog power. A single 27MHz crystal is all that needed to decode all analog video standards. The video decoder decodes the base-band analog CVBS into digital 8-bit 4:2:2 YCbCr for output. It consists of analog front-end with input source selection, variable gain amplifier and analog-to-digital converters, Y/C separation circuit, multi-standard color decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC 4.43) and synchronization circuitry. The Y/C separation is done with high quality adaptive 4H (5-line) comb filter for reduced cross color and cross luminance. The advanced synchronization processing circuitry can produce stable pictures for non-standard signal as well as weak signal. Analog Front End The analog front-end prepares and digitizes the AC coupled analog signal for further processing. Each channel has built-in anti-aliasing filter and 10-bit over-sampling ADCs. The characteristic of the filter is available in the filter curve section. The Y channel has additional 2-input multiplexer, and a variable gain amplifier for automatic gain control (AGC). It can support a maximum input voltage range of 1.4V without attenuation. Sync Processor The sync processor of TW2984 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video or component signal. The processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward. It allows the sampling of the video signal in line-locked fashion. Y/C Separation For NTSC and PAL standard signals, the luma/chroma separation can be done either by adaptive comb filtering or notch/band-pass filter combination. The default selection for NTSC/PAL is comb filter. The characteristics of the band-pass filter are shown in the filter curve section. TW2984 employs high quality 4-H (5-line) adaptive comb filter to reduce artifacts like hanging dots and crawling dots. Due to the line buffer used in the comb filter, there is always two lines processing delay in the output images no matter what standard or filter option is chosen. Color Demodulation The color demodulation of NTSC and PAL signal is done by first quadrature down mixing and then low- pass filtering. The low-pass filter characteristic can be selected for optimized transient color performance. For the PAL system, the PAL ID or the burst phase switching is identified to aid the PAL color demodulation. The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any sub-standard of NTSC and PAL to be demodulated easily with single crystal frequency.

frequency loss in video signal. The range of ACC control is –6db to +26db. status to switch-off the color. programmed appropriately for each of the composite video input formats. TABLE 3. VIDEO INPUT FORMATS SUPPORTED BY THE TW2984

NTSC-Japan has 0 IRE setup.

video characteristic. The Cb and Cr gain can be adjusted independently for flexibility. provided to prevent noise enhancement.

undershoot are also removed by special circuit to prevent false color generation at the color edge. four channel interfaces for synchronizing data. shows Video Decoder number to be output in this video stream. TABLE 4. THE CHANNEL ID FORMAT FOR 4X960H, 2X960H TIME-MULTIPLEXED FORMAT As default, m = 0 Video1 656 data, m = 1 Video2 656 data, m = 2 Video3 656 data, m = 3 Video4 656 data. When NOVID_656 register is set to 1, bit7 of Fourth byte of SAV/EAV code will be 0 when video signal is lost. This can be an optional set of 656 SAV/EAV code for no-video (video lost) specific application.

to identify no-video status using the NOVID_656 bit. FIGURE 2. TIMING DIAGRAM OF ITU-R BT.656 LIKE FORMAT TABLE 5. ITU-R BT.656 LIKE SAV AND EAV CODE SEQUENCE

Option includes video loss information in ITU-R BT.656 like format.

TABLE 6. SHOWS THE SPECIAL FORMAT OF ITU-R BT. 656 LIKE EMBEDDED TIMING CODE AND CHANNEL ID CODE register should be written after reset to enable outputs desired. Format is output on VD[7:0] pin.

Figure 6. The TW2984 can accept 5 analog audio signals and 1 digital serial audio data and produce 1 mixing analog audio signal and 2 digital serial audio data. the TW2984 provides the digital serial audio output via the ACLKR, ASYNR and ADATR pins. ASYNR pins that are shared with the digital serial audio record timing pins. special application. Usually, 4 AIN1/AIN2/AIN3/AIN4 audio data are only used on ADATR pin output.

FIGURE 6. BLOCK DIAGRAM OF AUDIO CODEC

FN8583 Rev.0.00 Page 25 of 123 September 24, 2013 AUDIO CLOCK MASTER/SLAVE MODE The TW2984 has two types of Audio Clock modes. If ACLKRMASTER register is set to 1, fs audio sample date is processed from audio clock internal ACKG (Audio Clock Generator) generates. In this master mode, ACLKR/ASYNR pins are output mode. ASYNROEN register for ASYNR pin should be set to 0 (output enable mode). If ACLKRMASTER register is set to 0, fs audio sample rate is processed from audio clock on ACLKR pin input. 256xfs, 320xfs or 384xfs audio clock should be connected to AC LKR pin from external master clock source in this slave mode. ASYNR pin can be input or output by external Audio clock master in slave mode. ASYNR signal should change per fs audio sample rate in both master and slave mode. AIN5MD and AFS384 register set up Audio fs mode by following table. REGISTER FS MODE AIN5MD AFS384 0 0 256xfs 1 0 320xfs 0 1 384xfs AUDIO DETECTION The TW2984 has an audio detector for individual 5 channels. There are 2 kinds of audio detection method defined by the ADET_TH. One is the detection of absolute amplitude and the other is of differential amplitude. For both detection methods, the accumulating period is defined by the ADET_FILT register and the detecting threshold value is defined by the ADET_TH1 ~ ADET_TH 5 registers. The detection of differential amplitude is recommended for most use. The status for audio detection is read by the STATE_AVDET register and it also makes the interrupt request through the IRQ pin with the combination of the status for video loss detection.

FN8583 Rev.0.00 Page 26 of 123 September 24, 2013 MULTI-CHIP OPERATION TW2984 can output 16 channel audio data on ACLKR/ASYNR/ADATR output simultaneously. Therefore, up to 4 chips should be connected on most Multi-Chip application cases. SMD register selects Audio cascade serial interface mode. If SMD register is set to 2, ALINKI pin is audio cascade serial input and ALINKO pin is audio cascade serial output mode. Each stage chip can accept 5 analog audio signals so that four cascaded chips will be 16-channel audio controller as default {AFS384, AIN5MD} = 00. The first stage chip provides 16ch digital serial audio data for record. Even though the first stage chip has only 1 digital serial audio data pin ADATR for record, the TW2984 can generate 16 channel data simultaneously using multi-channel method. In addition, each stage chip can support 4 channel record outputs that are corresponding with analog audio inputs. This first stage chip can also output 16 channel mixing audio data by the digital serial audio data and analog audio signal. The first stage chip accepts the digital serial audio data for playback. The digital playback data can be converted to analog signal by Digital-to-Analog converter in the first stage chip. Several Master/Slave mode configurations are available. Figure 7 is the most recommended and demanded system with Clock Master mode (ACLKRMASTER = 1). Figure 8 is the most recommended system with Clock Slave Sync Slave mode (ACLKRMASTER=0, ASYNROEN=1) . Other system combinations are also available if application need different type specific system. Figure 7 and Figure 8 show the most typical system. In the following FIGUREs, Mix1-16-51-54/Pb1 means Mix output of AIN1-16, AIN51-54 and Playback1. AIN1-16-51-54/Pb1 means one selected Audio output in AIN1-16-51-54/Pb1. If one of TW2984s uses {AFS384, AIN5MD} = 01 or {AFS384, AIN5MD} = 10, all other cascaded TW2984 chips must set up same {AFS384 AIN5MD} mode together. In Multi-Chip Audio operation mode, one same Oscillator clock source need to be connected to all TW2984 XTI pins.

FIGURE 7. RECOMMENDED CLOCK MASTER CASCADE MODE SYSTEM

FIGURE 8. RECOMMENDED CLOCK SLAVE SYNC SLAVE CASCADE MODE SYSTEM

follow a standard I2S or DSP interface as shown in Figure 9. FIGURE 9. FIG13 TIMING CHART OF SERIAL AUDIO INTERFACE data in left or right channel should be selected for playback audio by the PB_LRSEL.

and ADATR pins. Sampling frequency comes from 256xfs, 320xfs or 384xfs audio syste m clock setting. AIN5MD=0. Figure 10 shows the digital serial audio data organization for multi-channel audio. FIGURE 10. TIMING CHART OF MULTI-CHANNEL AUDIO RECORD Table 7 shows the sequence of audio data to be recorded for each mode of the R_MULTCH register. TABLE 7. SEQUENCE OF MULTI-CHANNEL AUDIO RECORD

FN8583 Rev.0.00 Page 31 of 123 September 24, 2013 (a) I2S Format R_MULTCH PIN LEFT CHANNEL RIGHT CHANNEL ADATR 0 8 ADATM F 7 ADATR 0 1 8 9 ADATM F E 7 6 ADATR 0 1 2 3 8 9 A B ADATM F E D C 7 6 5 4 ADATR 0 1 2 3 4 5 6 7 8 9 A B C D E F ADATM F E D C B A 9 8 7 6 5 4 3 2 1 0 (b) DSP Format R_MULTCH PIN LEFT/RIGHT CHANNEL ADATR 0 1 ADATM F E ADATR 0 1 2 3 ADATM F E D C ADATR 0 1 2 3 4 5 6 7 ADATM F E D C B A 9 8 ADATR 0 1 2 3 4 5 6 7 8 9 A B C D E F ADATM F E D C B A 9 8 7 6 5 4 3 2 1 0 Mix Output The digital serial audio data on the ADATM pin has 2 different audio data, which are mixing audio, and playback audio. The mixing digital serial audio data is the same as analog mixing output. The sampling frequency, bit width and number of audio for the ADATM pin are same as the ADATR pin because the ACLKR and ASYNR pins are shared with the ADATR and ADATM pins.

FIGURE 21. RM_SYNC=0, PB_MASTER=0, ADATPDLY=0 FIGURE 22. RM_SYNC=1, PB_MASTER=0, ADATPDLY=0 ACKI = round ( F AMCLK / F 27MHz * 2^23), it gives the Audio master Clock Nominal increment. ACKI registers make audio_source _clock by 27MHz clock. If MASCKMD=0, AMCLK=audio_source_clock.If MASCKMD=1, AMCLK=audio_source_clock/2. AMCLK is used as audio system clock and audio ADC clock in Master clock mode. ACPL=1(Loop open) should be used in TW2984 system. 256xfs mode: AFS384 = 0, AIN5MD = 0,MASCKMD = 1.

256 X 16 KHZ

FN8583 Rev.0.00 Page 37 of 123 September 24, 2013 320xfs mode: AFS384 = 0, AIN5MD = 1,MASCKMD = 1. AMCLK(MHZ) ACKI [DEC] ACKI [HEX] 320 x 16 KHz 5.12 3181457 30-8B-91 320 x 8 KHz 2.56 1590729 18-45-C9 384xfs mode: AFS384 = 1, AIN5MD=0,MASCKMD = 1. AMCLK(MHZ) ACKI [DEC] ACKI [HEX] 384 x 16 KHz 6.144 3817749 3A-41-15 384 x 8 KHz 3.072 1908874 1D-20-8A 256xfs mode: AFS384=0,AIN5MD=0,MASCKMD=0. AMCLK(MHZ) ACKI [DEC] ACKI [HEX] 256 x 48 KHz 12.288 3817749 3A-41-15 256 x 44.1KHz 11.2896 3507556 35-85-65 256 x 32 KHz 8.192 2545166 26-D6-0E 256 x 16 KHz 4.096 1272583 13-6B-07 256 x 8 KHz 2.048 636291 9-B5-83

FN8583 Rev.0.00 Page 38 of 123 September 24, 2013 320xfs mode: AFS384=0,AIN5MD=1,MASCKMD=0. AMCLK(MHZ) ACKI [DEC] ACKI [HEX] 320 x 32 KHz 10.24 3181457 30-8B-91 320 x 16 KHz 5.12 1590729 18-45-C9 320 x 8 KHz 2.56 795364 C-22-E4 384xfs mode: AFS384=1,AIN5MD=0,MASCKMD=0. AMCLK(MHZ) ACKI [DEC] ACKI [HEX] 384 x 32kHz 12.288 3817749 3A-41-15 384 x 16kHz 6.144 1908874 1D-20-8A 384 x 8kHz 3.072 954437 E-90-45 AUDIO CLOCK AUTO SETUP If ACLKRMASTER = 1 audio clock master mode is selected, and AFAUTO register is set to “1”,TW2984 set up ACKI register by AFMD register value automatically.ACKI control input in ACKG module block is automatically set up to the required value by the condition of AFS384 and AFS384 register value. AFAUTO AFMD ACKG MODULE ACKI CONTROL INPUT VALUE 1 0 8kHz mode value by each AFS384/AIN5MD case. 1 1 16kHz mode value by each AFS384/AIN5MD case. 1 2 32kHz mode value by each AFS384/AIN5MD case. 1 3 44.1kHz mode value by eachAFS384/AIN5MD case. 1 4 48kHz mode value by each AFS384/AIN5MD case. 0 X ACKI register set up ACKI control input value.

FN8583 Rev.0.00 Page 40 of 123 September 24, 2013 The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the TW2984 registers. SCLK is the serial clock and SDAT is the data line. Both lines are pulled high by resistors connected to VDDO. ICs communicate on the bus by pulling SCLK and SDAT low through open drain outputs. In normal operation the master generates all clock pulses, but control of the SDAT line alternates back and forth between the master and the slave. For both read and write, each byte is transferred MSB first, and the data bit is vali d whenever SCLK is high. The TW2984 is operated as a bus slave device. It can be programmed to respond to one of two 7 -bit slave device addresses by tying the SIAD[1:0] (Serial Interface Address) pins to either VDDOO or VSS (See below Table) through a pull-up or pull-down resister. The SIAD[1:0] pins are multi-purpose pins and must not tied to supply voltage or ground directly. If the SIAD[1:0] pins are tied to VDDO, then the least significant 2-bit of the 7-bit address is a “11”. If the SIAD[1:0] pins are tied to VSS then the least significant 2-bit of the 7-bit address is a “00”. The most significant 5-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to form the first byte transferred during a new transfer. If the read/write control bit is high,the next byte will be read from the slave device. If it is low, the next byte will be a write to the slave. When a bus master (the host microprocessor) drives SDA T from high to low, while SCLK is high, this is defined to be a start condition (See Figure 23). All slaves on the bus listen to determine when a start condition has been asserted. After a start condition, all slave devices listen for their device addresses. The host then sends a byte consisting of the 7-bit slave device ID and the R/W bit. This is shown in Figure 24. (For the TW2984, the next byte is normally the index to the TW2984 registers and is a write to the TW2984 therefore the first R/W bit is normally low.) After transmitting the device address and the R/W bit, the master must release the SDAT line while holding SCLK low, and wait for an acknowledgement from the slave. If the address matches the device address of a slave, the slave will respond by driving the SDAT line low to acknowledge the condition. The master will then continue with the next 8-bit transfer. If no device on the bus responds, the master transmits a stop condition and ends the cycle. Notice that a successful transfer always includes nine clock pulses. To write to the internal register of the TW2984, the master sends another 8-bits of data, the TW2984 loads this to the register pointed by the internal index register. The TW2984 will acknowledge the 8-bit data transfer and automatically increment the index in preparation for the next data. The master can do multiple writes to the TW2984 if they are in ascending sequential order. After each 8-bit transfer,the TW2984 will acknowledge the receipt of the 8-bits with an acknowledge pulse. To end all transfers to the TW2984 the host will issue a stop condition. SERIAL BUS INTERFACE 7-BIT SLAVE ADDRESS READ/WRITE BIT 0 1 0 1 0 SIAD[1] SIAD[0] 1=Read 0=Write A TW2984 read cycle has two phases. The first phase is a write to the internal index register. The second phase is the read from the data register. (See Figure 28). The host initiates the first phase by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit position. The index is then sent followed by either a stop condition or a second start condition. The second phase starts with the second start condition. The master then resends the same slave device ID with a 1 in the R/W bit position to indicate a read. The slave will transfer the contents of the desired register. The master remains in control of the clock. After transferring eight bits, the slave releases and the master takes control of the SDAT line and acknowledges the receipt of data to the slave. To terminate the last transfer the master will issue a negative acknowledge (SDAT is left high during a clock pulse) and issue a stop condition.

automatically, but has the same value as actual status of video and audio detection flag. FIGURE 26. TIMING DIAGRAM OF INTERRUPT INTERFACE

FN8583 Rev.0.00 Page 42 of 123 September 24, 2013 Video Decoder Filter Curves ANTI-ALIAS FILTER DECIMATION FILTER x 10 -40 -35 -30 -25 -20 -15 -10 Frequency (Hertz) Gain (dB) 0 2 4 6 8 10 12 14 16 18 x 10 -50 -45 -40 -35 -30 -25 -20 -15 -10 Frequency (Hertz) Magnitude Response (dB)

FN8583 Rev.0.00 Page 43 of 123 September 24, 2013 CHROMA BAND PASS FILTER CURVES LUMA NOTCH FILTER CURVE FOR NTSC AND PAL 0 1 2 3 4 5 6 7 8 x 10 -45 -40 -35 -30 -25 -20 -15 -10 Frequency (Hertz) Gain (dB) PAL/SEAM 0 1 2 3 4 5 6 7 8 9 x 10 -50 -45 -40 -35 -30 -25 -20 -15 -10 Frequency (Hertz) Magnitude Response (dB) NTSC PAL NTSC

FN8583 Rev.0.00 Page 44 of 123 September 24, 2013 CHROMINANCE LOW-PASS FILTER CURVE Low Med High Low Med High 0 1 2 3 4 5 6 x 10 -50 -45 -40 -35 -30 -25 -20 -15 -10 Frequency (Hertz) Gain (dB)CBW=0 CBW=3 CBW=1 CBW=2

FN8583 Rev.0.00 Page 45 of 123 September 24, 2013 PEAKING FILTER CURVES NTSC PAL 0 1 2 3 4 5 6 7 x 10 Frequency (Hertz) Magnitude Response (dB) 0 1 2 3 4 5 6 7 8 9 x 10 Frequency (Hertz) Magnitude Response (dB)

FN8583 Rev.0.00 Page 46 of 123 September 24, 2013 Audio Decimation Filter Response (*) 0.016 line = 0.016x64xFs

FN8583 Rev.0.00 Page 47 of 123 September 24, 2013 Control Register REGISTER MAP Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0x00 0x10 0x20 0x30 VIDSTAT * VDLOSS* HLOCK* SLOCK* FLD* VLOCK* Reserved* MONO* DET50* 0x01 0x11 0x21 0x31 BRIGHT BRIGHTNESS 0x02 0x12 0x22 0x32 CONTRAST CONTRAST 0x03 0x13 0x23 0x33 SHARPNESS SCURVE VSF CTI SHARPNESS 0x04 0x14 0x24 0x34 SAT_U SAT_U 0x05 0x15 0x25 0x35 SAT_V SAT_V 0x06 0x16 0x26 0x36 HUE HUE 0x07 0x17 0x27 0x37 CROP_HI VDELAY[9:8] VACTIVE[9:8] HDELAY[9:8] HACTIVE[9:8] 0x08 0x18 0x28 0x38 VDELAY_LO VDELAY[7:0] 0x09 0x19 0x29 0x39 VACTIVE_LO VACTIVE[7:0] 0x0A 0x1A 0x2A 0x3A HDELAY_LO HDELAY[7:0] 0x0B 0x1B 0x2B 0x3B HACTIVE_LO HACTIVE[7:0] 0x0C 0x1C 0x2C 0x3C MVSN* SF* PF* FF* KF* CSBAD* MCVSN* CSTRIPE* CTYPE* 0x0D 0x1D 0x2D 0x3D STATUS2* VCR* WKAIR* WKAIR1* VSTD* NINTL* 0 0 0 0x0E 0x1E 0x2E 0x3E SDT DETSTUS* STDNOW* ATREG STANDARD 0x0F 0x1F 0x2F 0x3F SDTR ATSTART PAL60EN PALCNEN PALMEN NTSC44EN SECAMEN PALBEN NTSCEN 0xA0 0xA1 0xA2 0xA3 NT50 NT50 CVSTD* CVFMT 0xA4 0xA5 0xA6 0xA7 IDCNTL IDX NSEN/SSEN/PSEN/WKTH 0xC4 0xC5 0xC6 0xC7 HREF* HREF* Note: * Read only registers Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0x50 VDFREQ VD4FREQ VD3FREQ VD2FREQ VD1FREQ H960EN4 H960EN3 H960EN2 H960EN1 0x51 FBITINV 0 0 0 0 FBITINV4 FBITINV3 FBITINV2 FBITINV1 0x52 ANADACTEST VCM_SEL LPF_SEL BIAS_SEL AN_ADACTEST 0x54 ASAVE 0 ADACLK_INV DOUT_RST DIV_RST ACALEN ASAVE 0x55 AAFLPF AAFLPF4 AAFLPF3 AAFLPF2 AAFLPF1 0x56 HASYNC HASYNC4 HASYNC3 HASYNC2 HASYNC1 HBLEN4[8] HBLEM3[8] HBLEN2[8] HBLEN1[8] 0x57 HBLEN1 HBLEM1[7:0] 0x58 HBLEN2 HBLEN2[7:0] 0x59 HBLEN3 HBLEN3[7:0]

FN8583 Rev.0.00 Page 48 of 123 September 24, 2013 Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0x5A HBLEN4 HBLEN4[7:0] 0x5B CKDS 0 0 0 0 PLLCKOUT XTI36 CKN_DS CLP_DS 0x5C BGCTL 0 0 BGCTL VSWEN VSWNUM 0x5D CH2MISC2 NKILL_2 PKILL_2 SKILL_2 CBAL_2 FCS_2 LCS_2 CCS_2 BST_2 0x5E CH3MISC2 NKILL_3 PKILL_3 SKILL_3 CBAL_3 FCS_3 LCS_3 CCS_3 BST_3 0x5F CH4MISC2 NKILL_4 PKILL_4 SKILL_4 CBAL_4 FCS_4 LCS_4 ICCS_4 BST_4 0x60 VCO CLK_DIFF CP_SEL LP_X8 VCO 0x61 XTIMD PLLRST PLL_PD PLL_IREF DECOSC SEL_144_72 SEL_108_54 XTIMD 0x62 O36M O36M4 O36M3 O36M2 O36M1 0x63 CH21NUM CH2NUM CH1NUM 0x64 CH43NUM CH4NUM CH3NUM 0x65 VDOEB 0 0 0 VD4ORD 0 VDOEB 0 0 0x67 HZST HZST 0x68 HZOOM_HI HZOOM4[9:8] HZOOM3[9:8] HZOOM2[9:8] HZOOM1[9:8] 0x69 HZOOM1_LOW HZOOM1[7:0] 0x6A HZOOM2_LOW HZOOM2[7:0] 0x6B HZOOM3_LOW HZOOM3[7:0] 0x6C HZOOM4_LOW HZOOM4[7:0] 0x6D D1 NMGAIN NMGAIN720 SHCOR720 0x6E PCLAMP720 PCLAMP720 0x70 ACLKPOL ACK36MD S2I_8BIT ACLKRPOL ACLKPPOL AFAUTO AFMD 0x71 AINCTL I2S8MODE MASCKMD PBINSWAP ASYNRDLY ASYNPDLY ADATPDLY INLAWMD 0x72 MRATIOMD MRATIOMD ADACTEST AOFFCORE DAORATIO DAOGAIN 0x73 A5NUM Reserved AIN51FORM AINTPOFF A51DET_ENA 0x74 A5DETST 0 0 0 0 0 0 0 A5DET_STATE* 0x75 AADC5OFS_H 0 0 0 0 0 0 AADC5OFS[9:8] 0x76 AADC5OFS_L AADCOFS[7:0] 0x77 AUD5ADC_H 0 0 0 0 0 0 AUD5ADC[9:8] 0x78 AUD5ADC_L AUD5ADC[7:0] 0x79 ADJAADC5_H 0 0 0 0 0 0 ADJAADC5[9:8] 0x7A ADJAADC5_L ADJAADC5[7:0] 0x7B I2SO_RSEL 0 0 0 I2SO_RSEL 0x7C I2SO_LSEL 0 0 0 I2SO_LSEL 0x7D RECSEL5 I2SRECSEL54 I2SRECSEL53 I2SRECSEL52 I2SRECSEL51 0x7E ADATMI2S A5OUTOFF ADATM_I2SOEN MIX_MUTE_A5 ADET_TH5[4:0] 0x7F AIGAIN5 AIGAIN5 MIX_RATIO5 0x80 SRST 0 0 AUDIORST VOUTRST VDEC4RST VDEC3RST VDEC2RST VDEC1RST 0x81 ACNTL 0 0 0 0 CLKPDN 0 YFLEN 0

FN8583 Rev.0.00 Page 49 of 123 September 24, 2013 Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0x82 ACNTL2 CTEST YCLEN CKIPOL 0 GTEST VLPF CKLY CKLC 0x83 CNTRL1 PBW DEM IDSNS SET7 COMB HCOMP YCOMB PDLY 0x84 CKHY GMEN CKHY HSDLY 0x85 SHCOR960 SHCOR960 VIN4 VIN3 VIN2 VIN1 0x86 CORING CTCOR CCOR VCOR CIF 0x87 CLMPG CLPEND CLPST 0x88 IAGC NMGAIN960 WPGAIN 0 0x89 AIN5MD ATHROUGH ASYNSERIAL ACLKR128 ACLKR64 AFS384 AIN5MD 0 0 0x8A PEAKWT PEAKWT 0x8B CLMPL CLMPLD CLMPL 0x8C SYNCT SYNCTD SYNCT 0x8D MISSCNT MISSCNT HSWIN 0x8E PCLAMP960 PCLAMP960 0x8F VCNTL1 VLCKI VLCKO VMODE DETV AFLD VINT 0x90 VCNTL2 BSHT VSHT 0x91 CKILL CKILMAX CKILMIN 0x92 VTL HTL VTL 0x93 LDLY CKLM YDLY PD_BIAS VSAVE 0x94 MISC1 HPLC EVCNT PALC SDET 0 BYPASS 0 0x95 CBW HPM ACCT SPM CBW 0x96 MISC2 NKILL PKILL SKILL CBAL FCS LCS CCS BST 0x97 CLMD FRM YNR CLMD PSP

FN8583 Rev.0.00 Page 50 of 123 September 24, 2013 Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0x9C OVSEND 0 OFDLY 0 0 0 0 0x9E NOVID VDELAYMD FC27 CHID_MD NOVID_656 EAVSWAP VIPCFG NTSC656 0x9F CLKODEL CLKNO_DEL CLKPO_DEL 0xAA AGCEN AGCEN4 AGCEN3 AGCEN2 AGCEN1 AGCGAIN4[8] AGCGAIN3[8] AGCGAIN2[8] AGCGAIN1[8] 0xAB AGCGAIN1 AGCGAIN1[7:0] 0xAC AGCGAIN2 AGCGAIN2[7:0] 0xAD AGCGAIN3 AGCGAIN3[7:0] 0xAE AGCGAIN4 AGCGAIN4[7:0] 0xAF VSHP21 0 VSHP2 0 VSHP1 0xB0 VSHP43 0 VSHP4 0 VSHP3 0xB1 CH8IDEN CH8IDEN 0 0 0 CLPOE TESTVNUM 0xB2 VADC_CKPOL VADC_CKPOL4 VADC_CKPOL3 VADC_CKPOL2 VADC_CKPOL1 0xB3 AADCOFS_H AADC4OFS[9:8] AADC3OFS[9:8] AADC2OFS[9:8] AADC1OFS[9:8] 0xB4 AADC1OFS_L AADC1OFS[7:0] 0xB5 AADC2OFS_L AADC2OFS[7:0] 0xB6 AADC3OFS_L AADC3OFS[7:0] 0xB7 AADC4OFS_L AADC4OFS[7:0] 0xB8 AUDADC_H* AUD4ADC[9:8] AUD3ADC[9:8] AUD2ADC[9:8] AUD1ADC[9:8] 0xB9 AUD1ADC_L* AUD1ADC[7:0] 0xBA AUD2ADC_L* AUD2ADC[7:0] 0xBB AUD3ADC_L* AUD3ADC[7:0] 0xBC AUD4ADC_L* AUD4ADC[7:0] 0xBD ADJAADC_H* ADJAADC4[9:8] ADJAADC3[9:8] ADJAADC2[9:8] ADJAADC1[9:8] 0xBE ADJAADC1_L* ADJAADC1[7:0] 0xBF ADJAADC2_L* ADJAADC2[7:0] 0xC0 ADJAADC3_L* ADJAADC3[7:0] 0xC1 ADJAADC4_L* ADJAADC4[7:0]

FN8583 Rev.0.00 Page 51 of 123 September 24, 2013 Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0xCA CHMD CHMD 0xCC SELCH SELCH 0xCD MAINCH MAINCH 0xCE ANAPWDN AAUTOMUTE Reserved A_DAC_PWDN A_ADC_PWDN VADC_PWDN 0xCF SMD SMD 0 0 0 0 0 0 0xD0 AIGAIN21 AIGAIN2 AIGAIN1 0xD1 AIGAIN43 AIGAIN4 AIGAIN3 0xD2 R_MULTCH M_RLSWAP RM_SYNC RM_PBSEL R_ADATM R_MULTCH 0xD3 R_SEQ10 R_SEQ_1 R_SEQ_0 0xD4 R_SEQ32 R_SEQ_3 R_SEQ_2 0xD5 R_SEQ54 R_SEQ_5 R_SEQ_4 0xD6 R_SEQ76 R_SEQ_7 R_SEQ_6 0xD7 R_SEQ98 R_SEQ_9 R_SEQ_8 0xD8 R_SEQBA R_SEQ_B R_SEQ_A 0xD9 R_SEQDC R_SEQ_D R_SEQ_C 0xDA R_SEQFE R_SEQ_F R_SEQ_E

FN8583 Rev.0.00 Page 52 of 123 September 24, 2013 Address Mnemonic BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CH1 CH2 CH3 CH4 0xDB AMASTER ADACEN AADCEN PB_MASTER PB_LRSEL PB_SYNC RM_8BIT ASYNROEN ACLKRMASTER 0xDC MIX_MUTE LAWMD MIX_DERATIO MIX_MUTE 0xDD MIX_RATIO21 MIX_RATIO2 MIX_RATIO1 0xDE MIX_RATIO43 MIX_RATIO4 MIX_RATIO3 0xDF MIX_RATIOP AOGAIN MIX_RATIOP 0xE0 MIX_OUTSEL 0 AADCCKPOL ADACCKPOL MIX_OUTSEL 0xE1 ADET AAMPMD ADET_FILT ADET_TH4[4] ADET_TH3[4] ADET_TH2[4] ADET_TH1[4] 0xE2 ADET_TH21 ADET_TH2[3:0] ADET_TH1[3:0] 0xE3 ADET_TH43 ADET_TH4[3:0] ADET_TH3[3:0] 0xF0 ACKI_L ACKI[7:0] 0xF1 ACKI_M ACKI[15:8] 0xF2 ACKI_H 0 0 ACKI[21:16] 0xF3 ACKN_L ACKN[7:0] 0xF4 ACKN_M ACKN[15:8] 0xF5 ACKN_H 0 0 0 0 0 0 ACKN[17:16] 0xF6 SDIV 0 0 SDIV 0xF7 LRDIV 0 0 LRDIV 0xF8 ACCNTL APZ APG Reserved ACPL SRPH LRPH 0xF9 VMISC LIM16 PBREFEN YCBCR422 Reserved VBI_FRAM CNTL656 CLKNF CLKPF 0xFA CLKOCTL 0 OE CLKNO_OEB CLKPO_OEB CLKNO_MD CLKPO_MD 0xFB AVDET_MODE CLKNO_POL CLKPO_POL IRQENA IRQPOL ADET_MODE VDET_MODE 0xFC AVDET_ENA AVDET_ENA 0xFD AVDET_STATE* AVDET_STATE 0xFE TEST DEV_ID[6:5]* 0 0 0 TEST 0xFF DEV_ID* DEV_ID[4:0]* REV_ID Note: * Read only registers

FN8583 Rev.0.00 Page 53 of 123 September 24, 2013 Register Descriptions 0X00(CH1)/0X10(CH2)/0X20(CH3)/0X30(CH4) – VIDEO STATUS REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7 VDLOSS R 1 = Video not present. (sync is not detected in number of consecutive line periods specified by MISSCNT register) 0 = Video detected. 6 HLOCK R 1 = Horizontal sync PLL is locked to the incoming video source. 0 = Horizontal sync PLL is not locked. 5 SLOCK R 1 = Sub-carrier PLL is locked to the incoming video source. 0 = Sub-carrier PLL is not locked. 4 FIELD R 0 = Odd field is being decoded. 1 = Even field is being decoded. 3 VLOCK R 1 = Vertical logic is locked to the incoming video source. 0 = Vertical logic is not locked.

2 Reserved R Reserved 0

1 MONO R 1 = No color burst signal detected. 0 = Color burst signal detected.

0 DET50 R 0 = 60Hz source detected

1 = 50Hz source detected The actual vertical scanning frequency depends on the current standard invoked. 0X01(CH1)/0X11(CH2)/0X21(CH3)/0X31(CH4) – BRIGHTNESS CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-0 BRIGHT R/W These bits control the brightness. They have value of –128 to 127 in 2's complement form. Positive value increases brightness. A value 0 has no effect on the data. 0X02(CH1)/0X12(CH2)/0X22(CH3)/0X32(CH4) – CONTRAST CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-0 CNTRST R/W These bits control the luminance contrast gain. A value of 100 (64h) has a gain of 1. The range of adjustment is from 0% to 255% at 1% per step. 64h

FN8583 Rev.0.00 Page 54 of 123 September 24, 2013 0X03(CH1)/0X13(CH2)/0X23(CH3)/0X33(CH4) – SHARPNESS CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7 SCURVE R/W This bit controls the center frequency of the peaking filter. The corresponding gain adjustment is HFLT. 0 = low 1 = center 6 VSF R/W This bit is for internal used. 0 5-4 CTI R/W CTI level selection. 0 = None. 3 = highest. 1 3-0 SHARP R/W These bits control the amount of sharpness enhancement on the luminance signals. There are 16 levels of control with ‘0’ having no effect on the output image. 1 through 15 provides sharpness enhancement with ‘F’ being the strongest. 0X04(CH1)/0X14(CH2)/0X24(CH3)/0X34(CH4) – CHROMA (U) GAIN REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-0 SAT_U R/W These bits control the digital gain adjustment to the U (or Cb) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%. 0X05(CH1)/0X15(CH2)/0X25(CH3)/0X35(CH4) – CHROMA (V) GAIN REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-0 SAT_V R/W These bits control the digital gain adjustment to the V (or Cr) component of the digital video signal. The color saturation can be adjusted by adjusting the U and V color gain components by the same amount in the normal situation. The U and V can also be adjusted independently to provide greater flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has gain of 100%.

FN8583 Rev.0.00 Page 55 of 123 September 24, 2013 0X06(CH1)/0X16(CH2)/0X26(CH3)/0X36(CH4) – HUE CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-0 HUE R/W These bits control the color hue as 2's complement number. They have value from +90o (7Fh) to -90o (80h) with an increment of 2.8o. The 2 LSB has no effect. The positive value gives greenish tone and negative value gives purplish tone. The default value is 0o (00h). This is effective only on NTSC and PAL system. 0X07(CH1)/0X17(CH2)/0X27(CH3)/0X37(CH4) – CROPPING REGISTER, HIGH BIT FUNCTION R/W DESCRIPTION RESET 7-6 VDELAY_HI R/W These bits are bit 9 to 8 of the 10-bit Vertical Delay register. 0 5-4 VACTIVE_HI R/W These bits are bit 9 to 8 of the 10-bit VACTIVE register. Refer to description on Reg09 for its shadow register. 3-2 HDELAY_HI R/W These bits are bit 9 to 8 of the 10-bit Horizontal Delay register. 0 1-0 HACTIVE_HI R/W These bits are bit 9 to 8 of the 10-bit HACTIVE register. 2 0X08(CH1)/0X18(CH2)/0X28(CH3)/0X38(CH4) – VERTICAL DELAY REGISTER, LOW BIT FUNCTION R/W DESCRIPTION RESET 7-0 VDELAY_LO R/W These bits are bit 7 to 0 of the 10-bit Vertical Delay register. The two MSBs are in the CROP_HI register. It defines the number of lines between the leading edge of VSYNC and the start of the active video. 0X09(CH1)/0X19(CH2)/0X29(CH3)/0X39(CH4) – VERTICAL ACTIVE REGISTER, LOW BIT FUNCTION R/W DESCRIPTION RESET 7-0 VACTIVE_LO R/W These bits are bit 7 to 0 of the 10-bit Vertical Active register. The two MSBs are in the CROP_HI register. It defines the number of active video lines per frame output. The VACTIVE register has a shadow register for use with 50Hz source when ATREG of Reg0x1C is not set. This register can be accessed through the same index address by first changing the format standard to any 50Hz standard.

FN8583 Rev.0.00 Page 56 of 123 September 24, 2013 0X0A(CH1)/0X1A(CH2)/0X2A(CH3)/0X3A(CH4) – HORIZONTAL DELAY REGISTER, LOW BIT FUNCTION R/W DESCRIPTION RESET 7-0 HDELAY_LO R/W These bits are bit 7 to 0 of the 10-bit Horizontal Delay register. The two MSBs are in the CROP_HI register. It defines the number of pixels between the leading edge of the HSYNC and the start of the image cropping for active video. The HDELAY_LO register has two shadow registers for use with PAL and SECAM sources respectively. These register can be accessed using the same index address by first changing the decoding format to the corresponding standard. 0X0B(CH1)/0X1B(CH2)/0X2B(CH3)/0X3B(CH4) – HORIZONTAL ACTIVE REGISTER, LOW BIT FUNCTION R/W DESCRIPTION RESET 7-0 HACTIVE_LO R/W These bits are bit 7 to 0 of the 10-bit Horizontal Active register. The two MSBs are in the CROP_HI register. It defines the number of active pixels per line output.

FN8583 Rev.0.00 Page 57 of 123 September 24, 2013 0X0C(CH1)/0X1C(CH2)/0X2C(CH3)/0X3C(CH4) – MACROVISION DETECTION BIT FUNCTION R/W DESCRIPTION RESET 7 SF R This bit is for internal use. 0 6 PF R This bit is for internal use. 0 5 FF R This bit is for internal use. 0 4 KF R This bit is for internal use. 0

3 CSBAD R 1 = Macrovision color stripe detection may be un-reliable 0

2 MVCSN R 1 = Macrovision AGC pulse detected. 0 = Not detected. 1 CSTRIPE R 1 = Macrovision color stripe protection burst detected. 0 = Not detected. 0 CTYPE R This bit is valid only when color stripe protection is detected, i.e. CSTRIPE=1. 1 = Type 2 color stripe protection 0 = Type 3 color stripe protection

FN8583 Rev.0.00 Page 58 of 123 September 24, 2013 0X0D(CH1)/0X1D(CH2)/0X2D(CH3)/0X3D(CH4) – CHIP STATUS II BIT FUNCTION R/W DESCRIPTION RESET 7 VCR R VCR signal indicator. 0 6 WKAIR R Weak signal indicator 2. 0 5 WKAIR1 R Weak signal indicator controlled by WKTH. 0

4 VSTD R 1 = Standard signal 0 = Non-standard signal 0

3 NINTL R 1 = Non-interlaced signal 0 = interlaced signal 0

2-0 Reserved R Reserved 0h 0X0E(CH1)/0X1E(CH2)/0X2E(CH3)/0X3E(CH4) – STANDARD SELECTION BIT FUNCTION R/W DESCRIPTION RESET

7 DETSTUS R 0 = Idle 1 = detection in progress 0

6-4 STDNOW R Current standard invoked 0 = NTSC(M) 1 = PAL (B,D,G,H,I) 2 = SECAM 3 = NTSC4.43 4 = PAL (M) 5 = PAL (CN) 6 = PAL 60 7 = Not valid 3 ATREG R/W 1 = Disable the shadow registers. 0 = Enable VACTIVE and HDELAY shadow registers value depending on standard 2-0 STD R/W Standard selection 0 = NTSC(M) 1 = PAL (B,D,G,H,I) 2 = SECAM(not supported) 3 = NTSC4.43 4 = PAL (M) 5 = PAL (CN) 6 = PAL 60 7 = Auto detection

FN8583 Rev.0.00 Page 59 of 123 September 24, 2013 0X0F(CH1)/0X1F(CH2)/0X2F(CH3)/0X3F(CH4) – STANDARD RECOGNITION BIT FUNCTION R/W DESCRIPTION RESET

7 ATSTART R/W Writing 1 to this bit will manually initiate the auto format detection

process. This bit is a self-resetting bit. 6 PAL6_EN R/W 1 = enable recognition of PAL60. 0 = disable recognition. 5 PALN_EN R/W 1 = enable recognition of PAL (CN). 0 = disable recognition. 4 PALM_EN R/W 1 = enable recognition of PAL (M). 0 = disable recognition. 3 NT44_EN R/W 1 = enable recognition of NTSC 4.43. 0 = disable recognition. 2 SEC_EN R/W 1 = enable recognition of SECAM. 0 = disable recognition. 1 PALB_EN R/W 1 = enable recognition of PAL (B,D,G,H,I). 0 = disable recognition. 0 NTSC_EN R/W 1 = enable recognition of NTSC (M). 0 = disable recognition.

FN8583 Rev.0.00 Page 60 of 123 September 24, 2013 0X56(CH1/CH2/CH3/CH4) – HASYNC BIT FUNCTION R/W DESCRIPTION RESET

7 HASYNC4 R/W 1: the length of EAV to SAV is set up and fixed by CH4 HBLEN

registers. 0: the length of SAV to EAV is set up and fixed by CH4 HACTIVE registers.

6 HASYNC3 R/W 1: the length of EAV to SAV is set up and fixed by CH3 HBLEN

registers. 0: the length of SAV to EAV is set up and fixed by CH3 HACTIVE registers.

5 HASYNC2 R/W 1: the length of EAV to SAV is set up and fixed by CH2 HBLEN

registers. 0: the length of SAV to EAV is set up and fixed by CH2 HACTIVE registers.

4 HASYNC1 R/W 1: the length of EAV to SAV is set up and fixed by CH1 HBLEN

registers. 0: the length of SAV to EAV is set up and fixed by CH1 HACTIVE registers. 3 HBLEN4[8] R/W Bit8 of CH4 HBLEN[8:0].Please see HBLEN description. 0 2 HBLEN3[8] R/W Bit8 of CH3 HBLEN[8:0]. Please see HBLEN description. 0 1 HBLEN2[8] R/W Bit8 of CH2 HBLEN[8:0]. Please see HBLEN description. 0 0 HBLEN1[8] R/W Bit8 of CH1 HBLEN[8:0]. Please see HBLEN description. 0 0X57(CH1)/0X58(CH2)/0X59(CH3)/0X5A(CH4) – HBLEN BIT FUNCTION R/W DESCRIPTION RESET 7-0 HBLENn[7:0] n=1,2,3,4 R/W These bits are effective when HASYNC bit is set to 1.These bits set up the length of EAV to SAV code when HASYNC bit is 1.Normal value is (Total pixel per line – HACTIVE) value.HBLENn[8] is 0 normally. HBLENn[8] is optional purpose only. 36MHz WD1 Vdeo Decoder mode. NTSC/PAL-M(60Hz): B8h(184dec)=1144-960 PAL/SECAM(50Hz): C0h(192dec)=1152-960 27MHz D1 Vdeo Decoder mode. NTSC/PAL-M(60Hz): 8Ah(138dec)=858-720 PAL/SECAM(50Hz): 90h(144dec)=864-720 90h

FN8583 Rev.0.00 Page 61 of 123 September 24, 2013 0X68(CH1/CH2/CH3/CH4) – HZOOM_HI BIT FUNCTION R/W DESCRIPTION RESET 7-6 HZOOM4 [9:8] R/W Bit9-8 of CH4 HZOOM registers. 0 5-4 HZOOM3 [9:8] R/W Bit9-8 of CH3 HZOOM registers. 0 3-2 HZOOM2 [9:8] R.W Bit9-8 of CH2 HZOOM registers. 0 1-0 HZOOM1 [9:8] R/W Bit9-8 of CH1 HZOOM registers. 0 0X69(CH1)/0X6A(CH2)/0X6B(CH3)/0X6C(CH4) – HZOOM_LOW BIT FUNCTION R/W DESCRIPTION RESET 7-0 HZOOM [7:0] R/W Bit7-0 of Horizontal Zoom Up register.This register has Horizontal Zoom Up fcuntion together HZOOMn[9:8] by following equation. HZOOM[9:0] = 1024 x source H pixel number / output H pixel number. For example, source H pixel numer = 948 Output H pixel number = 960 HZOOM[9:0] = 1024 x 948 / 960 = 1011.2 = 3F3h. If HZOOM=000h is set up,No HZOOM(path through) output. 00h 0XA0(CH1)/0XA1(CH2)/0XA2(CH3)/0XA3(CH4) – NT50 BIT FUNCTION R/W DESCRIPTION RESET 7 NT50 R/W 1 = Force decoding format to 50Hz NTSC. 0 = decoding format is set by register Standard Selection. 6-4 VSTD R/W Reserved 0h 3-0 CVFMT R/W Reserved 8h

FN8583 Rev.0.00 Page 62 of 123 September 24, 2013 0XA4(CH1)/0XA5(CH2)/0XA6(CH3)/0XA7(CH4) – ID DETECTION CONTROL BIT FUNCTION R/W DESCRIPTION RESET 7-6 IDX R/W These two bits indicate which of the four lower 6-bit registers is currently being controlled. The write sequence is a two steps process unless the same register is written. A write of {ID,000000} selects one of the four registers to be written. A subsequent write will actually write into the register. 5-0 NSEN / SSEN / PSEN / WKTH R/W IDX = 0 controls the NTSC color carrier detection sensitivity (NSEN). IDX = 1 controls the SECAM ID detection sensitivity (SSEN). IDX = 2 controls the PAL ID detection sensitivity (PSEN). IDX = 3 controls the weak signal detection sensitivity (WKTH). 1A / 20 / 1C / 0XAA(CH1/CH2/CH3/CH4) – VIDEO AGC CONTROL BIT FUNCTION R/W DESCRIPTION RESET

7 AGCEN4 R/W Select Video AGC loop function on VIN4

0: AGC loop function enabled (recommended for most application cases) 1: AGC loop function disabled. Gain is set by AGCGAIN4

6 AGCEN3 R/W Select Video AGC loop function on VIN3

0: AGC loop function enabled (recommended for most application cases) 1: AGC loop function disabled. Gain is set by AGCGAIN3

5 AGCEN2 R/W Select Video AGC loop function on VIN2

0: AGC loop function enabled (recommended for most application cases) 1: AGC loop function disabled. Gain is set by AGCGAIN2

4 AGCEN1 R/W Select Video AGC loop function on VIN1

0: AGC loop function enabled (recommended for most application cases) 1: AGC loop function disabled. Gain is set by AGCGAIN1

3 AGCGAIN4[8] R/W AGCGAIN4 MSB bit 0

2 AGCGAIN3[8] R/W AGCGAIN3 MSB bit 0

1 AGCGAIN2[8] R/W AGCGAIN2 MSB bit 0

0 AGCGAIN1[8] R/W AGCGAIN1 MSB bit 0

FN8583 Rev.0.00 Page 63 of 123 September 24, 2013 0XAB(CH1)/0XAC)CH2)/0XAD(CH3)/0XAE(CH4) – VIDEO AGC CONTROL BIT FUNCTION R/W DESCRIPTION RESET 7-0 AGCGAIN[7:0] R/W To control the AGC Gain when AGC loop is disabled. AGCGAIN bit7-0. F0h 0XC4(CH1)/0XC5(CH2)/0XC6(CH3)/0XC7(CH4) – H MONITOR BIT FUNCTION R/W DESCRIPTION RESET 7-0 HFREF R Horizontal line frequency indicator (Test purpose only) X

FN8583 Rev.0.00 Page 64 of 123 September 24, 2013 0X50 – VDFREQ/H960EN BIT FUNCTION R/W DESCRIPTION RESET

7 Reserved R/W 0

6 VDFREQ R/W 1 : VD[7:0] pin output 36MHz video data. 0 : VD[7:0] pin output 27MHz video data. 5-4 Reserved R/W 0h 3 H960EN4 R/W 1 : Ch4 video decoder is in 36MHz WD1 mode. 0 : Ch4 video decoder is in 27MHz D1 mode. 2 H960EN3 R/W 1 : Ch3 video decoder is in 36MHz WD1 mode. 0 : Ch3 video decoder is in 27MHz D1 mode. 1 H960EN2 R/W 1 : Ch2 video decoder is in 36MHz WD1 mode. 0 : Ch2 video decoder is in 27MHz D1 mode. 0 H960EN1 R/W 1 : Ch1 video decoder is in 36MHz WD1 mode. 0 : Ch1 video decoder is in 27MHz D1 mode. 0X51 – FBITINV BIT FUNCTION R/W DESCRIPTION RESET 7-4 Reserved R 0h 3 FBITINV4 R/W 1 : F-bit in 4th byte of 656 EAV/SAV code is inversed. 0 : normal mode.F-bit is not inversed. 2 FBITINV3 R/W 1 : F-bit in 4th byte of 656 EAV/SAV code is inversed. 0 : normal mode.F-bit is not inversed. 1 FBITINV2 R/W 1 : F-bit in 4th byte of 656 EAV/SAV code is inversed. 0 : normal mode.F-bit is not inversed. 0 FBITINV1 R/W 1 : F-bit in 4th byte of 656 EAV/SAV code is inversed. 0 : normal mode.F-bit is not inversed.

FN8583 Rev.0.00 Page 65 of 123 September 24, 2013 0X52 – AUDIO DAC CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7 VCM_SEL R/W Reserved. 0 5-4 LPF_SEL R/W Audio DAC LPF corner frequency selection. 0h : 15.6kHz 1h : 7.8kHz 2h : Don’t use 3h : 3.9kHz 4h,5h,6h : Don’t use 7h : 2.6kHz 3 BIAS_SEL R/W Bias selection. 0 : AVDD33 as the reference voltage. 1 : select bandgap voltage as the reference. 2-0 ADACTEST R/W Audio DAC Test control. 0h : normal operation 1h : ibias places to the dac_out(Don’t use) 2h : din_0 is placed to the dac_out(Don’t use) 3h : both ibias and din_0 are placed at the dac_out(Don’t use) 4h : disable output driver.Dac_out floating 5h : disable output driver,ibias places to dac_out 6h : disable output driver,din_0 places to dac_out 7h : don’t use 0X54 – AUDIO ADC CONTROL 1 BIT FUNCTION R/W DESCRIPTION RESET

7 Reserved R 0

6 ADACLK_INV R/W Audio DAC clock inversion. 0 : not inversed inside audio DAC. 1 : Clock is inversed inside audio DAC. 5 DOUT_RST R/W Audio ADC digital output reset for all channel. Test purpose only. This bit must be set up to 0 again after 1 value is set up. 4 DIV_RST R/W Audio ADC divider reset.Test purpose Only. This bit must be set up to 0 again after 1 value is set up. 3 ACALEN RW Audio ADC Calibration control.Test purpose only. This bit must be set up to 0 again after 1 value is set up. 2-0 ASAVE R/W 7h : normal mode. Others : test purpose only. 7

FN8583 Rev.0.00 Page 66 of 123 September 24, 2013 0X55 – VIDEO INPUT ANTI-ALIASING FILTER SELECTION BIT FUNCTION R/W DESCRIPTION RESET 7-6 AAFLPF4 R/W Ch4 Video input Anti-aliasing filter selection. 0h : 9MHz,0dB gain. 1h : 10MHz,-3.4dB gain. 2h : 7MHz,0db gain. 3h : 8MHz,-3.4dB gain. 5-4 AAFLPF3 R/W Ch3 Video input Anti-aliasing filter selection. 0h : 9MHz,0dB gain. 1h : 10MHz,-3.4dB gain. 2h : 7MHz,0db gain. 3h : 8MHz,-3.4dB gain. 3-2 AAFLPF2 R/W Ch2 Video input Anti-aliasing filter selection. 0h : 9MHz,0dB gain. 1h : 10MHz,-3.4dB gain. 2h : 7MHz,0db gain. 3h : 8MHz,-3.4dB gain. 1-0 AAFLPF1 R/W Ch1 Video input Anti-aliasing filter selection. 0h : 9MHz,0dB gain. 1h : 10MHz,-3.4dB gain. 2h : 7MHz,0db gain. 3h : 8MHz,-3.4dB gain. 0X5B – CLOCK OUTPU PIN DRIVE SELECTION BIT FUNCTION R/W DESCRIPTION RESET 7-4 Reserved R 0 3 PLLCKOUT R/W 1 : IRQ pin output PLL 36MHz clock. CLKPO pin output PLL 144MHz clock. CLKNO pin output PLL 108MHz clock. Test purpose only. 0 : normal mode. 2 XTI36 R/W 0 : XTI pin is normal 27MHz input. 1 : Special WD1 mode.XTI pin is one of 36MHz/72MHz/144MHz input. 27MHz/54MHz/108MHz D1 mode is not supported in this special mode. 1 CKN_DS R/W 0 : CLKNO pin output is 12mA current drive mode. 1 : CLKNO pin output is 16mA current drive mode. 0 CKP_DS R/W 0 : CLKPO pin output is 12mA current drive mode. 1 : CLKPO pin output is 16mA current drive mode.

FN8583 Rev.0.00 Page 67 of 123 September 24, 2013 0X5C– BGCTL BIT FUNCTION R/W DESCRIPTION RESET 7-6 Reserved R 0 5 BGCTL R/W 0: Reg96[7:0] control all CH1/CH2/CH3/CH4 video. 1: Reg96[7:0] control only CH1 video. Reg5D[7:0] control only CH2 video. Reg5E[7:0] control only CH3 video. Reg5F[7:0] control only CH4 video. 4-0 Reserved R/W 0h

FN8583 Rev.0.00 Page 68 of 123 September 24, 2013 0X5D – CH2 MISCELLANEOUS CONTROL II ON BGCTL=1 BIT FUNCTION R/W DESCRIPTION RESET 7 NKILL_2 R/W 1 = Enable noisy signal color killer function in NTSC mode. 0 = Disabled. 6 PKILL_2 R/W 1 = Enable automatic noisy color killer function in PAL mode. 0 = Disabled. 5 SKILL_2 R/W 1 = Enable automatic noisy color killer function in SECAM mode. 0 = Disabled.

4 CBAL_2 R/W 0 = Normal output

1 = special output mode. 3 FCS_2 R/W 1 = Force decoder output value determined by CCS. 0 = Disabled.

2 LCS_2 R/W 1 = Enable pre-determined output value indicated by CCS when video loss

is detected. 0 = Disabled.

1 CCS_2 R/W When FCS is set high or video loss condition is detected when LCS is set

high, one of two colors display can be selected. 1 = Blue color. 0 = Black. 0 BST_2 R/W 1 = Enable blue stretch. 0 = Disabled.

FN8583 Rev.0.00 Page 69 of 123 September 24, 2013 0X5E – CH3 MISCELLANEOUS CONTROL II ON BGCTL=1 BIT FUNCTION R/W DESCRIPTION RESET 7 NKILL_3 R/W 1 = Enable noisy signal color killer function in NTSC mode. 0 = Disabled. 6 PKILL_3 R/W 1 = Enable automatic noisy color killer function in PAL mode. 0 = Disabled. 5 SKILL_3 R/W 1 = Enable automatic noisy color killer function in SECAM mode. 0 = Disabled.

4 CBAL_3 R/W 0 = Normal output

1 = special output mode. 3 FCS_3 R/W 1 = Force decoder output value determined by CCS. 0 = Disabled.

2 LCS_3 R/W 1 = Enable pre-determined output value indicated by CCS when video loss

is detected. 0 = Disabled.

1 CCS_3 R/W When FCS is set high or video loss condition is detected when LCS is set

high, one of two colors display can be selected. 1 = Blue color. 0 = Black. 0 BST_3 R/W 1 = Enable blue stretch. 0 = Disabled.

FN8583 Rev.0.00 Page 70 of 123 September 24, 2013 0X5F – CH4 MISCELLANEOUS CONTROL II ON BGCTL=1 BIT FUNCTION R/W DESCRIPTION RESET 7 NKILL_4 R/W 1 = Enable noisy signal color killer function in NTSC mode. 0 = Disabled. 6 PKILL_4 R/W 1 = Enable automatic noisy color killer function in PAL mode. 0 = Disabled. 5 SKILL_4 R/W 1 = Enable automatic noisy color killer function in SECAM mode. 0 = Disabled.

4 CBAL_4 R/W 0 = Normal output

1 = special output mode. 3 FCS_4 R/W 1 = Force decoder output value determined by CCS. 0 = Disabled.

2 LCS_4 R/W 1 = Enable pre-determined output value indicated by CCS when video loss

is detected. 0 = Disabled.

1 CCS_4 R/W When FCS is set high or video loss condition is detected when LCS is set

high, one of two colors display can be selected. 1 = Blue color. 0 = Black. 0 BST_4 R/W 1 = Enable blue stretch. 0 = Disabled.

FN8583 Rev.0.00 Page 71 of 123 September 24, 2013 0X60 – CLOK PLL CONTROL 1 BIT FUNCTION R/W DESCRIPTION RESET 7 CLK_DIFF R/W 1 : XTI pin to PLL REF clock input is differential input. 0 : XTI pin to PLL REF clock input is non-differential input. 6-4 CP_SEL R/W Charge-pump current for PLL 0h : 1uA, 1h : 5uA, 2h : 10uA, 3h : 20uA, 4h : 40uA, 5h : 60UA, 6h : 80uA, 7h : 100uA. 3-2 LP_X8 R/W Loop resistor for PLL 0h : 55.7K, 1h : 17.6K, 2h ; 8.81K, 3h : 6.23K 1-0 VCO R/W Select VCO gain for PLL 0h : 416MHz/V, 1h : 517MHz/V, 2h : 615MHz/V, 3h : 755MHz/V

FN8583 Rev.0.00 Page 72 of 123 September 24, 2013 0X61 – VIDEO CLOCK SELECT BIT FUNCTION R/W DESCRIPTION RESET 7 PLLRST R/W PLL module Reset#.Test purpose only. 1 : PLL module Reset#, 0 : PLL module is in normal mode. 6 PLL_PD R/W 1 : PLL module is in power down mode. 0 : PLL module is in normal mode.

5 PLL_IREF R/W PLL Current bias reference 0

4 DECOSC R/W Video Decoder system clock select. 0: (PLL output clock)/4 is selected for video decoder process. 1: Video decoder system clock is generated by XTI input crystal clock. 3 SEL_144_72 R/W 1 : PLL moulde output 144MHz clock for D1 video decoder. 0 : PLL moulde output 72MHz clock.Test purpose only. 2 SEL_108_54 R/W 1 : PLL moulde output 108MHz clock for D1 video decoder. 0 : PLL moulde output 54MHz clock.Test purpose only. 1-0 XTIMD R/W XTI pin input clock process control. If XTIMD=0/1/2, Clock PLL Output clock is not used for internal logic process. 0: XTI clock is directly used for all video decoder clock source. 1: XTI/2 clock is used for all video decoder clock source. 2: XTI/4 clock is used for all video decoder clock source. 3: PLL output clock is used for all video decoder clock source when DECOSC=0.

FN8583 Rev.0.00 Page 73 of 123 September 24, 2013 0X62 – O36M BIT FUNCTION R/W DESCRIPTION RESET 7 O36M4 R/W 0 : CH4 video decoder output 27MHz video data. 1 : CH4 video decoder output 36MHz video data. 6 O36M3 R/W 0 : CH3 video decoder output 27MHz video data. 1 : CH3 video decoder output 36MHz video data. 5 O36M2 R/W 0 : CH2 video decoder output 27MHz video data. 1 : CH2 video decoder output 36MHz video data. 4 O36M1 R/W 0 : CH1 video decoder output 27MHz video data. 1 : CH1 video decoder output 36MHz video data. 3-0 Reserved R/W 0h 0X63 – CHANNEL ID 12 BIT FUNCTION R/W DESCRIPTION RESET 7-4 CH2NUM R/W Set up Channel ID number in VIN2 video decoder data output. 1h 3-0 CH1NUM R/W Set up Channel ID number in VIN2 video decoder data output. 0h 0X64 – CHANNEL ID 34 BIT FUNCTION R/W DESCRIPTION RESET 7-4 CH4NUM R/W Set up Channel ID number in VIN4 video decoder data output. 3h 3-0 CH3NUM R/W Set up Channel ID number in VIN3 video decoder data output. 2h

FN8583 Rev.0.00 Page 74 of 123 September 24, 2013 0X65 – VIDEO BUS TRI-STATE CONTROL BIT FUNCTION R/W DESCRIPTION RESET 7-5 Reserved R 0h 4 VD4ORD R/W Select the video channel output order on 4xD1 output mode. 0:Ch1->Ch2->Ch3->Ch4->Ch1->Ch2->Ch3->….(increase). 1:Ch4->Ch3->Ch2->Ch1->Ch4->Ch3->Ch2->….(decrease)

3 Reserved R/W 0

2 VDOEB R/W VD[7:0] output tri-state control. 1: tri-state output VD[7:0]. 0: normal output VD[7:0]. 1-0 Reserved R/W 0 0X67 – HZST BIT FUNCTION R/W DESCRIPTION RESET 7-0 HZST R/W HZOOM UP process start control.After this number’s pixels passed out data process from internal hsync(pksync),Hzoom Up module starts it’s zooming up process. 80h 0X6D – D1 NMGAIN/SHCOR BIT FUNCTION R/W DESCRIPTION RESET 7-0 NMGAIN 720 R/W These bits control the normal AGC loop maximum correction value in 720H D1 video decoder. 3-0 SHCOR 720 R/W These bits provide coring function for the sharpness control in 720H WD1 video decoder.

FN8583 Rev.0.00 Page 75 of 123 September 24, 2013 0X6E – D1 CLAMP POSITION REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-0 PCLAMP 720 R/W These bits set the clamping position from the PLL sync edge in 720H D1 video decoder. 38h 0X70 – AUDIO CLOCK CONTROL BIT FUNCTION R/W DESCRIPTION RESET 7 ACK36MD R/W 1 : 36MHz clock source is used for audio system clock. Special Test purpose only. 0 : 27MHz clock source is usded for audio system clock. 6 S2I_8BIT R/W 0 : ACLKP/ASYNP/ADATP pin input is 16-bit control. 1 : ACLKP/ASYNP/ADATP pin input is 8-bit control. 5 ACLKRPOL R/W ACLKR input signal polarity inverse. 0 : not inversed. 1 : inverses. 4 ACLKPPOL R/W ACLKP input signal polarity inverse. 0 : not inversed. 1 : inversed. 3 AFAUTO R/W ACKI[21:0] control automatic set up with AFMD registers. This mode is only effective when ACLKRMASTER=1. 0 : ACKI[21:0] registers set up ACKI control. 1 : ACKI control is automatically set up by AFMD register values. 2-0 AFMD R/W AFAUTO control mode. 0 : 8kHz setting (default). 1 : 16kHz setting. 2 : 32kHz setting. 3 : 44.1kHz setting. 4 : 48kHz setting.

FN8583 Rev.0.00 Page 76 of 123 September 24, 2013 0X71 – DIGITAL AUDIO INPUT CONTROL BIT FUNCTION R/W DESCRIPTION RESET 7 I2S8MODE R/W 8-bit I2S Record output mode. 0 : L/R half length separated output. 1 : One continuous packed output equal to DSP output format. 6 MASCKMD R/W Audio Clock Master ACLKR output wave format. 0 : High period is one 27 MHz clock period.This bit must be 0 when audio cascade is used with more than 32kHz Fs mode. 1 : Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two times bigger number value need to be set up ACKI registers. If AFAUTO=1, ACKI control is automatically set up even if MASCKMD=1. SDIV=00h is used with this function normally. 5 PBINSWAP R/W Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping. 0 : Not swapping. 1 : Swapping. 4 ASYNRDLY R/W ASYNR input signal delay. 0 : No delay. 1 : Add one 27MHz period delay in ASYNR signal input. 3 ASYNPDLY R/W ASYNP input signal delay. 0 : No delay. 1 : Add one 36MHz period delay in ASYNP signal input. 2 ADATPDLY R/W ADATP input data delay by one ACLKP clock. 0 : No delay. This is for I2S type 1T delay input interface. 1 : Add 1 ACLKP clock delay in ADATP input data. This is for left-justified type 0T delay input interface. 1-0 INLAWMD R/W Select u-Law/A-Law/PCM/SB data input format on ADATP pin. 0 : PCM input 1 : SB(Signed MSB bit in PCM data is inverted) input 2 : u-Law input 3 : A-Law input

FN8583 Rev.0.00 Page 77 of 123 September 24, 2013 0X72 – MIX RATIO VALUE 1 BIT FUNCTION R/W DESCRIPTION RESET

7 MRATIOMD R/W Audio Mixing ratio value divider control

0 : MIX_RATIOn 0 0.25 (default) 1 0.31 2 0.38 3 0.44 4 0.50 5 0.63 6 0.75 7 0.88 8 1.00 9 1.25 10 1.50 11 1.75 12 2.00 13 2.25 14 2.50 15 2.75 1 : MIX_RATIO / 64 6 ADACTEST R/W 0 : must be set up 0 in normal mode. 1 : test purpose only

5 AOFFCORE R/W 0: Audio No-input Noise reduction on(Test purpose only)

1: Audio No-input Noise reduction off

FN8583 Rev.0.00 Page 78 of 123 September 24, 2013 0X72 – MIX RATIO VALUE 2 BIT FUNCTION R/W DESCRIPTION RESET 4 DAORATIO R/W Digital Audio Output Gain is controlled by following. 0: DAOGAIN 0 0.25 1 0.31 2 0.38 3 0.44 4 0.50 5 0.63 6 0.75 7 0.88 8 1.00(default) 9 1.25 10 1.50 11 1.75 12 2.00 13 2.25 14 2.50 15 2.75 1: DAOGAIN / 64 3-0 DAOGAIN R/W Digital Audio Output Gain. Gain is controlled with DAORATIO mode.

FN8583 Rev.0.00 Page 79 of 123 September 24, 2013 0X73 – A51DET_ENA BIT FUNCTION R/W DESCRIPTION RESET 7-3 Reserved R Reserved 00h 2 AIN51FORM R/W AIN51/52/53/54 record output format selection. This bit is only effective when A51OUTOFF register is set to 0. When AIN1/2/3/4/51 and AIN6/7/8/9/52 are required to be continuous order in record output, 1 is necessary. 0: If I2S mode(RM_SYNC=0) If DSP mode(RM_SYNC=1) all data are continuous. 1: If I2S mode(RM_SYNC=0) If DSP mode(RM_SYNC=1) all data continuous.

1 AINTPOFF R/W 0 : must be set up 1 : test purpose only 0

0 A51DET_ENA R/W Enable state register updating and interrupt request of audio

AIN51 (AIN5 input in this chip) detection for each input. 0 : Disable state register updating and interrupt request 1 : Enable state register updating and interrupt request 0X74 – STATUS OF AUDIO 5 DETECTION BIT FUNCTION R/W DESCRIPTION RESET 7-1 Reserved R 00h 0 A5DET_STATE R State of Audio AIN51( AIN5 input in this chip) detection. This bit is activated according ADET_MODE. 0 : Inactivated 1 : Activated

FN8583 Rev.0.00 Page 80 of 123 September 24, 2013 0X7B – ADATM I2S OUTPUT SELECT BIT FUNCTION R/W DESCRIPTION RESET 7-5 Reserved R 0h 4-0 I2SO_RSEL R/W Select R-channel output data on ADATM pin when ADATM_I2SOEN=1. * 15h *Note : Both I2SO_RSEL and I2SO_LSEL select output data by following order.

0 Select record audio of channel 1(AIN1)

1 Select record audio of channel 2(AIN2)

2 Select record audio of channel 3(AIN3)

3 Select record audio of channel 4(AIN4)

4 Select record audio of channel 5(AIN5)

5 Select record audio of channel 6(AIN6)

6 Select record audio of channel 7(AIN7)

7 Select record audio of channel 8(AIN8)

8 Select record audio of channel 9(AIN9)

9 Select record audio of channel 10(AIN10)

10(Ah) Select record audio of channel 11(AIN11) 11(Bh) Select record audio of channel 12(AIN12) 12(Ch) Select record audio of channel 13(AIN13) 13(Dh) Select record audio of channel 14(AIN14) 14(Eh) Select record audio of channel 15(AIN15) 15(Fh) Select record audio of channel 16(AIN16) 16(10h) Select playback audio of the first stage chip(PB1) 17(11h) Select playback audio of the second stage chip(PB2) 18(12h) Select playback audio of the third stage chip(PB3) 19(13h) Select playback audio of the last stage chip(PB4) 20(14h) Select mixed audio. 21(15h) Select record audio of channel 51(AIN51)(default) 22(16h) Select record audio of channel 52(AIN52) 23(17h) Select record audio of channel 53(AIN53) 24(18h) Select record audio of channel 54(AIN54) Others no audio output. 0X7C – ADATM I2S OUTPUT SELECT BIT FUNCTION R/W DESCRIPTION RESET 7-5 Reserved R 0h 4-0 I2SO_LSEL R/W Select L-channel output data on ADATM pin when ADATM_I2SOEN=1. * 15h * Note : Please read 0x7B Note for detail description.

FN8583 Rev.0.00 Page 81 of 123 September 24, 2013 0X7D – AIN51/52/53/54 RECORD OUTPUT BIT FUNCTION R/W DESCRIPTION RESET 7-6 I2SRECSEL54 R/W Select output data in bellow dat54 position. 0: AIN51, 1:AIN52, 2:AIN53, 3:AIN54. 5-4 I2SRECSEL53 R/W Select output data in bellow dat53 position. 0: AIN51, 1:AIN52, 2:AIN53, 3:AIN54. 3-2 I2SRECSEL52 R/W Select output data in bellow dat52 position. 0: AIN51, 1:AIN52, 2:AIN53, 3:AIN54. 1-0 I2SRECSEL51 R/W Select output data in bellow dat51 position. 0: AIN51, 1:AIN52, 2:AIN53, 3:AIN54. These registers are only effective when A51OUTOFF=0.These registers function change under AIN51FORM control at that time as follows. When AIN51FORM=0: If I2S mode(RM_SYNC=0), If DSP mode(RM_SYNC=1), all data are continuous. When AIN51FORM=1: If I2S mode(RM_SYNC=0), If DSP mode(RM_SYNC=1),all data are continuous. All other datN(N=0,1,2,,,,F) are selected by R_SEQ_N registers

FN8583 Rev.0.00 Page 82 of 123 September 24, 2013 0X7E – A5OUTOFF BIT FUNCTION R/W DESCRIPTION RESET 7 A5OUTOFF R/W AIN5 data output control on ADATR record signal. 0: output AIN51/AIN52/AIN53/AIN54 record data on ADATR. 1: not output AIN51/AIN52/AIN53/AIN54 record data on ADATR.

6 ADATM_I2SOEN R/W Define ADATM pin output 2 word data to make standard I2S

output. 0:Mixing Data or Playback Input data are only output on ADATM pin by M_RLSWAP register.(default) 1:L/R data on ADATM pin is selected by I2SO_RSEL / I2SO_LSEL registers. 5 MIX_MUTE_A5 R/W MIX_MUTE_A5: Audio input AIN5 mute function control. 0:Normal 1:Muted 4-0 ADET_TH5[4:0] R/W AIN5 threshold value for audio detection 03h

FN8583 Rev.0.00 Page 83 of 123 September 24, 2013 0X80 – SOFTWARE RESET CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-6 Reserved R Reserved 00b