TW2984 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

 WD1 (960H) and D1 compatible video decoding operation and it is programmable each channel  NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60) support with automatic format detection  Built-in analog anti-alias filter  Four 10-bit ADCs and analog clamping circuit for CVBS input  Fully programmable static gain or automatic gain control for the Y channel  Programmable white peak control for CVBS channel  4-H adaptive comb filter Y/C separation  PAL delay line for color phase error correction  Image enhancement with peaking and CTI  Digital sub-carrier PLL for accurate color decoding  Digital Horizontal PLL for synchronization processing and pixel sampling  Advanced synchronization processing and sync detection for handling non-standard and weak signal  Programmable hue, brightness, saturation, contrast, sharpness  Automatic color control and color killer  ITU-R 656 like YCbCr (4:2:2) output or time multiplexed output with 36/72/144MHz for WD1 or 27/54/108MHz for D1 format Audio Codec  Integrated five audio ADCs processing and one audio DAC  Provides multi-channel audio mixed analog output  Support I2S/DSP Master/Slave interface for record output and playback input  PCM 8/16-bit and u-Law/A-Law 8-bit for audio word length  Programmable audio sample rate that covers popular frequencies of 8/16/32/44.1/48kHz Miscellaneous  Two-wire MPU serial bus interface  Integrated clock PLL for 144/108MHz clock output  Power save and Power down mode  Low power consumption  Single 27MHz crystal for all standards and both WD1 and D1 format  3.3V tolerant I/O  1.0V/3.3V power supply  8mm x 8mm 68-pin QFN package

specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. otherwise under any patent or patent rights of Intersil or its subsidiaries. FIGURE 1. TW2984 BLOCK DIAGRAM