TVP9900

TVP9900 TI | Alldatasheet

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Number: SLEA064 March 2007 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 6.2.19 Timing Recovery Status Register 6.2.20 Timing Recovery Status Register 6.2.21 Timing Recovery Status Register 6.2.22 Timing Recovery Status Register 6.2.23 Timing Recovery Status Register 6.2.24 Timing Recovery Status Register 6.2.25 Pilot Tracking Status Register 6.2.26 Pilot Tracking Status Register 6.2.27 Pilot Tracking Status Register 6.2.28 Carrier Recovery Status Register 6.2.29 Carrier Recovery Status Register 6.2.30 Carrier Recovery Status Register 6.2.31 Carrier Recovery Status Register 6.2.32 Carrier Recovery Status Register 6.2.33 Carrier Recovery Status Register 6.2.34 FEC Status Register 6.2.35 FEC Status Register 6.2.36 FEC Status Register 6.2.37 FEC Status Register 6.2.38 GPIO Alternate Function Select Register 6.2.39 GPIO Output Data Register 6.2.40 GPIO Output Enable Register 6.2.41 GPIO Input Data Register 6.2.42 MPEG Interface Output Enable Register 6.2.43 MPEG Interface Output Enable Register 6.2.44 Tuner Control Interface I C Slave Device Address Register 6.2.45 Tuner Control Interface Data Register Through 6.2.46 Tuner Control Interface Control and Status Register 6.2.47 Antenna Control Interface Control and Status Register 6.2.48 Antenna Control Interface Transmit Data Register 6.2.49 Antenna Control Interface Transmit Data Register 6.2.50 Antenna Control Interface Receive Data Register 6.2.51 Antenna Control Interface Receive Data Register 6.2.52 Firmware ID ROM Version Register 6.2.53 Firmware ID RAM Major Version Register 6.2.54 Firmware ID RAM Minor Version Register 6.2.55 Device ID LSB Register 6.2.56 Device ID MSB Register 6.2.57 Miscellaneous Control Register 6.2.58 Software Interrupt Raw Status Register 6.2.59 Software Interrupt Status Register 6.2.60 Software Interrupt Mask Register 6.2.61 Software Interrupt Clear Register Electrical Specifications 7.1 Absolute Maximum Ratings 7.2 Recommended Operating Conditions 7.3 DC Electrical Characteristics 7.4 Analog Input Characteristics 7.5 Timing Characteristics 7.5.1 Crystal and Input Clock 7.5.2 Device Reset 7.5.3 MPEG Interface 7.5.3.1 Parallel Mode (Data Only)

Contents

www.ti.com TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 7.5.3.2 Serial Mode (Data Only) 7.5.3.3 Parallel Mode (Data With Redundancy) 7.5.3.4 Serial Mode (Data With Redundancy) 7.5.4 Host and Tuner I C Interface Application Circuit

www.ti.com TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 List of Figures 2-1 TVP9900 Block Diagram 4-1 Parallel Transport Stream Timing Diagram (Data Only) 4-2 Serial Transport Stream Timing Diagram (Data Only) 4-3 Parallel Transport Stream Timing Diagram (Data Redundancy) 4-4 Serial Transport Stream Timing Diagram (Data Redundancy) 4-5 Tuner Control Interface System 4-6 Antenna Control Interface System 4-7 25-MHz Crystal Oscillation 4-8 4-MHz Clock Input 5-1 Thermal Land Size and Via Array 7-1 Crystal or Clock Timing Waveform 7-2 Device Reset Signal Timing Waveforms 7-3 MPEG Interface Parallel Mode (Data Only) Timing Waveforms 7-4 MPEG Interface Serial Mode (Data Only) Timing Waveforms 7-5 MPEG Interface Parallel Mode (Data With Redundancy) Timing Waveforms 7-6 MPEG Interface Serial Mode (Data with Redundancy) Timing Waveforms 7-7 I C SCL and SDA Timing Waveforms 7-8 I C Start and Stop Conditions Timing Waveforms List of Figures

www.ti.com TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 List of Tables 3-1 Terminal Functions 4-1 MPEG-2 Transport Stream Interface 4-2 MPEG-2 Transport Stream Output Clock Frequency 4-3 I C Terminal

Description

I C Host Interface Device Write Addresses 4-5 I C Host Interface Device Read Address 4-6 Tuner Control Interface Registers 4-7 Antenna Control Interface Registers 4-8 Antenna Control Interface Pins 6-1 I C Host Interface Registers 7-1 Crystal and Input Clock Timing 7-2 Device Reset Timing 7-3 Parallel Mode (Data Only) Timing 7-4 Serial Mode (Data Only) Timing 7-5 Parallel Mode (Data With Redundancy) Timing 7-6 Serial Mode (Data With Redundancy) Timing 7-7 Host and Tuner I C Interface Timing List of Tables Submit Documentation Feedback

www.ti.com Introduction 1.1

Features

1.2 Ordering Information (1) TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The TVP9900 is a cost-effective digital TV (DTV) front-end IC targeted for low-cost high-volume DTV receivers. The TVP9900 is a system-on-chip (SoC) device that integrates the main functions of a DTV front-end system, including programmable gain amplifier (PGA), A/D converter, VSB demodulator, ATSC forward error correction (FEC), QAM demodulator, and ITU-T Annex B FEC. It provides rich peripheral support including AGC control, tuner control, CEA-909 antenna control, and host I C interface. The TVP9900 supports processing of ATSC VSB or ITU-T Annex B QAM IF inputs. Host Interrupt for Remote Monitoring of Signal ATSC 8-VSB Demodulation and FEC Quality ITU-J.83B Compliant QAM SNR Monitor Demodulation and FEC BER Monitor Direct 44-MHz IF Sampling Eliminates Need for External Downconverter Integrated De-Interleaver RAM Integrated IF PGA Parallel/Serial MPEG Output Interface With Error Packet Indicator Integrated High-Speed 10-bit A/D Converter Direct Tuner Control Interface Integrated Digital Filter Relaxes External Tuner Filters EIA/CEA-909 Antenna Control Interface Sigma-Delta DAC for AGC Control Option for 4-MHz Clock Input Driven by MOP IC in Tuner, So No Quartz Crystal Required for Adjacent Channel Filter Demodulator NTSC Co-Channel Rejection Filter External DAC and VCXO for Clock Recovery All Digital Timing Recovery Not Required Pilot Tracking Loop With Lock Status Indicator Equalizer Covers Echo Profile Required by Signal ATSC A.74 Guideline Decision-Directed Carrier Phase Tracking Superior Multipath Performance Demodulating Loop for Brazil Ensembles A Through E Field and Segment Synchronization With Sync Power-Down Mode Status Indicator Signal 80-Pin TQFP Package PACKAGED DEVICES T A PACKAGE OPTION 80-Pin TQFP-PowerPAD TVP9900PFP Tray C to C TVP9900PFPR Tape and Reel (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

document. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Block Diagram VSB/QAM Demodulator ITU-T J.83 Annex B FEC ATSC FEC I2CSDA I2CSCL TUNSDA TUNSCL AIFIN_P AIFIN_N Tuner Interface AGCOUT GPIO [7:0] Output Formatter CEA-909 Interface GPIO Interface ANTCNTLIO VBUS ROM RAM MCU Host Interface Interrupt Ctrl JTAG DCLK BYTE_START PACCLK DATAOUT[7:0] DERROR PLL INTREQ PWRDOWN AFE VSB/QAM Demodulator ITU-T J.83 Annex B FEC ATSC FEC AIFIN_P AIFIN_N Tuner Interface AGCOUT GPIO [7:0] XTALIN XTALOUT CLKIN CLKSEL CLKOUT Output Formatter CEA-909 Interface GPIO Interface VBUS ROM RAM Host Interface Interrupt Ctrl JTAG DCLK BYTE_START PACCLK DATAOUT[7:0] DERROR PLL TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Figure 2-1. TVP9900 Block Diagram Block Diagram Submit Documentation Feedback

www.ti.com Terminal Assignments 3.1 Pinout TVP9900 80-Pin TQFP (Top View) 1AGND 2AVDD_3_3 3AIFIN_P 4AIFIN_N 5AVDD_3_3 6AGND 7AVDD_1_5 8AGND 9AGND_PLL 10AVDD_PLL_1_5 11XTALOUT 12XTALREF 13XTALIN 14CLKIN 15DIVINSEL 16CLKOUT 17DGND 18DVDD_1_5 19IOGND 20IOVDD_3_3 RESETZ TMSEL0 TMSEL1 DGND DVDD_1_5 TMSEL2 TMSEL3 AGCOUT ANTCNTLIO TUNSDA TUNSCL IOGND IOVDD_3_3 I2CSDA I2CSCL DGND DVDD_1_5 I2CA0 PWRD WN DERROR DATAOUT0 DATAOUT1 DVDD_1_5 DGND DATAOUT2 DATAOUT3 DATAOUT4 IOVDD_3_3 IOGND DATAOUT5 DATAOUT6 DATAOUT7/SERDATA0 DVDD_1_5 DGND PACCLK BYTESTART IOVDD_3_3 IOGND DCLK DGND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NSUB BGREFCAP BIASRES AVDD_REF_3_3 AGND_REFAGNDDGND DVDD_1_5 GPIO0/ANTCNTLIN GPIO1 GPIO2 DGND DVDD_1_5 GPIO3 GPIO4 GPIO5/SYNCOUT IO VDD_3_3 IOGND GPIO6 GPIO7/INTREQ TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Submit Documentation Feedback Terminal Assignments

www.ti.com 3.2 Terminal Functions TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Table 3-1. Terminal Functions TERMINAL I/O NO. IF INTERFACE AIFIN_P I Analog positive differential IF input AIFIN_N I Analog negative differential IF input TRANSPORT STREAM INTERFACE DCLK O MPEG-2 data clock output MPEG-2 Byte Start signal. An active high output signal that indicates the first byte of a BYTE_START O transport stream data packet. MPEG-2 interface packet framing signal. An active high output signal that remains high PACCLK O for the entire length of the valid data packet. MPEG-2 interface data error. An active high output signal that indicates an error in the DERROR O data output packet. Indicates an error in the input data. This pin should be tied low if not in use. MPEG-2 parallel data output. Bit is the first bit of the transport stream. DATAOUT7/SERDATA0 O MPEG-2 serial data output 50, 51, 54, 55, DATAOUT[6:0] O MPEG-2 parallel data output bits 6-0. 56, 59, CLOCK SIGNALS Crystal input. Input to the on-chip oscillator from an external crystal. The required crystal frequency is MHz. This input can also be driven by an external clock source instead of XTALIN I a crystal. When using an external clock source, a MHz or MHz clock must be used. NOTE: If an external clock source is used, the input can only be used with 1.5-V signal levels. XTALOUT O Crystal output. Output from the on-chip oscillator to an external crystal. External crystal reference. This pin is used for the external crystal capacitor ground XTALREF I reference. CLKIN I Test clock input. For normal operation, this input should be tied low. PLL VCO divider default input select. This input is used to select the default VCO divider value for the PLL. If a 25-MHz crystal or clock is used for XTALIN, then DIVINSEL should DIVINSEL I be driven low. If a 4-MHz crystal or clock is used for XTALIN, then DIVINSEL should be driven high. CLKOUT O Test clock output. For normal operation, this output is not used. MISCELLANEOUS SIGNALS AGCOUT O AGC control Delta-Sigma DAC output. ANTCNTLIO I/O Smart antenna control interface input/output. TUNSDA I/O Tuner I C serial data input/output. NOTE: The output functions as an open-drain. TUNSCL I/O Tuner I C serial clock. NOTE: The output functions as an open-drain. General purpose I/O GPIO7/INTREQ I/O Interrupt request output General purpose I/O GPIO6 I/O Reserved General purpose I/O GPIO5/SYNCOUT I/O Sync output 66, 67, GPIO[4:2] I/O General purpose I/O Dedicated to Smart Antenna support. Outputs direction of signal on pin in Smart Antenna 1-pin mode. GPIO1 O Signal input from antenna to TVP9900, pin Signal output from TVP9900 pin to antenna Terminal Assignments Submit Documentation Feedback

www.ti.com TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Table 3-1. Terminal Functions (continued) TERMINAL I/O NO. General purpose I/O GPIO0/ANTCNTLIN I/O Antenna Control Input System reset. An active-low asynchronous input that initializes the device to the default RESETZ I state. PWRDOWN I Power down terminal. An active high signal puts the device in a low power state. 22, 23, TMSEL[3:0] I Test mode select. Tie low for normal operation. 26, HOST INTERFACE I2CSDA I/O Host I C serial data input/output. NOTE: The pin functions as an open-drain output. I CSCL I/O Host I C serial clock. NOTE: The pin functions as an open-drain output. Host I C device address select. Determines address for I C (sampled during reset). A pullup or pulldown 10-k Ω resistor is needed to program the terminal to the desired I CA0 I address. Address is 0xB8h Address is 0xBAh POWER SUPPLIES 18, 25, 37, 48, DVDD_1_5 P Digital power supply. Connect to 1.5-V digital supply. 58, 68, 17, 24, 36, 41, DGND P Digital power supply return. Connect to digital ground. 47, 57, 69, 20, 33, IOVDD_3_3 44, 53, P IO power supply. Connect to 3.3-V digital supply. 19, 32, IOGND 43, 52, P IO power supply return. Connect to digital ground. AVDD_3_3 P Analog power supply. Connect to 3.3-V analog supply. AVDD_1_5 P Analog power supply. Connect to 1.5-V analog supply. AGND P Analog power supply return. Connect to analog ground. AVDD_PLL_1_5 P PLL power supply. Connect to 1.5-V analog supply. AGND_PLL P PLL power supply return. Connect to analog ground. NSUB P Die substrate. Connect to PCB ground. AVDD_REF_3_3 P Analog reference power supply. Connect to 3.3-V analog supply. AGND_REF P Analog reference ground. Connect to analog ground. BGREFCAP O Band-gap reference capacitor connection BIASRES O Analog bias register. Connect through a 24-k Ω resistor to PCB ground. Submit Documentation Feedback Terminal Assignments

www.ti.com Functional 4.1 Analog Front End 4.2 VSB/QAM Demodulator 4.3 Forward Error Correction TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The TVP9900 receiver has an analog input channel that accepts one differential or single-ended 44-MHz center frequency IF input, which are ac-coupled. The receiver supports a maximum input differential voltage range of Vpp with PGA setting at unity gain. The programmable gain amplifier (PGA) and the AGC circuit work together and ensure that the input signal is amplified sufficiently to ensure the proper input range for the ADC. The ADC has bits of resolution. The clock input for the ADC comes from the PLL. An external downconverter is not required to use this IF direct sampling method. The analog front end and adjacent digital filter can potentially relax the requirement for external analog filters, and only one external SAW filter is required. The VSB/QAM demodulator is designed for 8-VSB demodulation compliant with ATSC, and QAM demodulation compliant with ITU-T J83 Annex The VSB/QAM demodulator in the TVP9900 is composed of the following blocks: Automatic gain control Adjacent channel filter NTSC rejection filter Timing recovery Pilot tracking Matched filter Decision feedback equalizer Carrier recovery The all-digital demodulator architecture does not require an external downconverter, AGC control DAC, clock recovery VCXO, or carrier recovery VCXO. This architecture makes a low-cost system implementation possible. Forward Error Correction (FEC) in the TVP9000 includes the following blocks: QAM FEC Trellis decoder Synchronizer De-randomizer De-interleaver Reed Solomon decoder MPEG deframer VSB FEC Trellis decoder Synchronizer De-interleaver Reed Solomon decoder De-randomizer The Trellis decoder is designed for help protect against short-burst interference. The VSB synchronizer performs segment and frame synchronization and outputs the synchronization signal with data. An internal RAM is shared by both VSB and QAM modes, and additional external RAM is not required. Functional

www.ti.com 4.4 Output Formatter DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes Data 188 bytes 7 6 5 4 3 2 1 0 7 6 1 0 1st byte 7 6 5 4 3 2 1 0 7 6 DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes 7 6 5 4 3 2 1 0 7 6 1 0 1st byte 7 6 5 4 3 2 1 0 7 6 DCLK DATAOUT[7:0] BYTE_START PACCLK TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The TVP9900 transport stream interfaces directly to the back-end IC, which provides transport stream compliance with ISO/IEC 13818-1 in parallel or serial modes. The details of the transport stream interface are shown in Table 4-1 In serial mode, DATAOUT[7] is used as the serial data output, with the MSB output first. The maximum output rate is 42.1 Mbit/s in serial mode. The polarity of DCLK, BYTE_START, DERROR, and PACCLK is programmable. Table 4-1. MPEG-2 Transport Stream Interface TERMINAL TYPE O Parallel/serial clock output Parallel/serial data output DATAOUT[7:0] O DATAOUT7 is the first bit of the transport stream in parallel mode. DATAOUT7 is the serial data output in serial mode. BYTE_START O Packet sync, indicates the start byte of a transport packet PACCLK O Packet enable, indicates the valid packet data Figure 4-1 and Figure 4-2 show the parallel and serial transport stream timing diagrams in data-only mode. In data-only mode, 188 bytes of data is transferred from the transport stream interface continuously. PACCLK is always kept high. Figure 4-1. Parallel Transport Stream Timing Diagram (Data Only) Figure 4-2. Serial Transport Stream Timing Diagram (Data Only) Figure 4-3 and Figure 4-4 show the parallel and serial transport stream timing diagrams in data and redundancy mode. In data and redundancy mode, 188 bytes of data is transferred from the transport stream interface with redundant data bytes. PACCLK only becomes high when the data is valid. Redundancy data is bytes in the ATSC standard and bytes in ITU-T J.83 Annex Submit Documentation Feedback Functional

www.ti.com Parity 16 or 20 bytesData 188 bytes DCLK DATAOUT[7:0] BYTE_START PACCLK Parity 16 or 20 bytesData 188 bytes DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes Parity 16 or 20 bytes 7 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 5 1st byte DCLK DATAOUT[7:0] BYTE_START PACCLK Data 188 bytes Parity 16 or 20 bytes 7 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 5 1st byte DCLK DATAOUT[7:0] BYTE_START PACCLK 4.5 I C Host Interface TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Figure 4-3. Parallel Transport Stream Timing Diagram (Data Redundancy) Figure 4-4. Serial Transport Stream Timing Diagram (Data Redundancy) Table 4-2 shows the transport stream clock frequency in each mode. Table 4-2. MPEG-2 Transport Stream Output Clock Frequency DATA ONLY DATA REDUNDANCY BIT RATE MODE SERIAL CLOCK PARALLEL CLOCK SERIAL CLOCK PARALLEL CLOCK (Mbps) (MHz) (MHz) (MHz) (MHz) 8VSB 19.39266 19.39266 2.42408 21.45571 2.68196 64QAM 26.97035 26.97035 3.37129 29.26570 3.65821 256QAM 38.81070 38.81070 4.85133 42.11374 5.26422 Communication with the TVP9900 receiver is via an I C host interface. The I C standard consists of two signals, the serial input/output data (I2CSDA) line and the input/output clock line (I2CSCL), which carry information between the devices connected to the bus. A 1-bit control signal (I2CA0) is used for slave address selection. Although an I C system can be multi-mastered, the TVP9900 can function as a slave device only. Since I2CSDA and I2CSCL are kept open-drain at logic high output level or when the bus is not driven, the user should connect I2CSDA and I2CSCL to IOVDD_3.3 via a pullup resistor on the board. At the trailing edge of reset, the status of the I2CA0 line is sampled to determine the device address used. Table 4-3 summarizes the terminal functions of the I C-mode host interface. Table 4-4 and Table 4-5 show the device address selection options. Functional

www.ti.com 4.5.1 I C Write Operation TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Table 4-3. I C Terminal I Slave address selection I2CSCL I/O (open drain) Input/output clock line I2CSDA I/O (open drain) Input/output data line Table 4-4. I C Host Interface Device Write Addresses I2CA0 WRITE ADDRESS B8h BAh Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL, except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I C stop condition. Every byte placed on the SDA must be bits long. The number of bytes that can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I C master. Data transfers occur utilizing the following illustrated formats. An I C master initiates a write operation to the TVP9900 receiver by generating a start condition (S), followed by the TVP9900 I C address (as shown below), in MSB first bit order, followed by a to indicate a write cycle. After receiving an acknowledge from the TVP9900 receiver, the master presents the sub-address of the register or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP9900 receiver acknowledges each byte after completion of each transfer. The I C master terminates the write operation by generating a stop condition (P). Step S I C Start (master) Step X I C General address (master) Step A I C Acknowledge (slave) Step Addr Addr Addr Addr Addr Addr Addr Addr I C Write register address (master) Step A I C Acknowledge (slave) Step Data Data Data Data Data Data Data Data I C Write data (master) Step (1) A I C Acknowledge (slave) Step P I C Stop (master) (1) Repeat steps and until all data have been written. Submit Documentation Feedback Functional

www.ti.com 4.5.2 I C Read Operation TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The read operation consists of two phases. The first phase is the address phase. In this phase, an I C master initiates a write operation to the TVP9900 receiver by generating a start condition (S) followed by the TVP9900 I C address, in MSB first bit order, followed by a to indicate a write cycle. After receiving acknowledges from the TVP9900 receiver, the master presents the sub-address of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). Table 4-5. I C Host Interface Device Read Address I2CA0 READ ADDRESS B8h BAh The second phase is the data phase. In this phase, an I C master initiates a read operation to the TVP9900 receiver by generating a start condition, followed by the TVP9900 I C address (as shown below for a read operation), in MSB-first bit order, followed by a to indicate a read cycle. After an acknowledge from the TVP9900 receiver, the I C master receives one or more bytes of data from the TVP9900 receiver. The I C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP9900 receiver to the master, the master generates a not acknowledge, followed by a stop. Read Phase Step S I C Start (master) Step X I C General address (master) Step A I C Acknowledge (slave) Step Addr Addr Addr Addr Addr Addr Addr Addr I C Write register address (master) Step A I C Acknowledge (slave) Step P I C Stop (master) Read Phase Step S I C Start (master) Step X I C General address (master) Step A I C Acknowledge (slave) Step Data Data Data Data Data Data Data Data I C Read data (slave) Step (1) A I C Not Acknowledge (master) Step P I C Stop (master) (1) Repeat steps and for all bytes read. Master does not acknowledge the last read data received. Functional

www.ti.com 4.6 Tuner Control Interface Tuner Control Interface Host I2C Interface MCU From Host Processor SDA SCL TUNSDA TUNSCL T o Tuner Tuner Control Interface Host I2C Interface From Host Processor SDA SCL TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The TVP9900 has an I C-compatible two-wire serial interface that can be used by the host processor for tuner control. This dedicated tuner interface can be used by the host processor to transfer data to/from the tuner in order to isolate the tuner from the main system I C bus. As a result, noise coupling to the tuner from host processor I C bus transfers should be minimized. The TVP9900 tuner control interface operates as an I C bus master and supports both 100-kbps and 400-kbps data transfer rates. The mode and transfer rate is set in the Tuner Control Interface Control and Status Register (5Eh), bit The device does not support a multi-master bus environment (bus arbitration is not supported). To transfer data to/from the tuner, the host processor first writes the transaction to a set of registers in the TVP9900 via the host processor I C interface. Then the TVP9900 internal MCU transfers the data to/from the tuner via the tuner control interface. TUNSCL and TUNSDA need to be pulled up to the 3.3-V supply (IOVDD) and not to a 5-V supply. Figure 4-5 shows the block diagram of the tuner control interface system. Figure 4-5. Tuner Control Interface System Table 4-6 lists the I C registers and their functions used to control the tuner interface. Table 4-6. Tuner Control Interface Registers REGISTER FUNCTION 55h Tuner I C slave address and R/W control 56h to 5Dh Data registers through 5Eh Byte Count, Transaction Start, and I C Mode Software Interrupt Raw Status, Status, Mask, and Clear Transaction Error F9, FB, FD, FFh and Done Status When the TVP9900 tuner I C interface is used, rather than controlling the tuner over the host processor I C bus interface, two status bits are provided in the TVP9900 to indicate a transaction error or the completion of a successful transaction. The TCIERROR bit in the TVP9900 Software Interrupt Status Register (FBh) gets set as a result of a transaction error. The TCIDONE bit in the same register gets set at the end of a normal transaction; it does not get set for an abnormal transaction. The TVP9900 can be configured so that setting the TCIERROR or TCODONE status bits can assert the INTREQ output of the TVP9900; this requires the mask bits to be configured correctly in the TVP9900 Software Interrupt Mask Register (FDh). Submit Documentation Feedback Functional

www.ti.com 4.6.1 Tuner Write Operation 4.6.2 Tuner Read Operation TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 If the host INTREQ is not used, the TCIDONE and TCIERROR interrupts should be masked and the host should poll the TCIDONE status bit to determine when the transaction is complete, and the host should poll the TCIERROR status bit to determine when an error has occurred. Tuner data transfers occur utilizing the following illustrated formats. The following steps are required to initiate a write operation to the tuner. The host processor first writes the required transaction data to a set of registers in the TVP9900 via the host processor I C interface. Step Register 55h Set tuner I C slave address (bits 7:1) and read/write control (bit Step Registers 56h to 5Dh Write data bytes to be sent to tuner; 56h is first byte sent Step Set byte count (bits 7:5) and I C mode (bit Register 5Eh Set bit to to start transaction to tuner Step Register FBh Check state of bits 1:0 or INTREQ pin to verify successful transaction After the transaction has been initiated, the TVP9900 internal MCU transfers the data to the tuner via the tuner control interface. Acting as the I C master, the TVP9900 initiates a write operation to the tuner (as shown below), by generating a start condition, followed by the tuner I C address, in MSB-first bit order, followed by a to indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900 presents the sub-address of the register, if needed, followed by one or more bytes of data, MSB first. The tuner acknowledges each byte after completion of each transfer. The TVP9900 terminates the write operation by generating a stop condition. TVP9900/Tuner Write Operation Device Base SDA Start W Ack Ack Data Ack ... Data N Ack Stop Address Address The following steps are required to initiate a read operation from the tuner. The host processor first writes the required transaction data to a set of registers in the TVP9900 via the host processor I C interface, then reads the data bytes received from the tuner stored in TVP9900 registers. Step Register 55h Set tuner I C slave address (bits 7:1) and read/write control (bit Step Set byte count (bits 7:5) and I C mode (bit Register 5Eh Set bit to to start transaction to tuner Step Register FBh Check state of bits 1:0 or INTREQ pin to verify successful transaction Step Registers 56h to 5Dh Read data bytes from tuner; 56h is first byte received After the transaction has been initiated, the TVP9900 internal MCU transfers the data from the tuner via the tuner control interface. The read operation consists of two phases, as shown below. The first phase is the address phase. In this phase, the TVP9900 I C master initiates a write operation to the tuner by generating a start condition, followed by the tuner I C address, in MSB-first bit order, followed by a to indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900 presents the sub-address of the register, if needed. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition. Functional

www.ti.com 4.7 Antenna Control Interface TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The second phase is the data phase. In this phase, the TVP9900 I C master initiates a read operation to the tuner by generating a start condition, followed by the tuner I C address, in MSB-first bit order, followed by a to indicate a read cycle. After an acknowledge from the tuner, the TVP9900 receives one or more bytes of data from the tuner. The TVP9900 acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the tuner to the TVP9900, the TVP9900 generates a not acknowledge, followed by a stop. TVP9900/Tuner Set Start Address, Then Read Operation Device Base SDA Start W Ack Ack Stop Address Address Device SDA Start R Ack Data Ack ... Data N Ack Stop Address The TVP9900 has an antenna control interface compliant with EIA/CEA-909. The TVP9900 receives the antenna parameters from the host processor via I and sends a modulated PWM signal to the antenna. The antenna parameters include antenna direction, antenna polarization, preamplifier gain and channel number. This interface can be used to automatically optimize the signal by adjusting the antenna configuration for the best possible reception. Figure 4-6 shows the block diagram of the antenna control interface system. Figure 4-6. Antenna Control Interface System Table 4-7 lists the I C registers and their functions used with the antenna control interface. Table 4-7. Antenna Control Interface Registers REGISTER FUNCTION 4Fh GPIO Alternate Function Select 5Fh Antenna Control Interface Control and Status 60h to 61h Antenna Control Interface Transmit Data 62h to 63h Antenna Control Interface Receive Data Software Interrupt Raw Status, Status, Mask, and Clear Transaction F9, FB, FD, FFh Complete and Timeout Status The TVP9900 supports two modes of antenna control: Mode A for basic control (transmit transaction only) and Mode B for advanced control (transmit and receive transactions) as defined in the CEA-909 standard. For Mode B operation, the TVP9900 supports both 1-pin and 2-pin operation. In 1-pin mode, the data input and output are muxed into one pin (pin 29), and in 2-pin mode the input and output use separate pins (pin for output, pin for input.) The desired pin mode is selected by setting register 5Fh, bit Submit Documentation Feedback Functional

www.ti.com 4.7.1 Antenna Interrogation/Initialization TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Table 4-8 lists the TVP9900 pins and their functions used with the antenna control interface. Table 4-8. Antenna Control Interface Pins PIN NAME FUNCTION ANTCNTLIO Antenna control interface input/output GPIO1 Signal direction of pin in 1-pin mode GPIO0/ANTCNTLIN Antenna control input for 2-pin mode The GPIO1 pin provides dedicated smart antenna control support, and in 1-pin mode this pin outputs the direction of the signal on pin 29: GPIO1 indicates signal input from antenna to TVP9900 pin GPIO1 indicates signal output from TVP9900 pin to antenna Four status bit are provided in the TVP9900 to indicate the completion of a successful receive or transmit transaction, or if a transaction timeout has occurred. The ACIRXCT bit in the TVP9900 Software Interrupt Status Register (FBh) gets set when the receive transaction from a Mode B antenna is complete. The ACITXCT bit in the same register gets set when the transmit transaction to the antenna is complete. The ACIRXTO bit in the same register gets set when an interface timeout has occurred due to no reply form the antenna following a transmit transaction, or an incomplete receive transaction from the antenna. The RXERR bit in the Antenna Control Interface Control and Status Register (5Fh) is set if an incomplete receive transaction occurs. The TVP9900 can be configured so that setting the ACIRXCT, ACITXCT, or ACIRXTO status bits can assert the INTREQ output of the TVP9900; this requires the mask bits to be configured correctly in the TVP9900 Software Interrupt Mask Register (FDh). If the host INTREQ is not used, the ACIRXCT, ACITXCT, and ACIRXTO interrupts should be masked and the host should poll the ACIRXCT and ACITXCT status bits to determine when the transactions are complete, and the host should poll the ACIRXTO and RXERR status bits to determine when a receive timeout or error has occurred. Antenna control data transfers occur utilizing the following illustrated formats. The following steps are required to interrogate and initialize a smart antenna. The host processor first writes the required transaction data to a set of registers in the TVP9900 via the host processor I C interface. The system host processor transmits to the antenna a basic Mode A 14-bit serial data stream with an RF channel number of zero. The system tri-states the line and waits 100 ms for a reply message from the antenna controller. If no response is received, a timeout occurs, and the antenna controller is assumed to be a Mode A system. The system uses only transmit operations for antenna control. If the antenna responds with a 10-bit program identifier, the antenna controller is assumed to be a Mode B system, and the system uses transmit and receive operations for antenna control. This initialization is optional. If the system has only Mode A enabled, with no Mode B support, then this initialization step may be omitted. Functional

www.ti.com 4.7.2 Transmit Data to Antenna Operation 4.7.3 Receive Data from Antenna Operation 4.8 General-Purpose IO (GPIO) TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The following steps are required to transmit data to the antenna. The host processor writes the required transaction data to a set of registers in the TVP9900, as described below, via the host processor I C interface. Step Set TXRXSEL (bit to select a transmit data transaction, and set MODE (bit to enable auto receive Register 5Fh mode Step Registers 60h to 61h Load 14-bit data value to be transmitted to antenna Step Register 5Fh Set TXSTART (bit to to start transmit transaction to tuner Step Register FBh Check state of bit or INTREQ pin to verify successful transaction After an antenna transmit transaction is executed, a Mode B antenna should respond with a 10-bit data value within 100 ms. If the receive data is not received within 100 ms, then a receive timeout occurs. The following steps are required to receive data from the antenna. The host processor first writes the required transaction data to a set of registers in the TVP9900, as described below, via the host processor I C interface, then reads the data bytes received from the antenna stored in TVP9900 registers. Step Set TXRXSEL (bit to select a receive data transaction, and set MODE (bit to enable auto receive Register 5Fh mode Step Register FBh Check state of bit or INTREQ pin to verify successful transaction, or wait for timeout interrupt (bit to occur Step Registers 62h to 63h Read 10-bit data value received from antenna Step Register 5Fh Read RXERR value (bit The RXERR bit is set to to indicate an error occurred when receiving data from a Mode B antenna. If a non-zero data value was received from the antenna and no error occurred, then the data is valid and the antenna is a Mode B antenna. If the data value is zero and no error occurred, then a receive transaction did not occur and it is assumed that the antenna is a Mode A antenna. The TVP9900 has eight general-purpose IO pins, GPIO0 GPIO7. GPIO1 is a dedicated pin for Smart Antenna support. GPIO0, GPIO5, GPIO6, and GPIO7 are shared pins and can be programmed as the following dedicated functions. See register 4Fh functions. All pins are configured as inputs at device power-up. GPIO0 Antenna control input GPIO5 Sync output GPIO6 Reserved GPIO7 Interrupt request output Submit Documentation Feedback Functional

www.ti.com 4.9 Clock Circuits TVP9900 XTALIN XTALOUT

25 MHz

4 MHz

4.10 Power-Up Sequence 4.11 Reset TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 An internal PLL generates all clocks required in the chip. A 25-MHz clock is required to derive the PLL. Most tuner devices have a 4-MHz crystal oscillator that can be output to the demodulator as a clock source. In the TVP9900, a 4-MHz clock input also can be used as the clock source. A 4-MHz clock is input to the TVP9900 receiver on terminal (XTALIN), or a crystal of 25-MHz fundamental resonant frequency may be connected across terminals (XTALIN) and (XTALOUT). Figure 4-7 shows the reference clock configuration of 25-MHz crystal oscillation. NOTE: The oscillator input, XTALIN, is not 3.3-V tolerant and only works at 1.5-V signal levels. Figure 4-7. 25-MHz Crystal Oscillation Figure 4-8 shows the reference clock configuration of 4-MHz clock input. Figure 4-8. 4-MHz Clock Input No specific power-supply sequence is required, as long as all power supplies are ramped to valid operating levels within 500 ms of one another. Output or bidirectional buffers power-up with the output buffers in tri-state mode. The reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device at power-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of ms after all power-supply voltages are stable at the recommended operating voltage. Internal circuits synchronize the power-on reset with internal clocks; therefore, the RESETZ signal must remain active low for a minimum of µ s after the crystal oscillator and clocks are stable. Reset may be asserted any time after power up and stable crystal oscillation and must remain asserted for at least µ A minimum of 200 µ s must be allowed after reset before commencing I C operations. Functional

www.ti.com 4.12 Power Down 4.13 Power-Supply Voltage Requirements TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 There is no required power-down sequence for the TVP9900. The digital core uses a 1.5-V power supply. The digital IO cells use a 3.3-V power supply. Note that the exception is for the oscillator input, XTALIN, which is not 3.3-V tolerant and only works at 1.5-V signal levels. The analog circuitry uses both a 1.5-V and a 3.3-V power supply. Submit Documentation Feedback Functional

www.ti.com High-K PCB Design Recommendations 1.4 mm 0.33 mm 10-mm × 10-mm thermal land size 6 × 6 array of vias 1.4-mm via spacing 0.33-mm via diameter 10 mm 10 mm TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 In order to effectively transfer heat out of the package and to keep the die junction temperature below 105 the TVP9900 is packaged in the thermal PowerPAD package, which has an exposed metal pad on the bottom of the device. To effectively use this package, the following PCB design requirements must be followed. An array of thermal vias should be placed in the board at the placement location of the TVP9900, as shown in Figure 5-1. The ideal thermal land size is mm mm, and the ideal thermal via pattern is a array. The vias should be connected to the PCB ground plane. The exposed metal pad of the TVP9900 should be soldered to these vias. The copper trace thickness should be 0.071 mm oz), if possible. Figure 5-1. Thermal Land Size and Via Array Each of these recommendations is important to maximize the heat-sinking characteristics of the PCB. Refer to the Texas Instruments application report, PowerPAD Thermally Enhanced Package (literature number SLMA002 for more detailed information. High-K PCB Design Recommendations Submit Documentation Feedback

www.ti.com Host Processor I C Register Summary 6.1 Overview TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The TVP9900 IC is controlled by a host processor by using a set of control and status registers. Access to these registers by the host processor is via an I C serial interface. A summary of the I C host interface registers is given in Table 6-1 Table 6-1. I C Host Interface Registers ADDRESS REGISTER NAME DEFAULT R/W 00h Receiver Control Register Soft Reset 20h R/W 01h Receiver Control Register 11h R/W 02h Reserved 03h VSB Control Register 02h R/W 04h AGC Control Register 07h R/W 05h 1Ah Reserved 1Bh VSB FEC Time Counter Control Register BCh R/W 1Ch VSB FEC Time Counter Control Register 64h R/W 1Dh VSB FEC Time Counter Control Register 00h R/W 1Eh QAM FEC Time Counter Control Register 00h R/W 1Fh QAM FEC Time Counter Control Register 08h R/W 20h QAM FEC Time Counter Control Register 00h R/W 21h VSB FEC Segment Error Count Threshold 05h R/W 22h VSB FEC Segment Error Count Threshold 00h R/W 23h 24h Reserved 25h Update Status Control Register N/A R/W 26h Receiver Status Register N/A R 27h AGC Status Register AGC LF Accumulator Output (7:0) N/A R 28h AGC Status Register AGC LF Accumulator Output (15:8) N/A R 29h AGC Status Register AGC LF Accumulator Output (19:16) N/A R 2Ah NTSC Rejection Filter Status Register N/A R 2Bh Timing Recovery Status Register DTR LF Accumulator Output (7:0) N/A R 2Ch Timing Recovery Status Register DTR LF Accumulator Output (15:8) N/A R 2Dh Timing Recovery Status Register DTR LF Accumulator Output (23:16) N/A R 2Eh Timing Recovery Status Register DTR LF Accumulator Output (31:24) N/A R 2Fh Timing Recovery Status Register DTR LF Accumulator Output (39:32) N/A R 30h Timing Recovery Status Register DTR LF Accumulator Output (43:40) N/A R 31h 33h Reserved 34h Pilot Tracking Status Register DPT LF Accumulator Output (7:0) N/A R 35h Pilot Tracking Status Register DPT LF Accumulator Output (15:8) N/A R 36h Pilot Tracking Status Register DPT LF Accumulator Output (19:16) N/A R 37h 38h Reserved 39h Carrier Recovery Status Register DCL Average Error (7:0) N/A R 3Ah Carrier Recovery Status Register DCL Average Error (15:8) N/A R 3Bh Carrier Recovery Status Register DCL Average Error (19:16) N/A R 3Ch Carrier Recovery Status Register QAM DCL LF Accumulator Output (7:0) N/A R 3Dh Carrier Recovery Status Register QAM DCL LF Accumulator Output (15:8) N/A R 3Eh Carrier Recovery Status Register QAM DCL LF Accumulator Output (19:16) N/A R 3Fh 40h Reserved Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Table 6-1. I C Host Interface Registers (continued) ADDRESS REGISTER NAME DEFAULT R/W 41h Forward Error Correction Status Register N/A R 42h Reserved 43h Forward Error Correction Status Register FEC Segment Error Count (7:0) N/A R 44h Forward Error Correction Status Register FEC Segment Error Count (11:8) N/A R 45h Forward Error Correction Status Register N/A R 46h 4Eh Reserved 4Fh GPIO Alternate Function Select Register 00h R/W 50h GPIO Output Data Register 00h R/W 51h GPIO Output Enable Register FFh R/W 52h GPIO Input Data Register 00h R 53h MPEG Interface Output Enable Register 00h R/W 54h MPEG Interface Output Enable Register 00h R/W 55h Tuner Control Interface I C Slave Device Address 00h R/W 56h Tuner Control Interface Data Register 00h R/W 57h Tuner Control Interface Data Register 00h R/W 58h Tuner Control Interface Data Register 00h R/W 59h Tuner Control Interface Data Register 00h R/W 5Ah Tuner Control Interface Data Register 00h R/W 5Bh Tuner Control Interface Data Register 00h R/W 5Ch Tuner Control Interface Data Register 00h R/W 5Dh Tuner Control Interface Data Register 00h R/W 5Eh Tuner Control Interface Control and Status Register 00h R/W 5Fh Antenna Control Interface Control and Status Register 00h R/W 60h Antenna Control Interface Transmit Data Register 00h R/W 61h Antenna Control Interface Transmit Data Register 00h R/W 62h Antenna Control Interface Receive Data Register 00h R/W 63h Antenna Control Interface Receive Data Register 00h R/W 64h 6Fh Reserved 70h Firmware ID ROM Version 02h R 71h Firmware ID RAM Major Version 00h R 72h Firmware ID RAM Minor Version 00h R 73h 7Fh Reserved 80h Device ID LSB 00h R 81h Device ID MSB 99h R 82h EDh Reserved EEh Miscellaneous Control Register 00h R/W EFh F8h Reserved F9h Software Interrupt Raw Status Register 00h R FAh Reserved FBh Software Interrupt Status Register 00h R FCh Reserved FDh Software Interrupt Mask Register 00h R/W FEh Reserved FFh Software Interrupt Clear Register 00h W Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2 I C Register Definitions 6.2.1 Receiver Control Register Soft Reset TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Any write to this register causes a soft reset, which puts the receiver back into signal acquisition, and enables any changes made to registers 01h to 22h. Recommend performing soft reset after channel change. Address 00h Default 20h Bit Mnemonic RDNSEL MPEGSEL DCLKPS BYSTPS DERRPS PCLKPS DMDSEL Type R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME mode. RDNSEL redundancy select No redundancy (data only mode) selected (default) Data with redundancy mode selected The MPEG interface serial output select is used by the host processor to MPEG interface serial select the serial versus parallel output mode for the MPEG interface. MPEGSEL output select 8-bit parallel data output mode selected (default) Serial data output mode selected The MPEG interface data clock output polarity select is used by the host processor to select the polarity of the DCLK output pin. MPEG interface data All MPEG interface output signals transition with respect to the rising edge DCLKPS clock output polarity select of DCLK All MPEG interface output signals transition with respect to the falling edge of DCLK (default) The MPEG interface byte start output polarity select is used by the host MPEG interface byte start processor to select the polarity of the BYTESTART output pin. BYSTPS output polarity select BYTESTART is active high (default) BYTESTART is active low The MPEG interface data error output polarity select is used by the host MPEG interface data error processor to select the polarity of the DERROR output pin. DERRPS output polarity select DERROR is active high (default) DERROR is active low The MPEG interface packet clock output polarity select is used by the host MPEG interface packet processor to select the polarity of the PACCLK output pin. PCLKPS clock output polarity select PACCLK is active high (default) PACCLK is active low The VSB or QAM mode select bits are used by the host processor to select the demodulation type to be used by the TVP9900 receiver device. VSB or QAM VSB mode selected (default) 1:0 DMDSEL demodulation mode select Reserved QAM mode selected 256 QAM mode selected Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.2 Receiver Control Register 6.2.3 VSB Control Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 01h Default 11h Bit Mnemonic Reserved Reserved IQSWAP Reserved DNFCTRL DAFBYP Reserved Type R R R R/W R/W R/W R/W Default BIT MNEMONIC NAME 7:6 Reserved Reserved for future use Timing recovery spectral shift IQSWAP IQ swap Shift spectrum positive frequency (default) Shift spectrum negative frequency. For QAM mode, this bit swaps I and Reserved Reserved for future use. Always set to NTSC detection circuit control for VSB (always bypassed for QAM) Use detection circuit (default) NTSC detection circuit 3:2 DNFCTRL Force bypass of NTSC filter control Force insertion of NTSC filter Reserved Adjacent channel filter bypass for VSB (always bypassed for QAM) Adjacent channel filter DAFBYP Enable the adjacent channel filter (default) bypass Bypass the adjacent channel filter Reserved Reserved for future use. Always set to A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 03h Default 02h Bit Mnemonic Reserved Reserved Reserved RSTDIS Reserved Reserved Reserved Reserved Type R R R R/W R R R R Default BIT MNEMONIC NAME 7:5 Reserved Reserved for future use Disable VSB automatic soft reset mode. Firmware automatically restarts acquisition when there are too many RSTDIS Auto restart disable segment errors (default) Disable automatic restarts 3:0 Reserved Reserved for future use. Always set to 2h. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.4 AGC Control Register 6.2.5 VSB FEC Time Counter Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 04h Default 07h Bit Mnemonic Reserved Reserved Reserved Reserved Reserved DAGINV Reserved Type R R R R R R/W R Default BIT MNEMONIC NAME 7:3 Reserved Reserved for future use The Automatic Gain Control output signal (AGCOUT) invert select bit is used AGC output signal invert by the host processor to change the polarity of the output signal. DAGINV select AGCOUT is non-inverted AGCOUT is inverted (default) 1:0 Reserved Reserved for future use. Always set to 3h. A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 1Bh Default BCh Bit Mnemonic FCSFRSTIMECOUNT1 Type R/W Default 0xBC BIT MNEMONIC NAME (RS blocks) for segment error count; bits (7:0) 7:0 FCSFRSTIMECOUNT1 count, bits (7:0) of 24-bit value. The remaining bits are stored in registers 1Ch and 1Dh. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.6 VSB FEC Time Counter Register 6.2.7 VSB FEC Time Counter Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 1Ch Default 64h Bit Mnemonic FCSFRSTIMECOUNT2 Type R/W Default 0x64 BIT MNEMONIC NAME (RS blocks) for segment error count; bits (15:8) 7:0 FCSFRSTIMECOUNT2 count, bits (15:8) of 24-bit value A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 1Dh Default 00h Bit Mnemonic FCSFRSTIMECOUNT3 Type R/W Default 0x00 BIT MNEMONIC NAME (RS blocks) for segment error count; bits 7:0 FCSFRSTIMECOUNT3 count, bits (23:16) (23:16) of 24-bit value Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.8 QAM FEC Time Counter Register 6.2.9 QAM FEC Time Counter Register 6.2.10 QAM FEC Time Counter Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 1Eh Default 00h Bit Mnemonic JCSJRSTIMECOUNT1 Type R/W Default 0x08 BIT MNEMONIC NAME (RS blocks) for segment error count; bits (7:0) of 7:0 JCSJRSTIMECOUNT1 count, bits (7:0) 24-bit value. The remaining bits are stored in registers 1Fh and 20h. A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 1Fh Default 08h Bit Mnemonic JCSJRSTIMECOUNT2 Type R/W Default 0x08 BIT MNEMONIC NAME (RS blocks) for segment error count; bits (15:8) of 7:0 JCSJRSTIMECOUNT2 count, bits (15:8) 24-bit value A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 20h Default 00h Bit Mnemonic JCSJRSTIMECOUNT3 Type R/W Default 0x00 BIT MNEMONIC NAME (RS blocks) for segment error count; bits (23:16) 7:0 JCSJRSTIMECOUNT3 count, bits (23:16) of 24-bit value Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.11 VSB FEC Segment Error Count Threshold Register 6.2.12 VSB FEC Segment Error Count Threshold Register 6.2.13 Update Status Control Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 21h Default 05h Bit Mnemonic UNCORRINT1 Type R/W Default 0x05 BIT MNEMONIC NAME threshold; bits (7:0) of a 12-bit value. The remaining bits 7:0 UNCORRINT1 threshold, bits (7:0) are stored in register 22h. A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to register 00h. Address 22h Default 00h Bit Mnemonic Reserved Reserved Reserved Reserved UNCORRINT2 Type R R R R R/W Default BIT MNEMONIC NAME 7:4 Reserved Reserved Reserved for future use Segment error count 3:0 UNCORRINT2 Segment error count threshold; bits (11:8) of a 12-bit value threshold, bits (11:8) Address 25h Default 00h Bit Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved Reserved UPDATE Type R R R R R R R R/W Default BIT MNEMONIC NAME 7:1 Reserved Reserved for future use Update all status registers (26h to 45h) Host writes a to this bit to update all the status registers. Host should then UPDATE Update status registers read this bit until it reads the status update is then complete, and it is safe to read any/all of the status registers. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.14 Receiver Status Register 6.2.15 AGC Status Register 6.2.16 AGC Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 26h Bit Mnemonic Reserved Reserved Reserved ERRCNT Reserved SLCERR FLDSYNC Type R R R R R R R Default N/A N/A N/A N/A N/A N/A BIT MNEMONIC NAME 7:4 Reserved Reserved for future use Immediate RS segment error count threshold status bit Reed Solomon segment ERRCNT RS segment error count is below threshold error count status RS segment error count is above threshold Reserved Reserved for future use Immediate slicer error threshold status bit SLCERR Slicer error status Slicer error is below threshold Slicer error is above threshold Immediate field sync lock status bit FLDSYNC Field sync lock status Field sync is lost Field sync is locked (not lost) Address 27h Bit Mnemonic DAGLFACC1STAT Type R Default N/A BIT MNEMONIC NAME (7:0) of the 20-bit AGC loop filter accumulator output. The remaining bits AGC accumulator output, 7:0 DAGLFACC1STAT are stored in registers 28h and 29h. These register values are updated by bits (7:0) writing a to register 25h, bit Address 28h Bit Mnemonic DAGLFACC2STAT Type R Default N/A BIT MNEMONIC NAME output, 7:0 DAGLFACC2STAT Bits (15:8) of the 20-bit AGC loop filter accumulator output bits (15:8) Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.17 AGC Status Register 6.2.18 NTSC Rejection Filter Status Register 6.2.19 Timing Recovery Status Register 6.2.20 Timing Recovery Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 29h Bit Mnemonic Reserved Reserved Reserved Reserved DAGLFACC3STAT Type R R R R R Default N/A BIT MNEMONIC NAME 7:4 Reserved Reserved for future use AGC accumulator output, 3:0 DAGLFACC3STAT Bits (19:16) of the 20-bit AGC loop filter accumulator output bits (19:16) Address 2Ah Bit Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved Reserved DNFDETECT Type R R R R R R R R Default N/A BIT MNEMONIC NAME 7:1 Reserved Reserved for future use NTSC detection circuit status NTSC detection circuit DNFDETECT NTSC is NOT detected status NTSC is detected Address 2Bh Bit Mnemonic DTRLFACC1STAT Type R Default N/A BIT MNEMONIC NAME (7:0) of the 44-bit timing recovery loop filter accumulator output. The 7:0 DTRLFACC1STAT accumulator output, remaining bits are stored in registers 2Ch to 30h. These register values are bits (7:0) updated by writing a to register 25h, bit Address 2Ch Bit Mnemonic DTRLFACC2STAT Type R Default N/A BIT MNEMONIC NAME 7:0 DTRLFACC2STAT accumulator output, Bits (15:8) of the 44-bit timing recovery loop filter accumulator output bits (15:8) Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.21 Timing Recovery Status Register 6.2.22 Timing Recovery Status Register 6.2.23 Timing Recovery Status Register 6.2.24 Timing Recovery Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 2Dh Bit Mnemonic DTRLFACC3STAT Type R Default N/A BIT MNEMONIC NAME 7:0 DTRLFACC3STAT accumulator output, Bits (23:16) of the 44-bit timing recovery loop filter accumulator output bits (23:16) Address 2Eh Bit Mnemonic DTRLFACC4STAT Type R Default N/A BIT MNEMONIC NAME 7:0 DTRLFACC4STAT accumulator output, Bits (31:24) of the 44-bit timing recovery loop filter accumulator output bits (31:24) Address 2Fh Bit Mnemonic DTRLFACC5STAT Type R Default N/A BIT MNEMONIC NAME 7:0 DTRLFACC5STAT accumulator output, Bits (39:32) of the 44-bit timing recovery loop filter accumulator output bits (39:32) Address 30h Bit Mnemonic Reserved Reserved Reserved Reserved DTRLFACC6STAT Type R R R R R Default N/A BIT MNEMONIC NAME 7:4 Reserved Reserved for future use Timing recovery 3:0 DTRLFACC6STAT accumulator output, Bits (43:40) of the 44-bit timing recovery loop filter accumulator output bits (43:40) Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.25 Pilot Tracking Status Register 6.2.26 Pilot Tracking Status Register 6.2.27 Pilot Tracking Status Register 6.2.28 Carrier Recovery Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 34h Bit Mnemonic DPTLFACC1STAT Type R Default N/A BIT MNEMONIC NAME (7:0) of the 20-bit pilot tracking loop filter accumulator output. The Pilot tracking accumulator 7:0 DPTLFACC1STAT remaining bits are stored in registers 35h and 36h. These register values are output, bits (7:0) updated by writing a to register 25h, bit Address 35h Bit Mnemonic DPTLFACC2STAT Type R Default N/A BIT MNEMONIC NAME 7:0 DPTLFACC2STAT Bits (15:8) of the 20-bit pilot tracking loop filter accumulator output output, bits (15:8) Address 36h Bit Mnemonic Reserved Reserved Reserved Reserved DPTLFACC3STAT Type R R R R R Default N/A BIT MNEMONIC NAME 7:4 Reserved Reserved for future use Pilot tracking accumulator 3:0 DPTLFACC3STAT Bits (19:16) of the 20-bit pilot tracking loop filter accumulator output output, bits (19:16) Address 39h Bit Mnemonic DCLAVGERR1STAT Type R Default N/A BIT MNEMONIC NAME (7:0) of the 20-bit DCL average error (derotator SNR) value. The DCLAVGERR1ST DCL average error, bits 7:0 remaining bits are stored in registers 3Ah and 3Bh. These register values are AT (7:0) updated by writing a to register 25h, bit Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.29 Carrier Recovery Status Register 6.2.30 Carrier Recovery Status Register 6.2.31 Carrier Recovery Status Register 6.2.32 Carrier Recovery Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 3Ah Bit Mnemonic DCLAVGERR2STAT Type R Default N/A BIT MNEMONIC NAME error, 7:0 Bits (15:8) of the 20-bit DCL average error (derotator SNR) value AT bits (15:8) Address 3Bh Bit Mnemonic Reserved Reserved Reserved Reserved DCLAVGERR3STAT Type R R R R R Default N/A BIT MNEMONIC NAME 7:4 Reserved Reserved for future use DCLAVGERR3ST DCL average error, 3:0 Bits (19:16) of the 20-bit DCL average error (derotator SNR) value AT bits (19:16) Address 3Ch Bit Mnemonic DCLLFACC1STAT Type R Default N/A BIT MNEMONIC NAME (7:0) of the 20-bit DCL loop filter accumulator output for QAM. The QAM DCL loop filter 7:0 DCLLFACC1STAT remaining bits are stored in registers 3Dh and 3Eh. These register values accumulator output, bits (7:0) are updated by writing a to register 25h, bit Address 3Dh Bit Mnemonic DCLLFACC2STAT Type R Default N/A BIT MNEMONIC NAME 7:0 DCLLFACC2STAT Bits (15:8) of the 20-bit DCL loop filter accumulator output for QAM. accumulator output, bits (15:8) Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.33 Carrier Recovery Status Register 6.2.34 FEC Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 3Eh Bit Mnemonic Reserved Reserved Reserved Reserved DCLLFACC3STAT Type R R R R R Default N/A BIT MNEMONIC NAME 7:4 Reserved Reserved for future use QAM DCL loop filter 3:0 DCLLFACC3STAT accumulator output, Bits (19:16) of the 20-bit DCL loop filter accumulator output for QAM. bits (19:16) 6.2.34.1 VSB Mode Address 41h Bit Mnemonic FECSADDR1 Type R Default N/A BIT MNEMONIC NAME 7:2 Reserved Reserved for future use FEC synchronizer status bits Searching for sync (data not valid) FECSADDR1 1:0 FEC synchronizer status Locked sync (data valid) Reserved Sync lost (data not valid) 6.2.34.2 QAM Mode Address 41h Bit Mnemonic FECSADDR1 Type R Default N/A BIT MNEMONIC NAME locked, error under threshold 7:6 Trellis sync status Reserved Sync locked, error above threshold Hunting for sync Current deinterleaver control 5:2 FECSADDR1 Current deinterleaver control work value work value FEC synchronizer status bits Searching for sync (data not valid) 1:0 FEC synchronizer status Locked sync (data valid) Reserved Sync lost (data not valid) Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.35 FEC Status Register 6.2.36 FEC Status Register 6.2.37 FEC Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 43h Bit Mnemonic FECSADDR2 Type R Default N/A BIT MNEMONIC NAME (7:0) of the 12-bit FEC segment error count value. Bits (11:8) are stored in FEC segment error count, 7:0 FECSADDR2 register 44h, bits (7:4). These register values are updated by writing a to bits (7:0) register 25h, bit Address 44h Bit Mnemonic FECSADDR3 Type R Default N/A BIT MNEMONIC NAME count, 7:4 Bits (11:8) of the 12-bit FEC segment error count value bits (11:8) FECSADDR3 3:0 Reserved Reserved for future use 6.2.37.1 VSB Mode Address 45h Bit Mnemonic FECSADDR4 Type R Default N/A BIT MNEMONIC NAME 7:0 FECSADDR4 Reserved Reserved for future use 6.2.37.2 QAM Mode Address 45h Bit Mnemonic FECSADDR4 Type R Default N/A BIT MNEMONIC NAME 7:5 Reserved Reserved for future use Deframer synchronization FECSADDR4 Deframer synchronization Sync not locked Sync locked 3:0 Frame error maximum Maximum number of frame errors encountered Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.38 GPIO Alternate Function Select Register 6.2.39 GPIO Output Data Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 4Fh Default 00h Bit Mnemonic GPIO7FS GPIO6FS Reserved Reserved Reserved Reserved Reserved Reserved Type R/W R/W R R R R R R Default BIT MNEMONIC NAME pin. GPIO7FS GPIO bit function select Configures the GPIO7 pin as General Purpose IO bit (default). Configures the GPIO7 pin as the host processor INTREQ output. The GPIO bit and GPIO bit function select bit is used by the host processor to select the alternate function for both the GPIO6 and GPIO5 device pins. GPIO bit and GPIO bit GPIO6FS Configures the GPIO6 pin as General Purpose IO bit and GPIO5 pin as function select General Purpose IO bit (default). Configures the GPIO5 pin as the SYNCOUT output. The GPIO6 pin is reserved. 5:2 Reserved Reserved for future use NOTE: The GPIO1 pin is dedicated to Smart Antenna support. This pin outputs the direction of the signal on pin in Smart Antenna 1-pin mode (see Reserved register 5Fh, bit 0). If GPIO1 signal input from antenna to TVP9900 pin If GPIO1 signal output from TVP9900 pin to antenna NOTE: The GPIO0 pin has an alternate function, which is the Antenna Control Interface input (ANTCNTLIN) when 2-pin mode is selected for this interface. Reserved See the Antenna Control Interface Control and Status Register (5Fh), bit (pin mode select), for information on how to select this alternate function. Address 50h Default 00h Bit Mnemonic GPDO7 GPDO6 GPDO5 GPDO4 GPDO3 GPDO2 Reserved GPDO0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME pin. General purpose data General purpose data output bit is used by the host processor to set the data GPDO6 output bit value on the GPIO6 device pin. General purpose data General purpose data output bit is used by the host processor to set the data GPDO5 output bit value on the GPIO5 device pin. General purpose data General purpose data output bit is used by the host processor to set the data GPDO4 output bit value on the GPIO4 device pin. General purpose data General purpose data output bit is used by the host processor to set the data GPDO3 output bit value on the GPIO3 device pin. General purpose data General purpose data output bit is used by the host processor to set the data GPDO2 output bit value on the GPIO2 device pin. Reserved Reserved for future use General purpose data General purpose data output bit is used by the host processor to set the data GPDO0 output bit value on the GPIO0 device pin. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.40 GPIO Output Enable Register 6.2.41 GPIO Input Data Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 51h Default FFh Bit Mnemonic GPIO7OE GPIO6OE GPIO5OE GPIO4OE GPIO3OE GPIO2OE Reserved GPIO0OE Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME output. GPIO7OE output enable Configures GPIO7 as an output Configures GPIO7 as an input (default) General purpose IO bit output enable is used by the host processor to General purpose IO bit configure the GPIO6 device pin as either an input or output. GPIO6OE output enable Configures GPIO6 as an output Configures GPIO6 as an input (default) General purpose IO bit output enable is used by the host processor to General purpose IO bit configure the GPIO5 device pin as either an input or output. GPIO5OE output enable Configures GPIO5 as an output Configures GPIO5 as an input (default) General purpose IO bit output enable is used by the host processor to General purpose IO bit configure the GPIO4 device pin as either an input or output. GPIO4OE output enable Configures GPIO4 as an output Configures GPIO4 as an input (default) General purpose IO bit output enable is used by the host processor to General purpose IO bit configure the GPIO3 device pin as either an input or output. GPIO3OE output enable Configures GPIO3 as an output Configures GPIO3 as an input (default) General purpose IO bit output enable is used by the host processor to General purpose IO bit configure the GPIO2 device pin as either an input or output. GPIO2OE output enable Configures GPIO2 as an output Configures GPIO2 as an input (default) Reserved Reserved for future use General purpose IO bit output enable is used by the host processor to General purpose IO bit configure the GPIO0 device pin as either an input or output. GPIO0OE output enable Configures GPIO0 as an output Configures GPIO0 as an input (default) Address 52h Default 00h Bit Mnemonic GPDI7 GPDI7 GPDI7 GPDI7 GPDI7 GPDI7 Reserved GPDI7 Type R R R R R R R R Default BIT MNEMONIC NAME pin. General purpose data General purpose data input bit is used by the host processor to read the GPDI6 input bit data value on the GPIO6 device pin. General purpose data General purpose data input bit is used by the host processor to read the GPDI5 input bit data value on the GPIO5 device pin. General purpose data General purpose data input bit is used by the host processor to read the GPDI4 input bit data value on the GPIO4 device pin. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.42 MPEG Interface Output Enable Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 BIT MNEMONIC NAME pin. General purpose data General purpose data input bit is used by the host processor to read the GPDI2 input bit data value on the GPIO2 device pin. Reserved Reserved for future use General purpose data General purpose data input bit is used by the host processor to read the GPDI0 input bit data value on the GPIO0 device pin. Address 53h Default 00h Bit Mnemonic DO7OE DO6OE DO5OE DO4OE DO3OE DO2OE DO1OE DO0OE Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME output. After power-on reset, the output is disabled. DO7OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO6OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO5OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO4OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO3OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO2OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO1OE output enable Output is disabled (default) Output is enabled MPEG data output bit output enable is used by the host processor to enable MPEG data output bit the output. After power-on reset, the output is disabled. DO0OE output enable Output is disabled (default) Output is enabled Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.43 MPEG Interface Output Enable Register 6.2.44 Tuner Control Interface I C Slave Device Address Register 6.2.45 Tuner Control Interface Data Register Through TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 54h Default 00h Bit Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved SYNCSOE DCLKOE Type R R R R R R R/W R/W Default BIT MNEMONIC NAME 7:2 Reserved Reserved for future use MPEG sync signals output enable is used by the host processor to enable the MPEG interface sync signals, which are packet clock (PACCLK), byte start MPEG sync signals output (BYTESTART) and data error (DERROR). After power-on reset, the outputs SYNCSOE enable are disabled. Outputs are disabled (default) Outputs are enabled MPEG data clock output enable is used by the host processor to enable the MPEG data clock output clock output. After power-on reset, the output is disabled. DCLKOE enable Output is disabled (default) Output is enabled The I C slave device address register contains the 7-bit I C slave device address and the read/write transaction control bit to be used for the tuner device. Address 55h Default 00h Bit Mnemonic RW Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME I C 7:1 A(6:0) Slave device address slave address of the Tuner device to be accessed. The read/write control bit value is set by the host processor to program the type of Tuner Control Interface I C transaction to be done. RW Read/write control Read transaction Write transaction (default) Address 56h to 5Dh Default 00h Bit Mnemonic Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME a write transaction or the data bytes received from the tuner for a 7:0 D(7:0) Data (7:0) read transaction. The data byte contained in data register (56h) shall be the first byte sent to or read from the tuner. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.46 Tuner Control Interface Control and Status Register 6.2.47 Antenna Control Interface Control and Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 5Eh Default 00h Bit Mnemonic BCNT2 BCNT2 BCNT2 Reserved Reserved START Reserved MODE Type R/W R/W R/W R R R/W R R/W Default BIT MNEMONIC NAME device. The byte count should not include 7:5 BCNT(2:0) Byte count the tuner I C slave address byte. 000b byte, 001b bytes, ..., 110b bytes, 111b bytes 4:3 Reserved Reserved for future use The transaction start bit is set to by the host processor to indicate to the START Transaction start MCU to start the transaction to the tuner. The MCU clears this bit at the end of the transaction. Reserved Reserved for future use The mode bit is used by the host processor to set the I C transfer mode and rate. MODE I C mode Standard mode and 100-kbps transfer rate (default) Fast mode and 400-kbps transfer rate Address 5Fh Default 00h Bit Mnemonic Reserved Reserved RXERR MODE TXSTART TXRXSEL TXDINV PINSEL Type R R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME 7:6 Reserved Reserved for future use The receive data error bit is set to by the MCU to indicate an error occurred RXERR Receive data error when receiving data from a mode B antenna. The MCU clears this bit at the beginning of the next transaction. The auto receive mode bit is set to by the host processor to enable the MODE Auto receive mode antenna control interface logic to automatically set-up the receive mode after a transmit data transaction. This bit is set to by the host processor to start the transmit data transaction TXSTART Transmit start to the antenna. The MCU clears this bit when the transaction is complete. This bit is used by the host processor to select the next type of transaction to be done by the antenna control interface. In manual mode, the host processor controls this bit. In auto receive mode, the host processor sets this bit to for TXRXSEL Transmit/receive select the transmit data transaction, and the MCU sets this bit to after the completion of the transmit transaction to enable the receive transaction. Receive data transaction Transmit data transaction The transmit data polarity bit is set to by the host processor to invert the transmit data output. TXDINV Transmit data polarity Normal polarity in conformance with CEA909 Invert the transmit data output Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.48 Antenna Control Interface Transmit Data Register 6.2.49 Antenna Control Interface Transmit Data Register 6.2.50 Antenna Control Interface Receive Data Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 BIT MNEMONIC NAME configuration. Before the 2-pin mode is selected, the GPIO0 pin must be configured as an input in register 51h, bit PINSEL Pin mode select 2-pin mode (separate input and output pins are used, input pin 72, output pin 29) (default) 1-pin mode (one bidirectional pin is used, pin 29) Address 60h Default 00h Bit Mnemonic TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME 7:0 TXD(7:0) Transmit data (7:0) antenna. Bits (13:8) are stored in register 61h, bits (5:0). The data word is set by the host processor. Address 61h Default 00h Bit Mnemonic Reserved Reserved TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 Type R R R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME 7:6 Reserved Reserved for future use The most significant bits of the 14-bit data word to be transmitted to the 5:0 TXD(13:8) Transmit data (13:8) antenna. The data word is set by the host processor. Address 62h Default 00h Bit Mnemonic RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME a mode B 7:0 RXD(7:0) Receive data (7:0) antenna. Bits (9:8) are stored in register 63h, bits (1:0). Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.51 Antenna Control Interface Receive Data Register 6.2.52 Firmware ID ROM Version Register 6.2.53 Firmware ID RAM Major Version Register 6.2.54 Firmware ID RAM Minor Version Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 63h Default 00h Bit Mnemonic Reserved Reserved Reserved Reserved Reserved Reserved RXD9 RXD8 Type R R R R R R R/W R/W Default BIT MNEMONIC NAME 7:2 Reserved Reserved for future use The most significant bits of the 10-bit program code received from a mode B 1:0 RXD(9:8) Receive data (9:8) antenna. Address 70h Default 02h Bit Mnemonic ROMVER Type R Default 0x02 BIT MNEMONIC NAME 7:0 ROMVER ROM version Version identification for ROM code Address 71h Default 00h Bit Mnemonic RAM1VER Type R Default 0x00 BIT MNEMONIC NAME 7:0 RAM1VER Major RAM version Major version identification for RAM code Address 72h Default 00h Bit Mnemonic RAM2VER Type R Default 0x00 BIT MNEMONIC NAME 7:0 RAM2VER Minor RAM version Minor version identification for RAM code Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.55 Device ID LSB Register 6.2.56 Device ID MSB Register 6.2.57 Miscellaneous Control Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Address 80h Default 00h Bit Mnemonic DEVID1 Type R Default 0x00 BIT MNEMONIC NAME 7:0 DEVID1 Device ID LSB The LSB of the device ID Address 81h Default 99h Bit Mnemonic DEVID2 Type R Default 0x99 BIT MNEMONIC NAME 7:0 DEVID2 Device ID MSB The MSB of the device ID Address EEh Default 00h Bit Mnemonic Reserved Reserved Reserved Reserved Reserved INTRQPS MCUMDE MCURST Type R R R R R R/W R/W R/W Default BIT MNEMONIC NAME 7:3 Reserved Reserved for future use The interrupt request pin polarity select bit is used by the host processor to select either an active low or active high INTREQ output. Note that when active low is selected, the output goes tri-state when inactive (not driven high). Interrupt request pin INTRQPS Hence a pullup resistor needs to be used on the PCB. This is done so interrupt polarity select request sources from multiple ICs can be wired together. INTREQ output pin is active low (default) INTREQ output pin is active high The MCU memory mode is used by the host processor to select ROM or RAM as the code memory for the internal TVP9900 MCU. MCUMDE MCU memory mode MCU executes from ROM (default) MCU executes from RAM The MCU reset bit is used by the host processor to do a soft reset of the internal TVP9900 MCU. MCURST MCU reset MCU not in reset mode (default) MCU in reset mode Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.58 Software Interrupt Raw Status Register 6.2.59 Software Interrupt Status Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The raw status bits in this register are cleared by the host processor by writing a to the corresponding bit in the Software Interrupt Clear Register (FFh). The intended use of the raw status registers is for events to be monitored by the host processor via polling instead of interrupt driven. Address F9h Default 00h Bit Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type R R R R R R R R Default BIT MNEMONIC NAME 7:6 Reserved Reserved for future use The Antenna Control Interface receive transaction complete raw status bit is set to by the MCU when the receive transaction from a mode B antenna is complete. This means an entire 10-bit data word was received. If an Antenna Control Interface incomplete receive transaction (less than 10-bits) occurs, then this bit is not ACIRXCT receive transaction set; instead the ACIRXTO (bit occurs. After the receive transaction is complete complete, the host processor should also check the receive data error status bit (RXERR) in the Antenna Control Interface Control and Status Register (5Fh) to ensure that an error was not detected while receiving the data. Antenna Control Interface The Antenna Control Interface transmit transaction complete raw status bit is ACITXCT transmit transaction set to by the MCU when the transmit transaction to the antenna is complete. complete The Antenna Control Interface receive timeout raw status bit is set to by the MCU when the 100-ms timeout has occurred. If a 100-ms timeout occurs, then Antenna Control Interface the antenna either did not reply to the transmit transaction (it is a mode A ACIRXTO receive timeout antenna) or an incomplete (less than 10-bits) receive transaction occurred. If an incomplete transaction occurred, then the receive error status bit (RXERR) in the Antenna Control Interface Control and Status Register (5Fh) is also set. Reserved Reserved for future use The Tuner Control Interface transaction error raw status bit is set to by the Tuner Control Interface MCU to indicate to the host processor that the tuner device did not respond to TCIERROR transaction error the I C transaction or that a NO ACK was received from the tuner when an ACK was expected. The Tuner Control Interface transaction done raw status bit is set to by the Tuner Control Interface MCU at the end of a normal transaction to indicate to the host processor that TCIDONE transaction done the tuner I C transaction completed successfully. If an error occurs during a transaction to the tuner, the MCU does not set this bit to The status bits in this register are the result of the logical AND of the corresponding raw status bits and mask bits. A status bit is also automatically cleared when the corresponding raw status bit is cleared. Unmasked status bits in this register assert the host processor interrupt request output pin, INTREQ, of the TVP9900 when the status bit is set to All unmasked hardware and software status bits are ORed together to drive the INTREQ output pin. Address FBh Default 00h Bit Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type R R R R R R R R Default Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.60 Software Interrupt Mask Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 BIT MNEMONIC NAME 7:6 Reserved Reserved for future use Antenna Control Interface The Antenna Control Interface receive complete status bit is set to (if ACIRXCT receive transaction unmasked) when the receive transaction from a mode B antenna is complete complete and the bit is unmasked. Antenna Control Interface The Antenna Control Interface transmit complete status bit is set to (if ACITXCT transmit transaction unmasked) when the transmit transaction to the antenna is complete and the complete bit is unmasked. Antenna Control Interface The Antenna Control Interface receive timeout status bit is set to (if ACIRXTO receive timeout unmasked) when the 100-ms timeout has occurred and the bit is unmasked. Reserved Reserved for future use The Tuner Control Interface transaction error status bit is set to (if Tuner Control Interface unmasked) to indicate to the host processor that the tuner device did not TCIERROR transaction error respond to the I C transaction or that a NO ACK was received from the tuner when an ACK was expected. The Tuner Control Interface transaction done status bit is set to (if Tuner Control Interface unmasked) at the end of a normal transaction to indicate to the host processor TCIDONE transaction done that the tuner I C transaction completed successfully. If an error occurs during a transaction to the tuner, the MCU does not set this bit to The interrupt mask registers are used by the host processor to mask unused interrupt sources. When an interrupt status bit is masked, the event results in the raw status bit being set but does not result in the status bit being set or the assertion of the interrupt request output pin, INTREQ. Address FDh Default 00h Bit Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type R/W R/W R/W R/W R/W R/W R/W R/W Default BIT MNEMONIC NAME 7:6 Reserved Reserved for future use This bit is used by the host processor to enable the Antenna Control Interface Antenna Control Interface receive transaction complete interrupt. ACIRXCT receive transaction Interrupt disabled (default) complete interrupt mask Interrupt enabled This bit is used by the host processor to enable the Antenna Control Interface Antenna Control Interface transmit transaction complete interrupt. ACITXCT transmit transaction Interrupt disabled (default) complete interrupt mask Interrupt enabled This bit is used by the host processor to enable the Antenna Control Interface Antenna Control Interface receive timeout interrupt. ACIRXTO receive timeout interrupt Interrupt disabled (default) mask Interrupt enabled Reserved Reserved for future use This bit is used by the host processor to enable the Tuner Control Interface Tuner Control Interface transaction error interrupt. TCIERROR transaction error interrupt Interrupt disabled (default) mask Interrupt enabled This bit is used by the host processor to enable the Tuner Control Interface Tuner Control Interface transaction done interrupt. TCIDONE transaction done interrupt Interrupt disabled (default) mask Interrupt enabled Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com 6.2.61 Software Interrupt Clear Register TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The interrupt clear registers are used by the host processor to clear the interrupt raw status and status bits. To clear an interrupt, a must be written to the corresponding bit in this register. The interrupt clear bits are automatically reset to by the TVP9900 hardware. When all unmasked interrupts are cleared, the INTREQ device output pin is inactive. Address FFh Default 00h Bit Mnemonic Reserved Reserved ACIRXCT ACITXCT ACIRXTO Reserved TCIERROR TCIDONE Type W W W W W W W W Default BIT MNEMONIC NAME 7:6 Reserved Reserved for future use Antenna Control Interface This bit should be set to by the host processor to clear the Antenna ACIRXCT receive transaction complete Control Interface receive transaction complete raw status bit, which also interrupt clear clears the status bit and interrupt if unmasked. Antenna Control Interface This bit should be set to by the host processor to clear the Antenna ACITXCT transmit transaction complete Control Interface transmit transaction complete raw status bit, which also interrupt clear clears the status bit and interrupt if unmasked. This bit should be set to by the host processor to clear the Antenna Antenna Control Interface ACIRXTO Control Interface receive timeout raw status bit, which also clears the receive timeout interrupt clear status bit and interrupt if unmasked. Reserved Reserved for future use Tuner Control Interface This bit should be set to by the host processor to clear the Tuner Control TCIERROR transaction error interrupt Interface transaction error raw status bit, which also clears the status bit clear and interrupt if unmasked. Tuner Control Interface This bit should be set to by the host processor to clear the Tuner Control TCIDONE transaction done interrupt Interface transaction done raw status bit, which also clears the status bit clear and interrupt if unmasked. Submit Documentation Feedback Host Processor I C Register Summary

www.ti.com Electrical Specifications 7.1 Absolute Maximum Ratings (1) TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 This section provides the absolute maximum ratings and the recommended operating conditions for the TVP9900 device. All electrical and timing characteristics in this specification shall be valid over the recommended operating conditions, unless otherwise noted. over operating free-air temperature range (unless otherwise noted) DVDD_1_5 Supply voltage range 1.5 V digital core supply 0.5 V to 2.1 V IOVDD_3_3 Supply voltage range 3.3 V IO cell supply 0.5 V to 4.2 V AVDD_1_5 Supply voltage range 1.5 V analog core supply 0.5 V to 2.1 V AVDD_3_3 Supply voltage range 3.3 V analog core supply 0.5 V to 4.2 V AVDD_REF_3_3 Supply voltage range 3.3 V reference supply 0.5 V to 4.2 V AVDD_PLL_1_5 Supply voltage range 1.5 V PLL supply 0.5 V to 2.1 V XTALIN, oscillator input 0.5 V to AVDD_PLL_1_5 0.5 V V I Input voltage range Fail-safe LVCMOS 0.5 V to IOVDD_3_3 0.5 V Differential IF inputs: AIFIN_P, AIFIN_N 0.5 V to AVDD_3_3 0.5 V XTALOUT, oscillator output 0.5 V to AVDD_PLL_1_5 0.5 V V O Output voltage range Fail-safe LVCMOS 0.5 V to IOVDD_3_3 0.5 V I IK Input clamp current V I or V I V CC mA I OK Output clamp current V O or V O V CC mA T A Operating free-air temperature range C to C T stg Storage temperature range C to 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Electrical Specifications

www.ti.com 7.2 Recommended Operating Conditions 7.3 DC Electrical Characteristics TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 MIN NOM MAX UNIT DVDD_1_5 1.5-V digital core supply voltage 1.35 1.5 1.65 V IOVDD_3_3 3.3-V IO cell supply voltage 3.3 3.6 V AVDD_1_5 1.5-V analog core supply voltage 1.35 1.5 1.65 V AVDD_3_3 3.3-V analog core supply voltage 3.3 3.6 V AVDD_PLL_1_5 1.5-V PLL supply voltage 1.35 1.5 1.65 V AVDD_REF_3_3 3.3-V reference supply voltage 3.3 3.6 V XTALIN AVDD_PLL_1_5 V I Input voltage V LVCMOS IOVDD_3_3 XTALOUT AVDD_PLL_1_5 V O Output voltage V LVCMOS IOVDD_3_3 XTALIN 0.7(AVDD_PLL_1_5) AVDD_PLL_1_5 V IH High-level input voltage V LVCMOS 0.7(IOVDD_3_3) IOVDD3_3 XTALIN 0.3(AVDD_PLL_1_5) V IL Low-level input voltage V LVCMOS 0.3(IOVDD_3_3) I OH High-level output current LVCMOS mA I OL Low-level output current LVCMOS mA XTALIN f clock Clock input frequency MHz CLKIN t t Input transition, rise and fall time, 10% to 90% ns T A Operating free-air temperature C T J Operating junction temperature 105 C over recommended operating conditions (unless otherwise noted) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS V OH High-level output voltage LVCMOS I OH mA 0.8(IOVDD_3_3) V V OL Low-level output voltage LVCMOS I OL mA 0.22(IOVDD_3_3) V I IL Low-level input current V I V IL (min) µ A I IH High-level input current V I V IH (max) µ A I OZ High-impedance output current µ A I DVDD_1_5 1.5-V digital core supply current (1) 630 mA I IOVDD_3_3 3.3-V IO cell supply current (1) mA I AVDD_1_5 1.5-V analog core supply current (1) 0.2 mA I AVDD_3_3 3.3-V analog core supply current (1) mA I AVDD_PLL_1_5 1.5-V analog PLL supply current (1) mA I AVDD_REF_3_3 3.3-V analog reference supply current (1) mA 8-VSB mode with parallel MPEG 1.2 W P D Power dissipation output (1) Power-down mode 0.45 mW C i Input capacitance pF C o Output capacitance pF (1) For typical values: nominal voltages, T A C Electrical Specifications Submit Documentation Feedback

www.ti.com 7.4 Analog Input Characteristics TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V I Differential input voltage C coupling 0.1 µ F Vp-p R I Input resistance 2.4 k Ω C I Differential input capacitance pF Input gain control dB Input gain control ratio Submit Documentation Feedback Electrical Specifications

www.ti.com 7.5 Timing Characteristics 7.5.1 Crystal and Input Clock XTALIN tcyc1 7.5.2 Device Reset RESESTZ VDD (all supplies) tW1(L) TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 over recommended operating conditions (unless otherwise noted) The TVP9900 can be used with an external crystal with a frequency of MHz or with an external clock source with a frequency of MHz or MHz. The on-chip oscillator in the TVP9900 is designed to work with an external crystal with a frequency range of MHz to MHz. Therefore, if a clock frequency of MHz is required, an external clock source, not an external crystal, must be used. When an external clock source is used, the on-chip oscillator simply functions as an input buffer. Table 7-1. Crystal and Input Clock Timing PARAMETER MIN TYP MAX UNIT f XTALIN Frequency, XTALIN (external crystal or clock source) MHz t cyc1 Cycle time, XTALIN (external crystal or clock source) (1) ns f XTALIN Frequency, XTALIN (external clock source only) MHz t cyc1 Cycle time, XTALIN (external clock source only) (1) 250 ns Frequency stability ppm (1) Worst-case duty cycle is 45/55. Figure 7-1. Crystal or Clock Timing Waveform The power-on reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device at power-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of ms after all power-supply voltages are stable at the recommended operating voltage. Internal circuits synchronize the power-on reset with internal clocks; therefore, the RESETZ signal must remain active low for a minimum of µ s after the crystal oscillator and clocks are stable. Table 7-2. Device Reset Timing PARAMETER MIN TYP MAX UNIT Pulse duration, RESETZ low after all power supplies are stable at the recommended t w1(L) ms operating voltage and the crystal oscillator is stable Figure 7-2. Device Reset Signal Timing Waveforms Electrical Specifications Submit Documentation Feedback

www.ti.com 7.5.3 MPEG Interface 7.5.3.1 Parallel Mode (Data Only) PACCLK DCLK DATAOUT [7:0] tpd1 Byte 0 Byte 1 Byte 187 Byte 0 BYTE_START DERROR Byte 186 tpd2 tpd3 tpd4 tpd5 TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-3 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output signals transitioning with respect to the falling edge of DCLK. In this mode, PACCLK is always active. If an error occurs, the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes. Table 7-3. Parallel Mode (Data Only) Timing C L pF PARAMETER MIN TYP MAX UNIT VSB mode 2.42408 f DCLK Frequency, DCLK QAM mode 3.37129 MHz 256 QAM mode 4.85133 d cyc Duty cycle, DCLK t pd1 Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid ns t pd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high ns t pd3 Propagation delay time, DCLK falling (or rising) edge to BYTE_START low ns t pd4 Propagation delay time, DCLK falling (or rising) edge to DERROR high ns t pd5 Propagation delay time, DCLK falling (or rising) edge to DERROR low ns Figure 7-3. MPEG Interface Parallel Mode (Data Only) Timing Waveforms Submit Documentation Feedback Electrical Specifications

www.ti.com 7.5.3.2 Serial Mode (Data Only) PACCLK DCLK SERDATAO D7 BYTE_START DERROR D0 D7 D0 D7 tpd1 tpd2 tpd3 tpd4 tpd5 TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-4 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output signals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cycles corresponding to the eight bits of the first byte of data. In this mode, PACCLK is always active. If an error occurs, the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes. Table 7-4. Serial Mode (Data Only) Timing C L pF PARAMETER MIN TYP MAX UNIT VSB mode 19.39266 f DCLK Frequency, DCLK QAM mode 26.97035 MHz 256 QAM mode 38.81070 d cyc Duty cycle, DCLK t pd1 Propagation delay time, DCLK falling (or rising) edge to SERDATAO valid ns t pd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high ns t pd3 Propagation delay time, DCLK falling (or rising) edge to BYTE_START low ns t pd4 Propagation delay time, DCLK falling (or rising) edge to DERROR high ns t pd5 Propagation delay time, DCLK falling (or rising) edge to DERROR low ns Figure 7-4. MPEG Interface Serial Mode (Data Only) Timing Waveforms Electrical Specifications Submit Documentation Feedback

www.ti.com 7.5.3.3 Parallel Mode (Data With Redundancy) PACCLK DCLK DATAOUT [7:0] tpd1 Byte 0 Byte 1 BYTE_START DERROR Byte 187 tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 Byte 0 TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-5 are shown with BYTE_START, PACCLK and DERROR as active high signals and with the output signals transitioning with respect to the falling edge of DCLK. PACCLK is only active during the time period that the 188 bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the entire packet. Table 7-5. Parallel Mode (Data With Redundancy) Timing C L pF PARAMETER MIN TYP MAX UNIT VSB mode 2.68196 f DCLK Frequency, DCLK QAM mode 3.65821 MHz 256 QAM mode 5.26422 d cyc Duty cycle, DCLK t pd1 Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid ns t pd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high ns t pd3 Propagation delay time, DCLK falling or rising edge to BYTE_START low ns t pd4 Propagation delay time, DCLK falling (or rising) edge to PACCLK high ns t pd5 Propagation delay time, DCLK falling (or rising) edge to PACCLK low ns t pd6 Propagation delay time, DCLK falling (or rising) edge to DERROR high ns t pd7 Propagation delay time, DCLK falling (or rising) edge to DERROR low ns Figure 7-5. MPEG Interface Parallel Mode (Data With Redundancy) Timing Waveforms Submit Documentation Feedback Electrical Specifications

www.ti.com 7.5.3.4 Serial Mode (Data With Redundancy) D7 D0 D0 D7 PACCLK DCLK SERDATAO BYTE_START DERROR tpd1 tpd2 tpd4 tpd6 tpd3 tpd5 tpd7 TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in Figure 7-6 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output signals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cycles corresponding to the eight bits of the first byte of data. PACCLK is only active during the time period that the 188 bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the entire packet. Table 7-6. Serial Mode (Data With Redundancy) Timing C L pF PARAMETER MIN TYP MAX UNIT VSB mode 2.42408 f DCLK Frequency, DCLK QAM mode 3.37129 MHz 256 QAM mode 4.85133 d cyc Duty cycle, DCLK t pd1 Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid ns t pd2 Propagation delay time, DCLK falling (or rising) edge to BYTE_START high ns t pd3 Propagation delay time, DCLK falling (or rising) edge to BYTE_START low ns t pd4 Propagation delay time, DCLK falling (or rising) edge to DERROR high ns t pd5 Propagation delay time, DCLK falling (or rising) edge to DERROR low ns Figure 7-6. MPEG Interface Serial Mode (Data with Redundancy) Timing Waveforms Electrical Specifications Submit Documentation Feedback

www.ti.com 7.5.4 Host and Tuner I C Interface SCL SDA tw(H) tw(L) tr tf tsu1 th1 Start Condition Stop Condition SCL SDA tsu2 th2 tsu3 tbuf TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Host processor communication with the TVP9900 device is done via an I C slave interface. The TVP9900 also has an I C master interface that is used by the TVP9900 to communicate with the system tuner. Both of these I C interfaces are designed to work for both standard and fast modes of operation. The timing parameters and the timing waveforms below pertain to both I C interfaces. Table 7-7. Host and Tuner I C Interface Timing STANDARD FAST MODE MODE PARAMETER UNIT MIN MAX MIN MAX f SCL Frequency, SCL 100 400 kHz t W(H) Pulse duration, SCL high 0.6 µ s t W(L) Pulse duration, SCL low 4.7 1.3 µ s t r Rise time, SCL and SDA 1000 300 ns t f Fall time, SCL and SDA 300 300 ns t su1 Setup time, SDA to SCL 250 100 ns t Hold time, SCL to SDA (1) ns t buf Bus free time between stop and start condition 4.7 1.3 µ s t su2 Setup time, SCL to start condition 4.7 0.6 µ s t Hold time, start condition to SCL 0.6 µ s t su3 Setup time, SCL to stop condition 0.6 µ s C L Load capacitance for each bus line 400 400 pF (1) The TVP9900 internally provides a minimum hold time of 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Figure 7-7. I C SCL and SDA Timing Waveforms Figure 7-8. I C Start and Stop Conditions Timing Waveforms Submit Documentation Feedback Electrical Specifications

www.ti.com Application Circuit ABCD D C B A Tit le Numbe r Revis ion SizeB Date: 17-Jul-2006 Shee t of File: C:\\TV P9900\\TVP9900 A pp Circuit.ddb Drawn By: TVP990 0.Sch DA T AOUT[6. .0] DA T AOUT7 _S0 BYTE_V A LID P ACK_SYNCDCLKD_ERROR D3. .5V C1 0.1u F R1 24K 0.1% DG ND DGND A_R EF_3.3V D3.3V A3.3V .5V C2 0.1uFC3 0.1uF Put AC Cou pling Close to TVP 9900 ANTCNTL ANTCNTL TU NER_IF_OUT1 TUNER_IF_OUT2 R12 1.5K C21 0.01uF AGCOUT DGND AG COUT DGND JP2 I2CA0 10K JP2: TVP990

0 I2C Addr Se

D3.3V LOW (ON ): Address = 0xB 8h (default) HIGH (OFF): Add ress = 0xBAh X1 25MHz 18pF C40 18pF CLKIN_4_25MH z XT ALOUTXT AL REF APLL _1.5V XT ALIN XT ALOUTXT ALIN XT ALR EFDG ND OFF: C LKIN_4MHz DGND R9 10K ON: XT AL_25MH z (default) JP1 CLKIN_ SEL D3.3V DGND DGND HIGH (OFF ): PowerDown Mo de LOW (ON): Norm al Operation (defa ult) JP3: POWER DOWN (Activ e High) PWRDOWN DGND JP3 PWRD OWN R11 10K D3.3V DEM_SDA_3 _3V DEM_ SCL_3_3V GPIO7_INT REQ GPI O6_LOCK GPIO5_SYNCGPIO4GPIO3GPIO2GPIO1GPI DEM_SC L_3_3V DEM_SDA_3_3VTUNSDATUNSCL DGND DGND DGND DGND C24 0.1uF C4 0.01uF C8 0.01uF C26 0.1uF C7 0.01u F C25 0.1uF C5 0.01u F C22 0.1uF APLL_1.5V A1.5V A_REF_ 3.3V A3.3V C6 0.01uF C23 0.1uF D3.3V D3.3V C30 0.1uF C9 0.01uF C27 0.1uF C10 0.01uF C29 0.1uF C12 0.01uF C31 0.1uFC13 0.01uF C28 0.1uF C11 0.01uF DGND DG ND C14 0.01u F C15 0.01u F C17 0.01u F C18 0.01u F C16 0.01u F C19 0.01u F C20 0.01u F C35 0.1uF C32 0.1uF C34 0.1uF C36 0.1uF C33 0.1uF C37 0.1uF C38 0.1uF D1.5V D1.5V DGND DGND nRESET AGND A VDD _3_3 AIFIN AIFIN_N A VDD _3_3 AGND A VDD _1_5 AG ND AGND_P LL A VDD_PLL _1_5 XT ALOUT XT ALRE F XT ALIN CLK IN DIVINSEL CL KOUT DGND DVDD_1_5 IOGND IOVDD_3_3 RESETZ21 TMSEL022 TMSEL123 DGND 24 DVDD_1_525 TMSEL226 TMSEL327 AGCOUT28 ANTCNTLIO29 TUNSDA30 TUNSCL31 IOGND 32 IOVDD_3_333 I2CSDA34 I2CSCL35 DGND 36 DVDD_1_537 I2CA0 38 PWRDOWN39 DERROR40 DGND DCLK IOGND IOVDD_3_3 BY TEST AR T P ACCLK DGN D DVDD_1_5 DA T AOU T7/SERDA T A0 DA T AOUT6 DA T AOUT5 IOGND IO VDD DA T AOUT4 DA T A OUT3 DA T AOUT2 DGND DVDD_1_5 DA T AOUT1 DA T AOU GPIO7/INTREQ61 GPIO6/LOCK62 IOGND63 IOVDD_3_364 GPIO5/SYNCOUT65 GPIO466 GPIO367 DVDD_1_568 DGND69 GPIO270 GPIO171 GPIO0/ANTCNTLIN72 DVDD_1_573 DGND74 AGND75 AGND_REF76 A VDD_RE F_3_377 BIASRES78 BGREFCAP79 NSUB80 PWRP AD TVP9900 DNP R6 and R7 for 4MHz Inpu t from T uner Place R6, R7 an d R8 close to Pins 11 and 13 GPIO7_INTRE Q GPIO6_L OCK GPIO5_SYNC DA T AOUT[6..0] AIFIN_PAIFIN_N R8 0 DNP R8 fo r 25MHz Input fro m crystal (default) DNP R2 RP A CK8-10K R5 RP ACK4-33 R4 RP ACK4-33R3 RP ACK 4-33 JP1: CLKIN_SEL DA T A OUT0 DA T AOUT1DA T AOUT2 DA T AOU DA T AOUT DA T AOUT5DA T AOUT6 GPIO GPIO1GPI GPI GPIO4 TVP9900 VSB/QAM Receiver SLEA064 MARCH 2007 Application Circuit Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TVP9900PFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TVP9900PFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2007 Addendum-Page 1

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