TVP7000

TVP7000 TI | Alldatasheet

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8/10-BIT, MSPS, VIDEO AND GRAPHICS DIGITIZER WITH ANALOG PLL LCD TV/Monitors/Projectors Analog Channels DLP TV/Projectors dB to dB Analog Gain PDP TV/Monitors Analog Input MUXs PCTV Set-Top Boxes Auto Video Clamp Digital Image Processing Three Digitizing Channels, Each With Video Capture/Video Editing Independently Controllable Clamp, PGA, Scan Rate/Image Resolution Converters and ADC Video Conferencing Clamping: Selectable Clamping Between Video/Graphics Digitizing Equipment Bottom Level and Mid-level Offset: 1024-Step Programmable RGB or YPbPr Offset Control TVP7000 is a complete solution for digitizing video PGA: 8-Bit Programmable Gain Amplifier and graphic signals in RGB or YPbPr color spaces. ADC: 8/10-Bit MSPS A/D Converter The device supports pixel rates up to 150 MHz. Automatic Level Control Circuit Therefore, it can be used for PC graphics digitizing up to the VESA standard of SXGA (1280 1024) Composite Sync: Integrated Sync-on-Green resolution at Hz screen refresh rate, and in video Extraction From GreenLuminance Channel environments for the digitizing of digital TV formats, Support for DC and AC-Coupled Input including HDTV up to 1080p. TVP7000 can be used Signals to digitize CVBS and S-Video signal with 10-bit PLL ADCs. Fully Integrated Analog PLL for Pixel Clock The TVP7000 is powered from 3.3-V and 1.8-V Generation supply and integrates a triple high-performance A/D converter with clamping functions and variable gain, 12-150 MHz Pixel Clock Generation From independently programmable for each channel. The HSYNC Input clamping timing window is provided by an external Adjustable PLL Loop Bandwidth for pulse or can be generated internally. The TVP7000 Minimum Jitter includes analog slicing circuitry on the Y or G input to 5-Bit Programmable Subpixel Accurate support sync-on-luminance or sync-on-green extrac- Positioning of Sampling Phase tion. In addition, TVP7000 can extract discrete HSYNC and VSYNC from composite sync using a Output Formatter sync slicer. Support for RGB/YCbCr 4:4:4 and YCbCr TVP7000 also contains a complete analog PLL block 4:2:2 Output Modes to Reduce Board Traces to generate a pixel clock from the HSYNC input. Pixel Dedicated DATACLK Output for Easy clock output frequencies range from MHz to 150 Latching of Output Data MHz. System All programming of the part is done via an indus- Industry-Standard Normal/Fast I C Interface try-standard I C interface, which supports both read- With Register Readback Capability ing and writing of register settings. The TVP7000 is Space-Saving TQFP-100 Pin Package available in a space-saving TQFP 100-pin PowerPAD package. Thermally-Enhanced PowerPAD Package for Better Heat Dissipation Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Output Formatter ROUT[9:0] GOUT[9:0] Host Interface Timing Processor and Clock generation RIN_1 SCL SDA I2CA GIN_1 BIN_1 Clamp Clamp Clamp PGA PGA PGA 10−bit ADC 10−bit ADC 10−bit ADC HSYNC_A VSYNC_A COAST CLAMP FILT1 SOGIN_1 RESETB PWDN BOUT[9:0] SOGOUT HSOUT VSOUT DATACLK RIN_2 GIN_2 BIN_2 EXT_CLK SOGIN_2 HSYNC_B VSYNC_B FILT2 RIN_3 GIN_3 GIN_4 SOGIN_3 BIN_3 TVP7000 SLES143 SEPTEMBER 2005 ORDERING INFORMATION PACKAGED DEVICES T A 100-PIN PLASTIC FLATPACK PowerPAD C to C TVP7000PZP FUNCTIONAL BLOCK DIAGRAM

www.ti.com TERMINAL ASSIGNMENTS TVP7000 100−Pin TQFP Package (Top View) SOGIN_1 GIN_1 A18GND A18VDD A18GND A18VDD A18VDD A18GND RIN_3 RIN_2 RIN_1 A33GND A33VDD A33VDD A33GND BIN_3 BIN_2 BIN_1 A18VDD A18GND NSUB TEST VSOUT HSOUT SOGOUT IOVDD IOGND DATACLK B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 DVDD GND IOVDD IOGND G_9 G_8 G_7 G_6 G_5 G_4 G_3 G_2 SDA SCL I2CA TMS RESETB PWDN DVDD GND IOGND IOVDD R_0 R_1 R_2 R_3 R_4 IOGND R_5 R_6 R_7 R_8 R_9 IOGND IOVDD G_0 G_1 GIN_2 SOGIN_2 GIN_3 SOGIN_3 GIN_4 A33GND A33VDD A33VDD A33GND NSUB PLL_A18GND PLL_F FILT2 FILT1 PLL_A18GND PLL_A18VDD PLL_A18VDD PLL_A18GND HSYNC_B HSYNC_A EXT_CLK VSYNC_B VSYNC_A COAST CLAMP 100 TVP7000 SLES143 SEPTEMBER 2005

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 TERMINAL FUNCTIONS TERMINAL I/O NO. ANALOG VIDEO Analog video input for R/Pr RIN_1 I Analog video input for R/Pr RIN_2 I Analog video input for R/Pr RIN_3 I Analog video input for G/Y GIN_1 I Analog video input for G/Y GIN_2 100 I Analog video input for G/Y GIN_3 I Analog video input for G/Y GIN_4 I Analog video input for B/Pb BIN_1 I Analog video input for B/Pb BIN_2 I Analog video input for B/Pb BIN_3 I The inputs must be AC coupled. The recommended coupling capacitor is 0.1 µ Unused analog inputs should be connected to ground using a nF capacitor. CLOCK SIGNALS DATACLK O Data clock output EXT_CLK I External clock input for free running mode TEST O Internal MHz clock output, coast output, high-Z, or SOG output DIGITAL VIDEO ROUT [9:0] 59, O Digital video output of R/Cr, ROUT [9] is MSB. GOUT [9:0] 43-52 O Digital video output of G/Y, GOUT [9] is MSB. BOUT [9:0] 29-38 O Digital video output of B/Cb, BOUT [9] is MSB. For a 4:2:2 mode BOUT outputs CbCr data. Unused outputs can be left unconnected. MISCELLANEOUS SIGNALS PWDN I Power down input. Power down Normal mode RESETB I Reset input, active low Test Mode Select input. Used to enable JTAG test mode. Active high. Normal mode, this terminal TMS I should be connected to a ground. FILT1 O External filter connection for PLL. The recommended capacitor is 0.1 µ see Figure FILT2 O External filter connection for PLL. The recommended capacitor is 4.7 nF. See Figure HOST INTERFACE I C A I I C Address input SCL I I C Clock input SDA I/O I C Data bus POWER SUPPLIES NSUB 21, I Substrate ground. Connect to analog ground. A33VDD 13, 14, 93, I Analog power. Connect to 3.3 A33GND 12, 15, 92, I Analog 3.3 V return. Connect to Ground. A18GND I Analog 1.8V return. Connect to Ground A18VDD I Analog power. Connect to 1.8 PLL_A18VDD 84, I PLL analog power. Connect to 1.8 PLL_F I PLL filter internal supply connection PLL_A18GND 83, 86, I PLL analog power return. Connect to Ground. GND 40, I Digital return. Connect to Ground. DVDD 39, I Digital power. Connect to 1.8 V 27, 42, 54, 60, Digital power return. Connect to Ground. IOGND I IOVDD 26, 41, 53, I Digital power. Connect to 3.3 V or less for reduced noise. SYNC SIGNALS CLAMP I External Clamp input. Unused inputs can be connected to ground. COAST I External PLL COAST signal input. Unused inputs can be connected to ground

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS TVP7000 SLES143 SEPTEMBER 2005 TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. VSYNC_A I Vertical sync input A VSYNC_B I Vertical sync input Unused inputs can be connected to ground. HSYNC_A I Horizontal Sync input A HSYNC_B I Horizontal Sync input Unused inputs can be connected to ground. SOGIN1 I Sync-on-green input SOGIN2 I Sync-on-green input SOGIN3 i Sync-on-green input Unused inputs should be connected to ground using a nF capacitor. VSOUT O Vertical sync output HSOUT O Horizontal sync output SOGOUT O Sync-on-green slicer output over operating free-air temperature range (unless otherwise noted) (1) UNIT IOVDD to IOGND 0.5 V to 4.5 V DVDD to GND 0.5 V to 2.3 V Supply voltage range PLL_A18VDD to PLL_A18GND and A18VDD to A18GND 0.5 V to 2.3 V A33VDD to A33GND 0.5 V to 4.5 V Digital input voltage range VI to GND 0.5 V to 4.5 V Analog input voltage range AI to A33GND 0.2 V to 2.3 V Digital output voltage range VO to GND 0.5 V to 4.5 V TA Operating free-air temperature C to C Tstg Storage temperature C to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. over operating free-air temperature range, T A C to C (unless otherwise noted) MIN NOM MAX UNIT IOVDD Digital I/O supply voltage 3.0 3.3 3.6 V DVDD Digital supply voltage 1.70 1.8 1.9 V PLL_A18VDD Analog PLL supply voltage 1.70 1.8 1.9 V A18VDD Analog supply voltage 1.70 1.8 1.9 V A33VDD Analog supply voltage 3.0 3.3 3.6 V V I(P Analog input voltage (ac coupling necessary) 0.5 2.0 V V IH Digital input voltage high 0.7 IOVDD V V IL Digital input voltage low 0.3 IOVDD V I OH High level output current mA I OL Low level output current mA I OH_DATACLK DATACLK high level output current mA I OL_DATACLK DATACLK low level output current mA T A Operating free air temperature C

www.ti.com ELECTRICAL CHARACTERISTICS TVP7000 SLES143 SEPTEMBER 2005 IOVDD 3.3 DVDD 1.8 PLL_A18VDD 1.8 A18VDD 1.8 A33VDD 3.3 T A C PARAMETER TEST CONDITIONS MIN TYP (1) MAX (2) UNIT POWER SUPPLY I IOVDDD 3.3-V supply current 78.75 MHz 130 mA I DVDD 1.8-V supply current 78.75 MHz 253 260 mA P TOT Total power dissipation, normal mode 78.75 MHz 719 897 mW I IOVDDD 3.3-V supply current 108 MHz 101 160 mA I DVDD 1.8-V supply current 108 MHz 261 275 mA P TOT Total power dissipation, normal mode 108 MHz 803 1023 mW I IOVDDD 3.3-V supply current 148.5 MHz 128 240 mA I DVDD 1.8-V supply current 148.5 MHz 250 280 mA P TOT Total power dissipation, normal mode 148.5 MHz 872 1296 mW P DOWN Total power dissipation, power down mode mW (1) SMPTE color bar RGB input pattern used. (2) Worst case vertical line RGB input pattern used.

www.ti.com ELECTRICAL CHARACTERISTICS TVP7000 SLES143 SEPTEMBER 2005 IOVDD 3.3 DVDD 1.8 V 0.1, PLL_A18VDD 1.8 V 0.1, A18VDD 1.8 V 0.1, A33VDD 3.3 T A C to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INTERFACE Input voltage range By design 0.5 1.0 2.0 Vpp Z I Input impedance, analog video inputs By design 500 k Ω DIGITAL LOGIC INTERFACE C i Input capacitance By design pF Z i Input impedance By design 500 k Ω V OH Output voltage high I OH mA 0.8 IOVDD V V OL Output voltage low I OL mA 0.2 IOVDD V V OH_SCLK DATACLK output voltage high I OH mA 0.8 IOVDD V V OL_SCLK DATACLK output voltage low I OH mA 0.2 IOVDD V V IH High-level input voltage By design 0.7 IOVDD V V IL Low-level input voltage By design 0.3 IOVDD V A/D CONVERTERS Conversion rate 150 MSPS bit, 110 MHz 0.5 DNL DC differential nonlinearity LSB bit, 150 MHz 0.5 bit, 110 MHz INL DC integral nonlinearity LSB bit, 150 MHz Missing code bit, 150 MHz none SNR Signal-to-noise ratio MHz, 1.0 V P P at 110 dB MSPS Analog bandwidth By design 500 MHz PLL Clock jitter 500 ps Phase adjustment 11.6 degree VCO frequency range 150 MHz

www.ti.com TIMING REQUIREMENTS DATACLK Valid DataR, R, B, HSOUT Valid Data TVP7000 SLES143 SEPTEMBER 2005 PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT CLOCKS, VIDEO DATA, SYNC TIMING Duty cycle DATACLK 50% t DATACLK rise time 10% to 90% ns t DATACLK fall time 90% to 10% ns t Output delay time 1.5 3.5 ns (1) Measured with a load of pF. Figure Clock, Video Data, and Sync Timing

www.ti.com TIMING REQUIREMENTS SDA SCL Data Stop Start Stop TVP7000 SLES143 SEPTEMBER 2005 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I C HOST PORT TIMING t Bus free time between STOP and START Specified by design 1.3 µ s t Setup time for a (repeated) START condition Specified by design 0.6 µ s t Hold time (repeated) START condition Specified by design 0.6 µ s t Setup time for a STOP condition Specified by design 0.6 ns t Data setup time Specified by design 100 ns t Data hold time Specified by design 0.9 µ s t Rise time SDA and SCL signal Specified by design 250 ns t Fall time SDA and SCL signal Specified by design 250 ns C b Capacitive load for each bus line Specified by design 400 pF f 12C I C clock frequency Specified by design 400 kHz Figure I C Host Port Timing

www.ti.com FUNCTIONAL programmable. Each channel consists of a clamping circuit, a programmable gain amplifier, automatic offset control and an A/D converter. Analog Input Switch Control TVP7000 has analog channels that accept up to video inputs. The user can configure the internal analog video switches via the I2C interface. The analog video inputs can be used for different input configurations some of which are: Up to selectable individual composite video inputs Up to selectable RGB graphics inputs Up to selectable YPbPr video HD/SD inputs The input selection is performed by the input select register at I C subaddress and (see Input Mux Select and Input Mux Select Analog Input Clamping An internal clamping circuit restores the AC-coupled video/graphic signal to a fixed DC level. The clamping circuit provides line-by-line restoration of the signal black level to a fixed DC reference voltage. The selection between bottom and mid level clamping is performed by I C subaddress (see Sync On_Green Threshold) The internal clamping time can be adjusted by I C clamp start and width registers at subaddress and (see Clamp Start and Clamp Width) Programmable Gain Amplifier (PGA) The TVP7000 PGA can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a full-scale 10-bit A/D output code range. A 4-bit code sets the coarse gain (Red Coarse Gain, Green Coarse Gain, Blue Coarse Gain) with individual adjustment per channel. Minimum gain corresponds to a code (2-Vpp full-scale input, dB gain) while maximum gain corresponds to code F (0.5-Vpp full-scale, dB gain). TVP7000 also has 8-bit fine gain control (Red Fine Gain, Green Fine Gain, Blue Fine Gain) for RGB independently ranging from to For a normal PC graphics input, the fine gain will be used mostly. Programmable Offset Control and Automatic Level Control (ALC) The TVP7000 supports a programmable offset control for RGB independently. A 6-bit code sets the coarse offset (Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual adjustment per channel. The coarse offset ranges from LSB to +31 LSB. The coarse offset registers apply before the ADC. A 10-bit fine offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine offset ranges from 512 LSB to +511 LSB. ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I C register. It consists of pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by I C register address at 26. ALC circuit needs a timing pulse generated internally but user should program the position properly. The ALC pulse must be positioning after the clamp pulse. The position of ALC pulse is controlled by ALC placement I C register at address 31. This is available only for internal ALC pulse timing. For external clamp, the timing control of clamp is not applicable so the ALC pulse control is also not applicable. Therefore it is suggested to keep the external clamp pulse as long as possible. ALC is applied as same position of external clamp pulse. A/D Converters All ADCs have a resolution of 10-bits and can operate up to 150 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between MHz and 150 MHz. All ADC reference voltages are generated internally. Also the external sampling clock can be used.

www.ti.com COAST HSYNC Phase Detector PLL Control Register 0x03 Bit [5:3] PLL Control Register 0x03 Bit [7:6] Phase Select Register 0x04 Bit [7:3] Charge Pump VCO Phase Select Divider ADC Sampling CLK External Clock PLL Divide Register 0x01 and 0x02 Bit [11:0] Loop Filter ÷ N N = 1 or 2 TVP7000 SLES143 SEPTEMBER 2005 Analog PLL The analog PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal sync signal supplied on the HSYNC input or from extracted horizontal sync of sync slicer block for embedded sync signals. The analog PLL consisted of phase detector, loop filter, voltage controlled oscillator (VCO), divider and phase select. The analog block diagram is shown at Figure Figure PLL Block Diagram The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other time that the HSYNC is not available. There are several PLL controls to produce the correct sampling clock. The 12-bit divider register is programmable to select exact multiplication number to generate the pixel clock in the range of MHz to 150 MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass loop filter. The applicable current values are listed in the Table The 2-bit VCO range control is to improve the noise performance of the TVP7000. The frequency ranges for the VCO are shown in Table The phase of the PLL generated clock can be programmed in uniform steps over a single clock period (360/32=11.25 degrees phase resolution) so that the sampling phase of the ADC can be accurately controlled. In addition to sourcing the ADC channel clock from the PLL, an external pixel clock can be used (from pin 80). The PLL characteristics are determined by the loop filter design, by the PLL charge pump current, and by the VCO range setting. The loop filter design is shown in Figure Supported settings of VCO range and charge pump current for VESA standard display modes are listed in Table

www.ti.com 0.1 µF 4.7 nF 1.5 kΩ TVP7000 PLL_F FILT2 FILT1 TVP7000 SLES143 SEPTEMBER 2005 Figure PLL Loop Filter Table Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display Formats STANDARD RESOL- REFRESH HORIZON- PIXEL RATE PLL Divider PLLDIV PLLDIV LSB Reg 03h Output Div- VCO CP CUR- UTION RATE TAL (MHz) Total MSB Reg Reg 02h ider Reg RANGE Reg RENT Reg FRE- pix/line 01h [11:4] 04h [0] 03h [7:6] 03h [5:3] QUENCY (kHz) VGA 640 480 Hz 31.5 25.175 1600(2 64h 00h 68h Low (01b) 101b Hz 37.9 31.5 1664(2 68h 00h 58h Low (01b) 011b Hz 37.5 31.5 1680(2 69h 00h 58h Low (01b) 011b Hz 43.3 832 34h 00h 68h Low (01b) 101b SVGA 800 600 Hz 35.1 1024 40h 00h 68h Low (01b) 101b Hz 37.9 1056 42h 00h 68h Low (01b) 101b Hz 48.1 1040 41h 00h 68h Low (01b) 101b Hz 46.9 49.5 1056 42h 00h 68h Low (01b) 101b Hz 53.7 56.25 1048 41h 80h 68h Low (01b) 101b XGA 1024 768 Hz 48.4 1344 54h 00h 58h Low (01b) 011b Hz 56.5 1328 53h 00h A8h Med (10b) 101b Hz 78.75 1312 52h 00h A8h Med (10b) 101b Hz 68.7 94.5 1376 56h 00h A8h Med (10b) 101b SXGA 1280 1024 Hz 108 1688 69h 80h A8h Med (10b) 101b Hz 135 1688 69h 80h 98h Med (10b) 011b Video 720 480p Hz 31.468 1716(2 6Bh 40h 68h Low (01b) 101b 720 576p Hz 31.25 1728(2 6Ch 00h 68h Low (01b) 101b 1280 720p Hz 74.25 1650 67h 20h A8h Med (10b) 101b 1280 720p Hz 37.5 74.25 1980 7Bh C0h A8h Med (10b) 101b 1920 1080i Hz 33.75 74.25 2200 89h 80h A8h Med (10b) 101b 1920 1080i Hz 28.125 74.25 2640 A5h 00h A8h Med (10b) 101b 1920 Hz 67.5 148.5 2200 89h 80h D8h High (11b) 011b 1080p 1920 Hz 56.25 148.5 2640 A5h 00h D8h High (11b) 011b 1080p Sync Slicer TVP7000 includes a circuit that compares the input signal on Green channel to a level 150mV (typical value) above the clamped level (sync tip). The slicing level is programmable by I C register subaddress at 0x10. The digital output of the composite sync slicer is available on the SOGOUT pin. Sync Separator The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at the SOG input. The G or Y input containing the composite sync must be AC coupled to the SOG input pin using a 10-nF capacitor. Support for PC graphics, SDTV, and HDTV up to 1080p is provided.

www.ti.com Clock Generation SYNC Slicer SYNC Separator 5MHz CLK Polarity Detect SOG Phase Select ADCDIV HSYNC VSYNC COAST Activity Detect Activity Detect DATACLK SOGOUT VSOUT COAST HSYNC Activity Detect HSOUT Timing TVP7000 SLES143 SEPTEMBER 2005 Figure Sync Processing The TVP7000 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure All timing diagrams are shown for operation with internal PLL clock at phase For a 4:2:2 mode, CbCr data outputs at BOUT[9:0] pins.

www.ti.com RGBin HSYNC DATACLK RGBout HSOUT RGBin HSYNC DATACLK HSOUT GOUT BOUT P0 P1 P3 P10 P11 P12 13 clocks latency D0 D1 D3 D4 D5 Programmable Width P0 P1 P3 P10 P11 P12 13 clocks latency Programmable Width Y0 Y1 Y2 Y3 Y4 Cb2 Cr2 Cb4Cb0 Cr0 4:4:4: RGB/YCbCr Output Timing 4:2:2 YCbCr Output Timing TVP7000 SLES143 SEPTEMBER 2005 Figure Output Timing Diagram

www.ti.com I C Host Interface Reset and I C Bus Address Selection I C Operation Power-up, Reset, and Initialization TVP7000 SLES143 SEPTEMBER 2005 Communication with the TVP7000 device is via an I C host interface. The I C standard consists of two signals, serial input/output data (SDA) line and input clock line (SCL), which carry information between the devices connected to the bus. A third signal CA) is used for slave address selection. Although an I C system can be multi-mastered, the TVP7000 can function as a slave device only. Since SDA and SCL are kept open-drain at logic high output level or when the bus is not driven, the user should connect SDA and SCL to a positive supply voltage via a pull up resistor on the board. SDA is implemented bi-directional. The slave addresses select, terminal CA), enables the use of two TVP7000 devices tied to the same I C bus since it controls the least significant bit of the I C device address Table I C Host Interface Terminal I C A I Slave address selection SCL I Input clock line SDA I/O Input/output data line TVP7000 can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I C A pin. The TVP7000 device samples the level of terminal at power- up or at the trailing edge of RESETB and configures the I C bus address bit A0. The I C A terminal has an internal pull-down resistor to pull the terminal low to set a zero. Table I C Host Interface Device Addresses C R/W HEX (default) B9/B8 (1) BB/BA (1) If terminal strapped to DVDD via a 2.2 k Ω resistor, I C device address is set to Data transfers occur utilizing the following illustrated formats. S 10111000 ACK subaddress ACK send data ACK P Read from I C control registers S 10111000 ACK subaddress ACK S 10111001 ACK receive data NAK P S I C Bus Start condition P I C Bus Stop condition ACK Acknowledge generated by the slave NAK Acknowledge generated by the master, for multiple byte read master with ACK each byte except last byte Subaddress Subaddress byte Data Data byte, if more than one byte of DATA is transmitted (read and write), the subaddress pointer is automatically incremented I C bus address Example shown that I C A is in default mode. Write (B8h), Read (B9h) No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of each other. Reset may be low during power-up, but must remain low for at least µ s after the power supplies become stable. Alternately reset may be asserted any time with minimum ms delay after power-up and must remain asserted for at least µ Reset timing is shown in Figure It is also recommended that any I C operation starts µ s after reset ended. Table describes the status of the TVP7000 terminals during and immediately after reset.

www.ti.com Power Reset I2C 5 ms 1 µs 1 µs Control Registers TVP7000 SLES143 SEPTEMBER 2005 Table Reset Sequence SIGNAL NAME DURING RESET RESET COMPLETED ROUT[9:0], BOUT[9:0], BOUT[9:0] High impedence Output HSOUT, VSOUT, SOGOUT High impedence Output DATACLK High impedence Output Figure Reset Timing The TVP7000 is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP7000 is through a standard I C host port interface, as described earlier. Table shows the summary of these registers. Detailed programming information for each register is described in the following sections. Table Control Registers Summary (1) (2) Register Name I C Subaddress Default R/W Chip Revision 00h R PLL Divide MSB 01h 69h R/W PLL Divide LSB 02h D0h R/W PLL Control 03h 48h R/W Phase Select 04h 80h R/W Clamp Start 05h 80h R/W Clamp Width 06h 80h R/W HSYNC Output Width 07h 20h R/W Blue Fine Gain 08h 80h R/W Green Fine Gain 09h 80h R/W Red Fine Gain 0Ah 80h R/W Blue Fine Offset 0Bh 80h R/W Green Fine Offset 0Ch 80h R/W Red Fine Offset 0Dh 80h R/W Sync Control 0Eh 40h R/W PLL and Clamp Control 0Fh 4Eh R/W (1) Register addresses not shown in the register map summary are reserved and must not be written to. (2) Writing to or reading from any value labeled Reserved register may cause erroneous operation of the TVP7000. For registers with reserved bits, a must be written to reserved bit locations unless otherwise stated.

www.ti.com Register Definitions TVP7000 SLES143 SEPTEMBER 2005 Table Control Registers Summary (continued) Register Name I C Subaddress Default R/W Sync On Green Threshold 10h B8h R/W Sync Separator Threshold 11h 20h R/W Pre-Coast 12h 00h R/W Post-Coast 13h 00h R/W Sync Detect Status 14h R Output Formatter 15h 00h R/W Test Register 16h 00h R/W Reserved 17h 18h Input Mux Select 19h 00h R/W Input Mux Select 1Ah 00h R/W Blue and Green Coarse Gain 1Bh 55h R/W Red Coarse Gain 1Ch 05h R/W Fine Offset LSB 1Dh 00h R/W Blue Coarse Offset 1Eh 20h R/W Green Coarse Offset 1Fh 20h R/W Red Coarse Offset 20h 20h R/W HSOUT Output Start 21h 09h R/W MISC Control 22h 00h R/W Reserved 23h 25h Automatic Level Control Enable 26h 00h R/W Reserved 27h Automatic Level Control Filter 28h 00h R/W Reserved 29h Fine Clamp Control 2Ah 00h R/W Power Control 2Bh ADC Setup 2Ch 00h R/W Coarse Clamp Control 2Dh 00h R/W SOG Clamp 2Eh 00h R/W Reserved 2Fh 30h ALC Placement 31h 00h R/W R Read only W Write only R/W Read Write Chip Revision Subaddress 00h Read Only Chip revision [7:0] Chip revision [7:0]: Chip revision number

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 PLL Divide Subaddress 01h 02h Default (69D0h) PLL divide MSB [11:4] PLL divide LSB [3:0] Reserved PLL divide [11:0]: PLL divide number sets the number of pixels per line. Controls the PLL feedback divider. MSB [11:4] bits should be loaded first whenever a change is required PLL Control Subaddress 03h Default (48h) VCO[1:0] Charge Pump Current [3:1] Reserved Reserved Reserved VCO [1:0]: Selects VCO frequency range Ultra low Low (default) Medium High Charge Pump Current [3:0]: Selects charge current of PLL LPF 000 Small (default) 111 Large Phase Select Subaddress 04h Default (80h) Phase Select [4:0] Reserved DIV2 Phase Select [4:0]: ADC Sampling clock phase select. LSB 11.25 DATACLK Divide-by-2 DATACLK/1 DATACLK/2 Clamp Start Subaddress 05h Default (80h) Clamp Start [7:0] Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected this value has no meaning Clamp Width Subaddress 06h Default (80h) Clamp Width [7:0] Clamp Width [7:0]: Sets the width in pixels for clamp. See register Clamp Start.

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Table Recommended Fine Clamp Settings VIDEO STANDARD CLAMP START CLAMP WIDTH HDTV (tri-level) (32h) (20h) SDTV (bi-level) (06h) (10h) PC Graphics (06h) (10h) HSYNC Output Width Subaddress 07h Default (20h) HSOUT Width [7:0] HSOUT Width [7:0]: Sets the width in pixels for HSYNC output. Blue Fine Gain Subaddress 08h Default (80h) Blue Gain [7:0] Blue Gain [7:0]: PGA digital gain (contrast) for Blue channel applied after the ADC. Gain Blue Gain[7:0]/256 80h Recommended setting for 700 mVp-p input and default Coarse Gain (default). Green Fine Gain Subaddress 09h Default (80h) Green Gain [7:0] Green Gain [7:0]: PGA digital gain (contrast) for Green channel applied after the ADC. Gain Green Gain[7:0]/256 80h Recommended setting for 700 mVp-p input and default Coarse Gain (default). Red Fine Gain Subaddress 0Ah Default (80h) Red Gain [7:0] Red Gain [7:0]: Sets PGA digital gain (contrast) for Red channel applied after the ADC. Gain Red Gain[7:0]/256 80h Recommended setting for 700 mVp-p input and default Coarse Gain (default).

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Blue Fine Offset Subaddress 0Bh Default (80h) Blue Offset [9:2] Blue Offset [9:2]: DC digital offset (brightness) for Blue channel applied after the ADC. The default setting of 80h will place the bottom-level (YRGB) clamped output blank levels at and mid-level clamped (PbPr) output blank levels at 512. Blue Offset (default) 01111111 LSB 00000000 minimum Green Fine Offset Subaddress 0Ch Default (80h) Green Offset [9:2] Green Offset [9:2]: DC digital offset (brightness) for Green channel applied after the ADC. See Red Fine Offset register at I C address 0x0B Red Fine Offset Subaddress 0Dh Default (80h) Red Offset [9:2] Red Offset [9:2]: DC digital offset (brightness) for Red channel applied after the ADC. See Blue Fine Offset register at I C address 0x0B.

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Sync Control Subaddress 0Eh Default (40h) HSPO HSIP HSOP AHSO AHSS VSOI AVSO AVS HSPO: HSYNC Polarity Override Polarity determined by chip (default) Polarity set by Bit in register 0Eh HSIP: HSYNC Input Polarity Indicates input HSYNC polarity active low Indicates input HSYNC polarity active high (default) HSOP: HSYNC Output Polarity Active low (default) Active high AHSO: Active HSYNC Override The active interface is selected via Bit in register 14h, selected by chip (default) The user can select HSYNC to be used via Bit AHSS: Active HSYNC Select. The indicated HSYNC will be used only if Bit is set to or both syncs are active (Bits 1,7 in 14h) Select HSYNC as the active sync (default) Select Sync-on-green as the active sync VSOI: VSYNC Output Invert (relative to VSYNC IN polarity) No invert (default) Invert AVSO: Active VSYNC Override The active interface is selected via Bit3 in register 14h, selected by chip (default) The user can select the VSYNC to be used via Bit AVS: Active VSYNC select, This bit is effective when AVSO Bit is set to Raw VSYNC (default) Sync separated VSYNC

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 PLL and Clamp Control Subaddress 0Fh Default (4Eh) CF CP Coast Sel CPO CPC Reserved FCPD Free run Clamp Function: Internal Clamp(default) External Clamp Clamp Polarity: Active high Active low (default) Coast Select: External coast (default) Internal Coast Coast Polarity Override: Polarity determined by chip (default) Polarity set be Bit in register 0Fh Coast Polarity Change: Active low Active high (default) Full Chip Power-Down: Power-down mode Normal operation (default) Free run: Also ADC test mode, ADC uses external clock PLL normal operation (default) Enabled Sync On_Green Threshold Subaddress 10h Default (B8h) SOG Threshold [4:0] Blue CS Green CS Red CS SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator. The minimum setting is mV and the maximum is 350 mV. The step is mV. (default 17h, 10h recommended) Blue Clamp Select: When free running mode this bit is no effect Bottom level clamp (default) Mid level clamp Green Clamp Select: When free running mode this bit is no effect Bottom level clamp (default) Mid level clamp Red Clamp Select: When free running mode this bit is no effect. Bottom level clamp (default) Mid level clamp

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Sync Separator Threshold Subaddress 11h Default (20h) Sync Separator Threshold [7:0] Sync Separator Threshold [7:0]: Sets how many internal MHz clock periods the sync separator will count to before toggling high or low. The selection of this register affects the VSYNC out position relative to HSYNC out. Pre-Coast Subaddress 12h Default (00h) Pre-Coast [7:0] Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC. Post-Coast Subaddress 13h Default (00h) Post-Coast [7:0] Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC. Table Recommended Pre and Post-Coast Settings STANDARD PRE_COAST POST-COAST 480i/p with Macrovision 0Ch 576i/p with Macrovision 0Ch 1080i 1080p 720p

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Sync Detect Status Subaddress 14h Read Only HSD AHS IHSPD VSD AVS VSPD SOGD ICPD HSYNC Detect: No HSYNC detected HSYNC detected Active HSYNC: HSYNC input pin HSYNC from SOG Input HSYNC Polarity Detect: Active low Active high VSYNC Detect: No VSYNC detected VSYNC detected AVS: VSYNC input pin VSYNC from Sync separator VSYNC Polarity Detect: Active low Active high SOG Detect: No SOG detected SOG is present on the SOG interface Input Coast Polarity Detect: Active low Active high Output Formater Subaddress 15h Default (00h) Reserved Clamp REF CbCr order Reserved Clamp REF: Clamp pulse placement respect to the trailing edge of HSYNC (default) Clamp pulse placement respect to the leading edge of HSYNC CbCr order: This bit is effective when Bit is set to CrCb (default) CbCr 422/444: Output is in 4:4:4 format (default) Output is in 4:2:2 format

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Test Register Subaddress 16h Default (00h) Pixel tolerance [2:0] Reserved Test ouptut PLL PD STRTB Pixel tolerance: 000 No tolerance (default) 001 pixel tolerance (recommended setting for best SOG performance) 111 pixel tolerance (maximum) Test output: Controls TEST pin output MHz clock (default) Coast output Clamp High impedance PLL PD: PLL power-down Normal operation (default) PLL powered down STRTB: PLL start-up circuit enable Disabled (default) Enabled Input Mux Select Subaddress 19h Default (00h) SOG Select [1:0] Red Select [1:0] Green Select [1:0] Blue Select [1:0] SOG Select [1:0]: CH1 selected (default) CH2 selected CH3 selected Reserved Red Select [1:0]: CH1 selected (default) CH2 selected CH3 selected Reserved Green Select [1:0]: CH1 selected (default) CH2 selected CH3 selected CH4 selected Blue Select [1:0]: CH1 selected (default) CH2 selected CH3 selected Reserved

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Input Mux Select Subaddress 1Ah Default (00h) Reserved VSYNC Select Reserved HSYNC Select Bit It must be written to VSYNC Select: VSYNC_A selected (default) VSYNC_B selected HSYNC Select [1:0]: HSYNC_A selected (default) HSYNC_B selected Blue and Green Coarse Gain Subaddress 1Bh Default (55h) Green Gain [3:0] Blue Gain [3:0] Green Coarse Gain [3:0]: Coarse analog gain for Green channel applied before the ADC. Gain [3:0] 0.5 0001 0.6 0010 0.7 0011 0.8 0100 0.9 0101 1.0 0110 1.1 0111 1.2 1000 1.3 Maximum recommended gain for 700mVp-p input. 1001 1.4 1010 1.5 1011 1.6 1100 1.7 1101 1.8 1110 1.9 1111 2.0 Blue Coarse Gain [3:0]: Coarse gain for Blue channel Red Coarse Gain Subaddress 1Ch Default (05h) Reserved Red Gain [3:0] Red Coarse Gain [3:0]: Coarse analog gain for Red channel applied before the ADC.

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Fine Offset LSB Subaddress 1Dh Default (00h) Reserved Red Offset [1:0] Green Offset [1:0] Blue Offset [1:0] Red Offset [1:0] Offset LSB for red channel. This is LSB of register 0x0D Green Offset [1:0] Offset LSB for green channel. This is LSB of register 0x0C Blue Offset [1:0] Offset LSB for blue channel. This is LSB of register 0x0B Blue Coarse Offset Subaddress 1Eh Default (20h) Reserved Blue offset [5:0] Blue Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC. 1Fh +31 LSB (Recommended for optimum ALC performance) 00h LSB 20h LSB (default) 3Fh -32 LSB Green Coarse Offset Subaddress 1Fh Default (20h) Reserved Coarse Green offset [5:0] Green Coarse offset [5:0]: Coarse analog offset for green channel applied before the ADC. 1Fh +31 LSB (Recommended for optimum ALC performance) Red Coarse Offset Subaddress 20h Default (20h) Reserved Coarse Red offset [5:0] Red Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC. 1Fh +31 LSB (Recommended for optimum ALC performance) HSOUT Output Start Subaddress 21h Default (09h) HSOUT Start [7:0] HSOUT Start [7:0]: HSYNC output Start pixel number.

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 MISC Control Subaddress 22h Default (00h) Reserved MAC_EN Reserved VS_ALIGN Reserved MAC_EN: Macrovision compatibility disabled (default) Macrovision compatibility enabled VS_ALIGN VSOUT alignment relative to HSOUT varies with SyncSep Threshold VSOUT alignment not affected by SyncSep Threshold Automatic Level Control Enable Subaddress 26h Default (00h) ALC enable Reserved ALC enable: Automatic level control enable Disabled (default) Enabled

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Automatic Level Control Filter Subaddress 28h Default (00h) Reserved NSV[3:0] NSH [2:0] The horizonal ALC coefficient (NSH) specifies the number of the horizonal samples (N) used to calculate the average blank level per horizonal line. Offset error correction is applied immediately based on the vertical (NSV) coefficient. The vertical coefficient (NSV) specifies the amount of offset error correction (derived from NSH) that is applied to each line update. NSV [3:0]: ALC vertical filter coefficient NSV [3:0] (default) Maximum error correction applied per line update 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Minimum error correction applied per line update NSH [2:0]: ALC horizontal sample filter coefficient NSH [2:0] (default) Minimum number of pixels used in horizonal filter 001 010 011 100 101 110 111 Maximum number of pixels used in horizonal filter

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 Fine Clamp Control Subaddress 2Ah Default (00h) Reserved Fine swsel[1:0] Fine B Fine G Fine R Fine swsel: Fine clamp time constant adjustment Highest (default) Lowest Fine Blue channel fine clamp is off (default) Blue channel fine clamp is on Fine Green channel fine clamp is off (default) Green channel fine clamp is on Fine Red channel fine clamp is off (default) Red channel fine clamp is on Power Control Subaddress 2Bh (Default 00h) SOG SLICER REF CURRENT PW ADC B PW ADC G PW ADC R SOG: Normal operation (default) SOG power-down Slicer: Normal operation (default) Slicer power-down Reference: Normal operation (default) Reference block power-down Current control: Normal operation (default) Current control block power-down PW ADC Power-down ADC blue channel PW ADC Power-down ADC red channel ADC channel power-down PW ADC Power-down ADC green channel PW ADC Power-down ADC red channel ADC channel power-down PW ADC Power-down ADC red channel PW ADC Power-down ADC red channel ADC channel power-down

www.ti.com TVP7000 SLES143 SEPTEMBER 2005 ADC Setup Subaddress 2Ch (Default 00h) 50h Recommended setting Coarse Clamp Control Subaddress 2Dh Default (00h) CCCLP_cur_CH1 Reserved Coarse B Coarse G Coarse R Coarse clamp charge current switch selection: Highest (default) Lowest Course Coarse clamp off at BLUE channel (default) Coarse clamp on at BLUE channel Coarse G Coarse clamp off at GREEN channel (default) Coarse clamp on at GREEN channel Coarse R Coarse clamp off at RED channel (default) Coarse clamp on at RED channel SOG Clamp Subaddress 2Eh (Default 00h) SOG_CE Reserved SOG_CE: SOG Clamp disabled (default) SOG Clamp enabled. Set to for SOG operation. ALC Placement Subaddress 31h (Default 00h) ALC placement [7:0] ALC placement [7:0]: Default 18h PC graphics and SDTV with bi-level syncs 5Ah HDTV with tri-level syncs Positions the ALC signal an integer number of clock periods after the HSYNC signal. ALC must be applied after the clamp end.

www.ti.com TVP7000 SLES143 SEPTEMBER 2005

www.ti.com APPLICATION INFORMATION 10 nF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 4.7 nF 75 Ω 75 Ω 75 Ω 2.2 kΩ x 2 2.2 kΩ x 3 G/Y B/Pb R/Pr HSYNC VSYNC +3.3 V GIN1 BIN1 RIN1 HSYNC_A VSYNC_A RESETB SOG1 PLL_F FILT2 FILT1 SDA SCL I2C COAST PWDN CLAMP TMS 1.5 kΩ GOUT[9:0] BOUT[9:0] ROUT[9:0] DATACLK SOGOUT VSOUT HSOUT Schematic TVP7000 SLES143 SEPTEMBER 2005 Figure TVP7000 Application Example

A B C D 654321 D C B A Title Number RevisionSize C Date: 31-Aug-2005 Sheet of File: C:\\Documents and Settings\\a0214685.ENT\\Desktop\\TVP7000_EVM_MODULE_REV1.0.ddbDrawn By: I2CA I2C ADDRESS SELECTION 2-3: Base Addr 0xBA 1-2: Base Addr 0xB8 - Default 10k SDA SCL TVP7000 REV 1.1 10k 10nF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF RESETB 0.1uF 10nF 0.1uF 10nF 0.1uF GIN_3 GIN_1 BIN_1 BIN_3 RIN_1 RIN_3 I2CA PLL_F FILT2 FILT1 VSYNC_A VSYNC_B HSYNC_A HSYNC_B SOGOUT 0.1uF 0.1uF 0.1uF 4.7nF 0.1uF FILT1 FILT2 49.9 49.9 49.9 49.9 R[9..0] G[9..0] B[9..0] R[9..0] G[9..0] B[9..0] DCLK VSOUT HSOUT SOGIN_11 GIN_12 A18GND3 A18VDD4 A18GND5 A18VDD6 A18VDD7 A18GND8 RIN_39 RIN_210 RIN_111 A33GND12 A33VDD13 A33VDD14 A33GND15 BIN_316 BIN_217 BIN_118 A18VDD19 A18GND20 NSUB21 TEST22 VSOUT23 HSOUT24 SOGOUT25 IOVDD26 IOGND27 DATACLK28 B_929 B_830 B_731 B_632 B_533 B_434 B_335 B_236 B_137 B_038 DVDD39 GND40 IOVDD41 IOGND42 G_943 G_844 G_745 G_646 G_547 G_448 G_349 G_250 G_1 51G_0 52IOVDD 53IOGND 54R_9 55R_8 56R_7 57R_6 58R_5 59IOGND 60R_4 61R_3 62R_2 63R_1 64R_0 65IOVDD 66IOGND 67GND 68DVDD 69PWDN 70RESETB 71TMS 72I2CA 73SCL 74SDA 75 CLAMP 76COAST 77VSYNC_A 78VSYNC_B 79EXT_CLK 80HSYNC_A 81HSYNC_B 82PLL_A18GND 83PLL_A18VDD 84PLL_A18VDD 85PLL_A18GND 86FILT1 87FILT2 88PLL_F 89PLL_A18GND 90NSUB 91A33GND 92A33VDD 93A33VDD 94A33GND 95GIN_4 96SOGIN_3 97GIN_3 98SOGIN_2 99GIN_2 100 PwrPad D3.3V D3.3V D1.8V A1.8VA3.3V A3.3V A1.8V 1 3 JMP3 PLLA1.8V PLLA1.8V A3.3V D1.8V D3.3V1.5k 0.1uF 2.2k (2) 2.2k (2) PLL_F PWDN D3.3V BIN_2 RIN_2 GIN_2 GIN_4 49.9 (3) TVP7000 TP1 TEST TP1 EXT_CLK

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TVP7000PZP ACTIVE HTQFP PZP 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TVP7000PZPR ACTIVE HTQFP PZP 100 1000 TBD CU NIPDAU Level-4-220C-72 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2005 Addendum-Page 1

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