TVP5151IPBSR

TVP5151 TI | Alldatasheet

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www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 Ultralow-PowerNTSC/PAL/SECAM Video Decoder Check forSamples: TVP5151

1 Introduction

1.1 Features

• Accepts NTSC (J,M, 4.43),PAL (B,D, G, H, I, • Standard Programmable Video Output Formats M, N, Nc),and SECAM (B,D, G, K, K1, L)Video – ITU-R BT.656,8-Bit4:2:2With Embedded
• Supports ITU-R BT.601 Standard Sampling Syncs
• High-Speed 9-BitAnalog-to-DigitalConverter – 8-Bit4:2:2With DiscreteSyncs (ADC) • Macrovision™ Copy ProtectionDetection
• Two Composite Inputsor One S-VideoInput • Advanced Programmable Video Output
• FullyDifferentialCMOS Analog Preprocessing Formats Channels With Clamping and Automatic Gain – 2× Oversampled Raw VerticalBlanking Control(AGC) forBest Signal-to-Noise(S/N) Interval(VBI)Data During ActiveVideo Performance – SlicedVBI Data During HorizontalBlanking
• UltralowPower Consumption or ActiveVideo
• 48-TerminalPBGA Package (ZQC) or • VBI Modes Supported 32-TerminalTQFP Package (PBS) – Teletext(NABTS, WST)
• Power-Down Mode: <1 mW – Closed-CaptionDecode With FIFO and
• Brightness,Saturation,Hue, and Sharpness Extended Data Services(XDS) ControlThrough I2C – Wide Screen Signaling,Video Program
• Complementary 4-Line(3-HDelay)Adaptive System, CGMS-A, VerticalIntervalTime Comb FiltersforBoth Cross-Luminance and Code Cross-Chrominance Noise Reduction – Gemstar 1x/2xElectronicProgram Guide
• PatentedArchitectureforLocking toWeak, Compatible Mode Noisy,or UnstableSignals – Custom ConfigurationMode That Allows
• Single27.000-MHz CrystalforAllStandards User toProgram SliceEngine forUnique VBI
• InternalPhase-Locked Loop (PLL)for Data Signals Line-LockedClock and Sampling • Power-On Reset
• SubcarrierGenlock Output forSynchronizing • IndustrialTemperature Range ColorSubcarrierofExternalEncoder (TVP5151I):–40°C to85°C
• VariableDigitalI/OSupply VoltageRange from 1.8V to3.3V

1.2 Description

The TVP5151 deviceisan ultralow-powerNTSC/PAL/SECAM videodecoder.Availableina space-saving 48-terminalPBGA package ora 32-terminalTQFP package,theTVP5151 decoderconvertsNTSC, PAL, and SECAM videosignalsto8-bitITU-R BT.656 format.Discretesyncsarealsoavailable.The optimized architectureof the TVP5151 decoder allowsforultralowpower consumption.The decoder consumes 138-mW power under typicaloperatingconditionsand consumes lessthan1 mW inpower-down mode, considerablyincreasingbatterylifein portableapplications.The decoder uses justone crystalforall supportedstandards.The TVP5151 decodercan be programmed usingan I2C serialinterface. The TVP5151 decoder convertsbaseband analog video intodigitalYCbCr 4:2:2component video. Composite and S-videoinputsare supported.The TVP5151 decoderincludesone 9-bitanalog-to-digital converter(ADC) with2× sampling.SamplingisITU-R BT.601 (27.0MHz, generatedfromthe27.000-MHz crystaloroscillatorinput)and islinelocked.The outputformatscan be 8-bit4:2:2or8-bitITU-R BT.656 withembedded synchronization. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas of publicationdate. Copyright© 2009–2011,Texas InstrumentsIncorporatedProducts conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com The TVP5151 decoder utilizesTexas Instrumentspatentedtechnologyforlockingto weak, noisy,or unstablesignals.A Genlock/real-timecontrol(RTC) outputisgeneratedforsynchronizingdownstream videoencoders. Complementary four-lineadaptivecomb filteringisavailableforboththeluminanceand chrominancedata pathsto reduce both cross-luminanceand cross-chrominanceartifacts;a chrominancetrapfilterisalso available. Videocharacteristicsincludinghue,brightness,saturation,and sharpnessmay be programmed usingthe industrystandardI2C serialinterface.The TVP5151 decoder generatessynchronization,blanking,lock, and clocksignalsin additionto digitalvideo outputs.The TVP5151 decoder includesmethods for advanced verticalblankinginterval(VBI)data retrieval.The VBI data processorslices,parses,and performserrorcheckingon teletext,closedcaption,and otherdatainseveralformats. The TVP5151 decoderdetectscopy-protectedinputsignalsaccordingtotheMacrovision™ standardand detectsType 1,2,3,and colorstripeprocesses. The main blocksoftheTVP5151 decoderinclude:

• Robustsyncdetector
• ADC withanalogprocessor
• Y/C separationusingfour-lineadaptivecomb filter
• Chrominanceprocessor
• Luminance processor
• Videoclock/timingprocessorand power-down control
• Outputformatter
• I2C interface
• VBI dataprocessor
• Macrovisiondetectionforcompositeand S-video

1.3 Applications

The followingisa partiallistofsuggestedapplications:

• Digitaltelevisions
• PDAs
• NotebookPCs
• Cellphones
• Videorecorder/players
• Internetappliances/webpads
• Handheldgames
• Surveillance
• Portablenavigation
• Portablevideoprojectors

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1.4 RelatedProducts

• TVP5150AM1
• TVP5154A
• TVP5146M2
• TVP5147M1
• TVP5158

1.5 Trademarks

TIand MicroStarJunioraretrademarksofTexas Instruments. Macrovisionisa trademarkofMacrovisionCorporation. Gemstar isa trademarkofGemstar-TV Guide International. Othertrademarksarethepropertyoftheirrespectiveowners.

1.6 Document Conventions

Throughoutthisdatamanual,severalconventionsareused toconveyinformation.These conventionsare:

• To identifya binarynumber orfield,a lowercase b followsthenumbers.For example,000b isa 3-bit binaryfield.
• To identifya hexadecimalnumber orfield,a lowercase h followsthenumbers.Forexample,8AFh isa 12-bithexadecimalfield.
• Allothernumbers thatappear inthisdocument thatdo nothave eithera b or h followingthenumber areassumed tobe decimalformat.
• Ifthesignalor terminalname has a bar above thename (forexample,RESETB), thisindicatesthe logicalNOT function.When asserted,thissignalisa logiclow,0,or0b.
• RSVD indicatesthatthereferenceditemisreserved.

1.7 OrderingInformation

TA PACKAGED DEVICES (1)(2) PACKAGE OPTION TVP5151PBS Tray TVP5151PBSR Tape and reel 0°C to70°C TVP5151ZQC Tray TVP5151ZQCR Tape and reel TVP5151IPBS Tray –40°C to85°C TVP5151IPBSR Tape and reel (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTIweb siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging. Copyright© 2009–2011,Texas InstrumentsIncorporated Introduction 3 SubmitDocumentationFeedback

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M U X AIP1A AIP1B PGA A/D OutputFormatterYOUT[7:0] YCbCr 8-Bit 4:2:2 VBI Data Processor (VDP) Embedded Processor XTAL1/OSC XTAL2 SCLK Horizontal and Color PLLs FID/GLCO VSYNC/PALI INTREQ/GPCL/VBLK HSYNC Timing Processor SCL SDA Y/C SeparationChrominance Processing Luminance Processing Macrovision Detection Host Interface AVID/CLK_IN PDN TVP5151 www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011

2 Device Details

2.1 FunctionalBlock Diagram

Figure2-1.FunctionalBlock Diagram Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceDetails 5 SubmitDocumentationFeedback

A B C D E F G 1 2 3 4 5 6 7 PBGA (ZQC) PACKAGE (BOTTOM VIEW) TQFP (PBS) PACKAGE (TOP VIEW) 31 30 29 28 27 SCLK IO_D VDD Y OUT7/I2CSEL Y OUT6 Y OUT5 Y OUT4 Y OUT3 Y OUT2 CH_A VDD CH_AGND REFM REFP PDN INTREQ/GPCL/VBLK A VID/CLK_IN HSYNC 32 26 25 VSYNC/P ALI FID/GLCO SDA SCL D VDD DGND Y OUT0 Y OUT1 AIP1A AIP1B PLL_AGND PLL_A VDD XT AL1/OSC XT AL2 AGND RESETB 10 1 1 12 13 149 15 16 TVP5151 SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com

2.2 TerminalAssignments

The TVP5151 video decoder is packaged in a 48-terminalPBGA package or a 32-terminalTQFP package.Figure2-2shows theterminaldiagramsforbothpackages.Table2-1givesa descriptionofthe terminals. Figure2-2.TerminalDiagrams

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2.3 TerminalFunctions

Table2-1.TerminalFunctions TERMINAL NO. I/O DESCRIPTION NAME ZQC PBS Analog Section AGND E1 7 G Substrate.Connecttoanalogground. Analoginput.Connecttothevideoanaloginputvia0.1-µF capacitor.The maximum input AIP1A A1 1 I rangeis0-0.75VPP ,and may requirean attenuatortoreducetheinputamplitudetothe desiredlevel.Ifnotused,connecttoAGND viaa 0.1-µF capacitor(seeFigure6-1). Analoginput.Connecttothevideoanaloginputvia0.1-µF capacitor.The maximum input AIP1B B1 2 I rangeis0-0.75VPP ,and may requirean attenuatortoreducetheinputamplitudetothe desiredlevel.Ifnotused,connecttoAGND viaa 0.1-µF capacitor(seeFigure6-1). CH_AGND A3 31 G Analogground CH_AVDD A2 32 P Analogsupply.Connectto1.8-Vanalogsupply. B2,B3, B6,C4, C5,NC – – No connectD3 –D6, E2–E5, F2,F5,F6 PLL_AGND C2 3 G PLL ground.Connecttoanalogground. PLL_AVDD C1 4 P PLL supply.Connectto1.8-Vanalogsupply. A/D referencenegativeoutput.Connecttoanaloggroundthrougha 1-µF capacitor.Also,itREFM A4 30 O isrecommended toconnectdirectlytoREFP througha 1-µF capacitor(seeFigure6-1). A/D referencepositiveoutput.Connecttoanaloggroundthrougha 1-µF capacitor(seeREFP B4 29 O Figure6-1). Externalclockreferenceinput.Connecttoanaloggroundifan externalsingle-endedXTAL1/OSC D2 5 I oscillatorisconnectedtoAVID/CLK_IN pin. Externalclockreferenceoutput.Not connectedifXTAL1 orCLK_IN isdrivenby an externalXTAL2 D1 6 O single-endedoscillator. DigitalSection Activevideoindicatoroutput/externalclkinput When XTAL1 is used as a referenceclockand thisterminalis leftunconnected,this terminalisinternallypulleddown. When XTAL1 isused as a referenceclockand AVID outputisrequired,thispinmust beAVID/CLK_IN A6 26 I/O low untilterminalisconfiguredas an output.Thismay be dependenton externalcircuitry connectedtothisterminal. When XTAL 1 is connected to ground, CLK_IN may be connected to an external single-endedoscillatorfrom a 1.8-V to 3.3-V compatibleclock signaldepending on IO_DVDD voltage. DGND E6 19 G Digitalground DVDD E7 20 P Digitalsupply.Connectto1.8-Vdigitalsupply. FID:Odd/even fieldindicatororverticallockindicator.Fortheodd/evenindicator,a 1 indicatestheodd field. FID/GLCO C6 23 O GLCO: ThisserialoutputcarriescolorPLL information.A slavedevicecan decode the informationtoallowchrominancefrequencycontrolfromtheTVP5151 decoder.Data is transmittedattheSCLK rateinGenlockmode. InRTC mode, SCLK/4 isused. HSYNC A7 25 O Horizontalsynchronizationsignal Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceDetails 7 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com Table2-1.TerminalFunctions(continued) TERMINAL NO. I/O DESCRIPTION NAME ZQC PBS Thisterminalhas threefunctionsselectableby bit7 of I2C register03h and bit1 of I2C register0Fh:

• INTREQ: Interruptrequestoutput
• GPCL: General-purposecontrollogicoutput.Inthismode, thestateofterminal27 isINTREQ/ B5 27 O directlyprogrammed viaI2C.GPCL/VBLK
• VBLK: Verticalblankingoutput.Inthismode, terminal27 indicatestheverticalblanking intervaloftheoutputvideo.The beginningand end timesofthissignalare programmableviaI2C. An externalpulluporpulldownresistorisrequiredundercertainconditions(seeFigure6-1). IO_DVDD G2 10 P Digitaloutputsupply,1.8V to3.3V SCLK G1 9 O System clockat2x thefrequencyofthepixelclock. Power-down terminal(activelow).Putsthedecoderinstandbymode. PreservesthevaluePDN A5 28 I oftheregisters. Active-lowreset.RESETB can be used onlywhen PDN = 1.When RESETB ispulledlow,itRESETB F1 8 I resetsalltheregistersand restartstheinternalmicroprocessor. SCL D7 21 I/O I2C serialclock(opendrain) SDA C7 22 I/O I2C serialdata(opendrain) VSYNC: Verticalsynchronizationsignal PALI:PAL lineindicatororhorizontallockindicator.ForthePAL lineindicator:VSYNC/PALI B7 24 O 1 = Noninvertedline 0 = Invertedline G3 12 F4 13 G4 14 YOUT[6:0] G5 15 O ITU-R BT.656 output/YCbCr4:2:2outputwithdiscretesyncs G6 16 G7 17 F7 18 I2CSEL:DeterminesaddressforI2C (sampledduringreset).A pulluporpulldownresistoris needed (>1 kΩ)toprogramtheterminaltothedesiredaddress. 1 = AddressisBAhYOUT7/I2CSEL F3 11 I/O 0 = AddressisB8h YOUT7: Most significantbit(MSB) ofITU-R BT.656 output/YCbCr4:2:2output

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3 FunctionalDescription

3.1 Analog FrontEnd

The TVP5151 decoder has an analoginputchannelthatacceptstwo videoinputsthatare ac-coupled. The decodersupportsa maximum inputvoltagerange of0.75V; therefore,an attenuationofone-halfis needed formost inputsignalswitha peak-to-peakvariationof 1.5 V. The nominalparalleltermination beforetheinputtothedeviceisrecommended tobe 75 Ω.See theapplicationdiagraminFigure6-1for therecommended configuration.The two analoginputportscan be connectedas follows:

• Two selectablecompositevideoinputs,or
• One S-videoinput An internalclampingcircuitrestoresthesync-tipoftheac-coupledvideosignaltoa fixeddc level. The programmablegainamplifier(PGA) and theautomaticgaincontrol(AGC) algorithmwork togetherto make surethattheinputsignalisamplifiedsufficientlytoensuretheproperinputrangefortheADC. The ADC has ninebitsofresolutionand runsata nominalspeed of27 MHz. The clockinputfortheADC comes fromthehorizontalPLL.

3.2 Composite ProcessingBlock Diagram

The compositeprocessingblockprocessesNTSC/PAL/SECAM signalsintothe YCbCr colorspace. Figure3-1shows thebasicarchitectureofthisprocessingblock. Figure3-1 shows the luminance/chrominance(Y/C)separationprocessin the TVP5151 decoder.The compositevideoismultipliedby subcarriersignalsin the quadraturemodulatorto generatethe color differencesignalsCb and Cr.Cb and Cr arethenlow pass (LP)filteredtoachievethedesiredbandwidth and toreducecrosstalk. An adaptivefour-linecomb filterseparatesCbCr from Y. Chrominance isremodulatedthroughanother quadraturemodulatorand subtractedfrom the line-delayedcompositevideo to generateluminance. Brightness,hue,saturation,and sharpness(usingthepeakingfilter)areprogrammableviaI2C. The Y/C separationisbypassedforS-videoinput.ForS-video,theremodulationpathisdisabled. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 9 SubmitDocumentationFeedback

LPF ↓ 2 4-Line Adaptive Comb Filter Burst Accumulator (Cr) Notch Filter LP Filter LP Filter Delay Brightness Saturation Adjust Delay Cr Y Cb Cb Cr Y Burst Accumulator (Cb) Delay Color LPF ↓ 2Composite +Delay X Gain Factor BandpassPeak Detector Composite SECAM Color Demodulation Composite Cr Cb SECAM Luminance TVP5151 SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com Figure3-1.Composite ProcessingBlock Diagram (Comb/Trap FilterBypassed forSECAM)

3.3 AdaptiveComb Filtering

The four-linecomb filtercan be selectivelybypassed intheluminanceor chrominancepath.Ifthecomb filteris bypassed in the luminancepath,then chrominancetrapfiltersare used which are shown in Figure3-2and Figure3-3.TI'spatentedadaptivefour-linecomb filteralgorithmreducesartifactssuch as hanging dots at colorboundariesand detectsand properlyhandles falsecolorsin high-frequency luminanceimages such as a multiburstpatternorcirclepattern.

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www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 Figure3-2.Chrominance Trap FilterFrequency Figure3-3.Chrominance Trap FilterFrequency Response, NTSC ITU-R BT.601 Sampling Response, PAL ITU-R BT.601 Sampling

3.4 ColorLow-Pass Filter

Insome applications,itisdesirabletolimittheCb/Cr bandwidthtoavoidcrosstalk.Thisisespeciallytrue incase ofvideosignalsthathave asymmetricalCb/Cr sidebands.The colorLP filtersprovidedlimitthe bandwidthoftheCb/Crsignals. ColorLP filtersareneeded when thecomb filteringturnsoff,due toextremecolortransitionsintheinput image.See Section3.21.25,Chrominance Control#2 Register,fortheresponseofthesefilters.The filters have three optionsthat allow three differentfrequencyresponses based on the colorfrequency characteristicsoftheinputvideoas shown inFigure3-4. Figure3-4.ColorLow-Pass FilterwithFilterCharacteristics,NTSC/PAL ITU-R BT.601 Sampling Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 11 SubmitDocumentationFeedback

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3.5 Luminance Processing

The luminance component is derivedfrom the composite signalby subtractingthe remodulated chrominanceinformation.A linedelayexistsinthispathtocompensate forthelinedelayintheadaptive comb filterinthecolorprocessingchain.The luminanceinformationisthenfedintothepeakingcircuit, whichenhances thehighfrequencycomponents ofthesignal,thusimprovingsharpness.

3.6 Chrominance Processing

For NTSC/PAL formats,the colorprocessingbeginswitha quadraturedemodulator.The Cb/Cr signals thenpass throughthegaincontrolstageforchrominancesaturationadjustment.An adaptivecomb filteris appliedto the demodulatedsignalsto separatechrominanceand eliminatecross-chrominanceartifacts. An automaticcolorkillercircuitisalsoincludedinthisblock.The colorkillersuppressesthechrominance processingwhen theburstamplitudefallsbelowa programmablethreshold(seeI2C subaddress06h).The SECAM standardissimilartoPAL exceptforthemodulationofcolorwhichisFM insteadofQAM.

3.7 Timing Processor

The timingprocessorisa combinationof hardware and softwarerunninginthe internalmicroprocessor thatservesto controlhorizontallockto the inputsync pulseedge, AGC and offsetadjustmentin the analogfrontend,verticalsyncdetection,and Macrovisiondetection.

3.8 VBI Data Processor (VDP)

The TVP5151 VDP slicesvariousdataservicessuch as teletext(WST, NABTS), closedcaptioning(CC), wide screen signaling(WSS), etc.These servicesare acquiredby programming the VDP to enable standardsintheVBI.The resultsarestoredina FIFO and/orregisters.The teletextresultsarestoredonly ina FIFO.Table3-1listsa summary ofthetypesofVBI datasupportedaccordingtothevideostandard.It supportsITU-R BT. 601 samplingforeach. Table3-1.Data Types Supported by VDP LINE MODE REGISTER NAME DESCRIPTION(D0h–FCh) BITS [3:0] 0000b WST SECAM Teletext,SECAM 0001b WST PAL B Teletext,PAL, System B 0010b WST PAL C Teletext,PAL, System C 0011b WST, NTSC B Teletext,NTSC, System B 0100b NABTS, NTSC C Teletext,NTSC, System C 0101b NABTS, NTSC D Teletext,NTSC, System D (Japan) 0110b CC, PAL ClosedcaptionPAL 0111b CC, NTSC ClosedcaptionNTSC 1000b WSS/CGMS-A Wide-screensignaling/CopyGenerationManagement System-Analog,PAL 1001b WSS/CGMS-A Wide-screensignaling/CopyGenerationManagement System-Analog,NTSC 1010b VITC,PAL Verticalintervaltimecode,PAL 1011b VITC,NTSC Verticalintervaltimecode,NTSC 1100b VPS, PAL Videoprogramsystem,PAL 1101b Gemstar 2x Custom 1 Electronicprogramguide 1110b Reserved Reserved 1111b ActiveVideo Activevideo/fullfield

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www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 At power-upthehostinterfaceisrequiredtoprogram theVDP-configurationRAM (VDP-CRAM) contents withthelookuptable(seeSection3.21.64).Thisisdone throughportaddressC3h. Each read from or writeto thisaddress auto incrementsan internalcounterto the next RAM location.To access the VDP-CRAM, thelinemode registers(D0h toFCh) must be programmed withFFh toavoida conflictwith the internalmicroprocessorand the VDP in both writingand reading.Fullfieldmode must also be disabled. AvailableVBI linesarefromline6 toline27 ofbothfield1 and field2.Each linecan be any VBI mode. OutputdataisavailableeitherthroughtheVBI-FIFO (B0h)or throughdedicatedregistersat90h toAFh, bothofwhichareavailablethroughtheI2C port.

3.9 VBI FIFO and AncillaryData inVideo Stream

SlicedVBI datacan be outputas ancillarydatainthevideostreamintheITU-R BT.656 mode. VBI datais outputduringthehorizontalblankingperiodfollowingthelinefromwhichthedatawas retrieved.Table3-2 shows theheaderformatand sequence oftheancillarydatainsertedintothevideostream.Thisformatis alsoused tostoreany VBI dataintotheFIFO. The sizeofFIFO is512 bytes.Therefore,theFIFO can storeup to11 linesofteletextdatawiththeNTSC NABTS standard. Table3-2.AncillaryData Format and Sequence D7 D0BYTE NO. D6 D5 D4 D3 D2 D1 DESCRIPTION(MSB) (LSB) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Ancillarydatapreamble 2 1 1 1 1 1 1 1 1

3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID)

4 NEP EP F5 F4 F3 F2 F1 F0 SecondarydataID (SDID)

5 NEP EP N5 N4 N3 N2 N1 N0 Number of32-bitdata(NN)

6 Videoline[7:0] InternaldataID0 (IDID0)

Data7 0 0 0 Match 1 Match 2 Videoline[9:8] InternaldataID1 (IDID1)error 8 1.Data Data byte 9 2.Data Data byte Firstword 10 3.Data Data byte 11 4.Data Data byte m –1.Data Data byte m. Data Data byte N thword RSVD CS[5:0] Check sum 4(N+2)–1 1 0 0 0 0 0 0 0 Fillbyte EP: Even parityforD0 –D5 NEP: Negated even parity DID: 91h:SliceddataofVBI linesoffirstfield 53h:Sliceddataofline24 toend offirstfield 55h:SliceddataofVBI linesofsecond field 97h:Sliceddataofline24 toend ofsecond field SDID: Thisfieldholdsthedataformattakenfromthelinemode registerofthecorrespondingline. NN: Number ofDwords beginningwithbyte8 through4(N+2).Thisvalueisthenumber of Dwords where each Dword is4 bytes. IDID0: Transactionvideolinenumber [7:0] Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 13 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com IDID1: Bit0/1= Transactionvideolinenumber [9:8] Bit2 = Match 2 flag Bit3 = Match 1 flag Bit4 = 1 ifan errorwas detectedintheEDC block;0 ifnot CS: Sum ofD0 –D7 ofDID throughlastdatabyte. Fillbyte: Fillbytesmake a multipleof4 bytesfrombyte0 tolastfillbyte.

3.10 Raw Video Data Output

The TVP5151 decodercan outputraw A/D videodataat2x samplingrateforexternalVBI slicing.Thisis transmittedas an ancillarydata blockduringthe activehorizontalportionof the lineand duringvertical blanking.

3.11 Output Formatter

The YCbCr digitaloutputcan be programmed as 8-bit4:2:2or 8-bitITU-R BT.656 parallelinterface standard. Table3-3.Summary ofLineFrequencies,Data Rates,and PixelCounts COLORACTIVE PIXEL HORIZONTALSTANDARDS PIXELS PER LINES PER SUB-CARRIERPIXELS PER FREQUENCY LINE RATE(ITU-RBT.601) LINE FRAME FREQUENCYLINE (MHz) (kHz)(MHz) NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426 PAL-M 858 720 525 13.5 3.57561149 15.73426 PAL-B,D, G, H, I 864 720 625 13.5 4.43361875 15.625 PAL-N 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625 SECAM 864 720 625 13.5 4.40625/4.25 15.625

3.12 SynchronizationSignals

External(discrete)syncsareprovidedviathefollowingsignals(seeFigure3-5and Figure3-6):

• VSYNC (verticalsync)
• FID/VLK (fieldindicatororverticallockindicator)
• INTREQ/GPCL/VBLK (general-purposeoutputorverticalblankingindicator)
• PALI/HLK (PAL switchindicatororhorizontallockindicator)
• HSYNC (horizontalsync)
• AVID (activevideoindicator)(ifsetas output) VSYNC, FID,PALI,and VBLK are softwaresetand programmable totheSCLK pixelcount.Thisallows any possiblealignmenttotheinternalpixelcountand linecount.The defaultsettingsfora 525-/625-line videooutputaregivenas an example.

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1 2 3 4 5 6 7 8 9 10 11 20 21 22

525 Line

262 263 264 265 266 267 268 269 270 271 272 273 282 283 284 310 311 312 313 314 315 316 317 318 319 320 333 334 335 336 622 623 624 625 1 2 3 4 5 6 7 20 21 22 23

625 Line

www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 A. LinenumberingconformstoITU-R BT.470 and ITU-R BT.1700. Figure3-5.8-Bit4:2:2,Timing With 2× PixelClock (SCLK) Reference Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 15 SubmitDocumentationFeedback

Y 718 1438 1438 Cr 359 1439 1439 Y 719 1440 1440 FF 1441 1441 1455 1459 1456 1460 HSYNC AVID ITU-R BT.656 Timing 1583 1587 1584 1588 1711 1723 1712 1724 FF 1713 1725 1714 1726 1715 1727 XX Cb Y Cr Y AVID Stop AVID Start HSYNC Start SECAM 1436 1437 1438 1439 1440 1441 1479 1480 1607 1608 1719 1720 1721 1722 1723 17 TVP5151 SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com A. AVID risingedge occursfourSCLK cyclesearlywhen intheITU-R BT.656 outputmode. Figure3-6.HorizontalSynchronizationSignals

3.13 ActiveVideo (AVID)Cropping

The AVID outputsignalprovidesa means toqualifyand cropactivevideobothhorizontallyand vertically. The horizontalstartand stop positionof the AVID signalis controlledusing registers11h-12h and 13h-14h,respectively.These registersalsocontrolthehorizontalpositionoftheembedded syncSAV/EAV codes. AVID verticaltimingiscontrolledby theVBLK startand stopregistersataddresses18h and 19h.These VBLK registershave no effecton the embedded verticalsync code timing.Figure3-7 shows an AVID application. NOTE The above settingsalterAVID outputtiming,butthevideooutputdataisnotforcedtoblack leveloutsideoftheAVID interval.

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www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 Figure3-7.AVID Application

3.14 Embedded Syncs

Standardswithembedded syncsinsertSAV and EAV codes intothedatastreamatthebeginningand end of horizontalblanking.These codes containthe V and F bitsthatalsodefineverticaltiming.F and V change on EAV. Table3-4givestheformatoftheSAV and EAV codes. H equals1 alwaysindicatesEAV. H equals0 alwaysindicatesSAV. The alignmentofV and F totheline and fieldcountervariesdependingon thestandard.See ITU-R BT.656 formore informationon embedded syncs. The P bitsareprotectionbits: P3 = V xorH P2 = F xorH P1 = F xorV P0 = F xorV xorH Table3-4.EAV and SAV Sequence 8-BITDATA D7 (MSB) D6 D5 D4 D3 D2 D1 D0 Preamble 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 Statusword 1 F V H P3 P2 P1 P0 Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 17 SubmitDocumentationFeedback

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3.15 I2C Host Interface

The I2C standardconsistsof two signals,serialinput/outputdata line(SDA) and input/outputclockline (SCL),whichcarryinformationbetween thedevicesconnectedtothebus.A thirdsignal(I2CSEL)isused forslave address selection.Althoughthe I2C system can be multimastered,the TVP5151 decoder functionsonlyas a slavedevice. Both SDA and SCL must be connectedtoa positivesupplyvoltageviaa pullupresistor.When thebus is free,both linesare high.The slaveaddressselectterminal(I2CSEL)enablesthe use of two TVP5151 decoderstiedtothesame I2C bus.At power up,thestatusoftheI2CSEL ispolled.Depending on the writeand readaddressestobe used fortheTVP5151 decoder,itcan eitherbe pulledlow orhighthrough a resistor.This terminalismultiplexedwithYOUT7 and hence must not be tieddirectlyto ground or IO_DVDD. Table3-6summarizestheterminalfunctionsoftheI2C-mode hostinterface. Table3-5.WriteAddress Selection I2CSEL WRITE ADDRESS

0 B8h

1 BAh

Table3-6.I2C TerminalDescription SIGNAL TYPE DESCRIPTION I2CSEL (YOUT7) I Slaveaddressselection SCL I/O(opendrain) Input/outputclockline SDA I/O(opendrain) Input/outputdataline Data transferrateon the bus isup to 400 kbit/s.The number of interfacesconnectedto the bus is dependenton thebus capacitancelimitof400 pF. The dataon theSDA linemust be stableduringthe highperiodoftheSCL exceptforstartand stopconditions.The highorlow stateofthedatalinecan only change withtheclocksignalon theSCL linebeinglow.A high-to-lowtransitionon theSDA linewhilethe SCL ishighindicatesan I2C startcondition.A low-to-hightransitionon theSDA linewhiletheSCL ishigh indicatesan I2C stopcondition. Every byteplacedon theSDA must be eightbitslong.The number ofbyteswhich can be transferredis unrestricted.Each bytemust be followedby an acknowledgebit.The acknowledge-relatedclockpulseis generatedby theI2C master.

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3.15.1 I2C WriteOperation

Data transfersoccurutilizingthefollowingillustratedformats. An I2C master initiatesa writeoperationto the TVP5151 decoder by generatinga startcondition(S) followedby theTVP5151 I2C slaveaddress(seethefollowingillustration),inMSB firstbitorder,followed by a 0 toindicatea writecycle.Afterreceivingan acknowledgefrom theTVP5151 decoder,themaster presentsthesubaddressoftheregister,orthefirstofa blockofregistersitwantstowrite,followedby one ormore bytesofdata,MSB first.The TVP5151 decoderacknowledgeseach byteaftercompletionofeach transfer.The I2C masterterminatesthewriteoperationby generatinga stopcondition(P). Step 1 0 I2C Start(master) S Step 2 7 6 5 4 3 2 1 0 I2C slaveaddress(master) 1 0 1 1 1 0 X 0 Step 3 9 I2C Acknowledge(slave) A Step 4 7 6 5 4 3 2 1 0 I2C Writeregisteraddress(master) Addr Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge(slave) A Step 6 7 6 5 4 3 2 1 0 I2C Writedata(master) Data Data Data Data Data Data Data Data 9Step 7(1) I2C Acknowledge(slave) A Step 8 0 I2C Stop(master) P (1) Repeat steps6 and 7 untilalldatahave been written.

3.15.2 I2C Read Operation

The read operationconsistsoftwo phases.The firstphase istheaddressphase.Inthisphase,an I2C masterinitiatesa writeoperationtotheTVP5151 decoderby generatinga startcondition(S)followedby the TVP5151 I2C slaveaddress,inMSB firstbitorder,followedby a 0 to indicatea writecycle.After receivingan acknowledgefromtheTVP5151 decoder,themasterpresentsthesubaddressoftheregister orthefirstofa blockofregistersitwants toread.Afterthecycleisacknowledged,themasterterminates thecycleimmediatelyby generatinga stopcondition(P). Table3-7.Read Address Selection I2CSEL READ ADDRESS

0 B9h

1 BBh

The second phase isthe data phase. In thisphase, an I2C master initiatesa read operationto the TVP5151 decoder by generatinga startconditionfollowedby the TVP5151 I2C slaveaddress(see the followingillustrationofa read operation),inMSB firstbitorder,followedby a 1 toindicatea read cycle. Afteran acknowledgefromtheTVP5151 decoder,theI2C masterreceivesone ormore bytesofdatafrom theTVP5151 decoder.The I2C masteracknowledgesthetransferattheend ofeach byte.Afterthelast databytedesiredhas been transferredfromtheTVP5151 decodertothemaster,themastergeneratesa notacknowledgefollowedby a stop. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 19 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com 3.15.2.1Read Phase 1 Step 1 0 I2C Start(master) S Step 2 7 6 5 4 3 2 1 0 I2C slaveaddress(master) 1 0 1 1 1 0 X 0 Step 3 9 I2C Acknowledge(slave) A Step 4 7 6 5 4 3 2 1 0 I2C Writeregisteraddress(master) Addr Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge(slave) A Step 6 0 I2C Stop(master) P 3.15.2.2Read Phase 2 Step 7 0 I2C Start(master) S Step 8 7 6 5 4 3 2 1 0 I2C slaveaddress(master) 1 0 1 1 1 0 X 1 Step 9 9 I2C Acknowledge(slave) A Step 10 7 6 5 4 3 2 1 0 I2C Read data(slave) Data Data Data Data Data Data Data Data 9Step 11(1) I2C Not Acknowledge(master) A Step 12 0 I2C Stop(master) P (1) Repeat steps10 and 11 forallbytesread.Masterdoes notacknowledgethelastreaddatareceived.

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27.000-MHz Crystal C CL2 XTAL2 R TVP5151 CLK_IN NC IO_DVDD XTAL1/OSC XTAL2 TVP5151 CLK_IN NC IO_DVDD 1.8 V to 3.3 V 27.000-MHz 1.8-V Clock XTAL1/OSC XTAL2 TVP5151 CLK_IN IO_DVDD 27.000-MHz 1.8-V to 3.3-V Clock NC NC 1.8 V to 3.3 V 1.8 V to 3.3 V TVP5151 www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 3.15.2.3I2C Timing Requirements The TVP5151 decoderrequiresdelaysintheI2C accessestoaccommodate itsinternalprocessor'stiming. InaccordancewithI2C specifications,theTVP5151 decoderholdstheI2C clockline(SCL) low toindicate thewaitperiodtotheI2C master.IftheI2C masterisnotdesignedtocheck fortheI2C clocklineheld-low condition,thenthemaximum delaysmust alwaysbe insertedwhere required.These delaysareofvariable length;maximum delaysareindicatedinthefollowingdiagram: Normal registerwritingaddresses00h to8Fh (addresses90h toFFh do notrequiredelays). Slave Start address Ack Subaddress Ack Data (XXh) Ack Wait64 µs Stop (B8h) The 64-µs delayisforallregistersthatdo not requirea reinitialization.Delays may be more forsome registers.

3.16 Clock Circuits

An internalline-lockedPLL generatesthe system and pixelclocks.A 27.000-MHz clockisrequiredto drivethe PLL. This may be inputto the TVP5151 decoder on terminal5 (XTAL1),or a crystalof 27.000-MHz fundamentalresonantfrequencymay be connected across terminals5 and 6 (XTAL2). Figure 3-8 shows the referenceclock configurations.For the example crystalcircuitshown (a parallel-resonantcrystalwith27.000-MHz fundamentalfrequency),theexternalcapacitorsmust have the followingrelationship: C L1 = C L2 = 2C L – C STRAY where C STRAY istheterminalcapacitancewithrespecttoground,and C L isthecrystalloadcapacitance specifiedby thecrystalmanufacturer. Figure3-8shows thereferenceclockconfigurations. NOTE: The resistor(R)inparallelwiththecrystalisrecommended tosupporta widerangeofcrystaltypes.A 100-kΩ resistor may be used formost crystaltypes. Figure3-8.ReferenceClock Configurations An alternatemethod tosupplyan externalsourcewitha 1.8-Vto3.3-Vpeak-to-peaklevelistopullpin5 (XTAL1/OSC) low and connecta 1.8-Vto3.3-Vexternaloscillatorclocksourcetopin26,AVID/CLK_IN, dependingon what IO_DVDD supplyvoltageisused. Clocksourcefrequencyshouldhave an accuracyof±50 ppm (max). Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 21 SubmitDocumentationFeedback

128 SCLK

1 SCLK

7 SCLK23 SCLK

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3.17 Genlock Control(GLCO) and RTC

A Genlock controlfunctionisprovidedto supporta standardvideoencoder to synchronizeitsinternal coloroscillatorforproperlyreproducedcolorwithunstabletimebasesourcessuch as VCRs. The frequencycontrolword of the internalcolorsubcarrierdigitallytuned oscillator(DTO) and the subcarrierphase resetbitaretransmittedviaterminal23 (GLCO). The frequencycontrolword isa 23-bit binarynumber.The frequencyoftheDTO can be calculatedfromthefollowingequation: fdto = (fctrl/223)× fsclk where fdto isthefrequencyoftheDTO, fctrlisthe23-bitDTO frequencycontrol,and fsclkisthefrequencyof theSCLK.

3.17.1 GLCO Interface

A writeof1 tobit4 ofthechrominancecontrolregisteratI2C subaddress1Ah causes thesubcarrierDTO phase resetbittobe senton thenextscan lineon GLCO. The active-lowresetbitoccursseven SCLKs afterthetransmissionofthelastbitofDTO frequencycontrol.Upon thetransmissionoftheresetbit,the phase oftheTVP5151 internalsubcarrierDTO isresettozero. A Genlock slavedevicecan be connectedtotheGLCO terminaland uses theinformationon GLCO to synchronizeitsinternalcolorphase DTO toachievecleanlineand colorlock. Figure3-9shows thetimingdiagramoftheGLCO mode. Figure3-9.GLCO Timing

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M S B

16 CLK

L S B 21 0

128 CLK

22-Bit f Frequency Controlsc Start Bit Reset Bit

2 CLK

1 CLK

3 CLK

44 CLK

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3.17.2 RTC Mode

Figure3-10shows thetimingdiagramoftheRTC mode. ClockratefortheRTC mode isfourtimesslower thantheGLCO clockrate.For ColorPLL frequencycontrol,theupper 22 bitsare used.Each frequency controlbitistwo clockcycleslong.The active-lowresetbitoccurssixCLKs afterthetransmissionofthe lastbitofPLL frequencycontrol. Figure3-10.RTC Timing

3.18 Reset and Power Down

The RESETB and PDN terminalswork togethertoputtheTVP5151 decoderintoone ofthetwo modes. Table3-8shows theconfiguration. Afterpower-up,thedeviceisinan unknown statewithitsoutputsundefined,untilitreceivesa RESETB signalas depictedinFigure3-11.AfterRESETB isreleased,outputsSCLK and YOUT0 toYOUT7 arein high-impedancestateuntilTVP5151 isinitializedand theoutputsareactivated. NOTE I2C SCL and SDA signalsmust notchange stateuntiltheTVP5151 resetsequence has been completed. Table3-8.Reset and Power-Down Modes PDN RESETB CONFIGURATION 0 0 Reserved(unknown state) 0 1 Powers down thedecoder 1 0 Resetsthedecoder 1 1 Normal operation Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 23 SubmitDocumentationFeedback

PLL_A VDD DVDD IO_DVDD SDA PDN SCL Data TVP5151 SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com AfterRESETB isreleased,outputsSCLK and YOUT0 to YOUT7 are high-impedanceuntilthe chipis initializedand theoutputsareactivated. Figure3-11.Power-On Reset Timing Table3-9.Power-On Reset Timing NO. PARAMETER MIN MAX UNIT t1 Delaytimebetween power suppliesactiveand reset 20 ms t2 RESETB pulseduration 500 ns t3 Delaytimebetween end ofresettoI2C active 200 µs

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3.19 Reset Sequence

Table3-10shows theresetsequence oftheTVP5151 pinsstatusduringresettimeand immediatelyafter resettime. Table3-10.Reset Sequence IMMEDIATELY AFTERPIN DESCRIPTION DURING RESETB RESETB FID/GLCO, HSYNC, INTREQ/GPCL/VBLK, SCLK, VSYNC/PALI, YOUT[6:0] High-impedance High-impedance AIP1A,AIP1B,AVID/CLK_IN,RESETB, PDN, SDA, SCL, XTAL1/OSC Input Input XTAL2 Output Output YOUT7/I2CSEL Input High-impedance TVP5151 ispin compatiblewithTVP5150/A/AM1, and the followingdifferencesshouldbe considered when an upgradeisplanned.

• IO_DVDD supplycan be any voltagefrom1.8V to3.3V.
• AVID/CLK_IN isinputduringRESETB. Ifthisinputisused as theclocksource,XTAL1/OSC pinmust be grounded. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 25 SubmitDocumentationFeedback

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3.20 InternalControlRegisters

The TVP5151 decoderisinitializedand controlledby a setofinternalregistersthatsetalldeviceoperating parameters.Communication between the externalcontrollerand the TVP5151 decoder isthroughI2C. Table3-11 shows thesummary oftheseregisters.The reservedregistersmust notbe written.Reserved bitsinthedefinedregistersmust be writtenwithzeros,unlessotherwisenoted.The detailedprogramming informationofeach registerisdescribedinthefollowingsections. Table3-11.RegisterSummary REGISTER ADDRESS DEFAULT R/W (1) Videoinputsourceselection#1 00h 00h R/W Analogchannelcontrols 01h 15h R/W Operationmode controls 02h 00h R/W Miscellaneouscontrols 03h 00h R/W Autoswitchmask 04h DCh R/W Miscellaneousoutputcontrols 05h 00h R/W Colorkillerthresholdcontrol 06h 10h R/W Luminance processingcontrol#1 07h 60h R/W Luminance processingcontrol#2 08h 00h R/W Brightnesscontrol 09h 80h R/W Colorsaturationcontrol 0Ah 80h R/W Hue control 0Bh 00h R/W Reserved 0Ch Outputsand dataratesselect 0Dh 47h R/W Luminance processingcontrol#3 0Eh 00h R/W Configurationsharedpins 0Fh 00h R/W Reserved 10h ActivevideocroppingstartpixelMSB 11h 00h R/W ActivevideocroppingstartpixelLSB 12h 00h R/W ActivevideocroppingstoppixelMSB 13h 00h R/W ActivevideocroppingstoppixelLSB 14h 00h R/W Genlockand RTC 15h 01h R/W Horizontalsyncstart 16h 80h R/W Reserved 17h Verticalblankingstart 18h 00h R/W Verticalblankingstop 19h 00h R/W Chrominancecontrol#1 1Ah 0Ch R/W Chrominancecontrol#2 1Bh 14h R/W InterruptresetregisterB 1Ch 00h R/W InterruptenableregisterB 1Dh 00h R/W InterruptconfigurationregisterB 1Eh 00h R/W Reserved 1Fh-20h IndirectRegisterData 21h-22h 00h R/W IndirectRegisterAddress 23h 00h R/W IndirectRegisterRead/WriteStrobe 24h 00h R/W Reserved 25h-27h Videostandard 28h 00h R/W Reserved 29h–2Bh Cb gainfactor 2Ch R (1) R = Read only,W = Writeonly,R/W = Read and write

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www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 Table3-11.RegisterSummary (continued) REGISTER ADDRESS DEFAULT R/W (1) Cr gainfactor 2Dh R Macrovisionon counter 2Eh 0Fh R/W Macrovisionoffcounter 2Fh 01h R/W 656 revisionselect 30h 00h R/W Reserved 31h–7Dh PatchWriteAddress 7Eh 00h R/W (2) PatchCode Execute 7Fh 00h R/W (2) DeviceID MSB 80h 51h R DeviceID LSB 81h 51h R ROM version 82h 04h R RAM version 83h 00h R VerticallinecountMSB 84h R VerticallinecountLSB 85h R InterruptstatusregisterB 86h R InterruptactiveregisterB 87h R Statusregister#1 88h R Statusregister#2 89h R Statusregister#3 8Ah R Statusregister#4 8Bh R Statusregister#5 8Ch R Reserved 8Dh PatchRead Address 8Eh 00h R/W (2) Reserved 8Fh Closedcaptiondata 90h–93h R WSS data 94h–99h R VPS data 9Ah–A6h R VITC data A7h–AFh R VBI FIFO readdata B0h R Teletextfilterand mask 1 B1h–B5h 00h R/W Teletextfilterand mask 2 B6h–BAh 00h R/W Teletextfiltercontrol BBh 00h R/W Reserved BCh –BFh InterruptstatusregisterA C0h 00h R/W InterruptenableregisterA C1h 00h R/W InterruptconfigurationregisterA C2h 04h R/W VDP configurationRAM data C3h DCh R/W VDP configurationRAM addresslowbyte C4h 0Fh R/W VDP configurationRAM addresshighbyte C5h 00h R/W VDP status C6h R FIFO word count C7h R FIFO interruptthreshold C8h 80h R/W FIFO reset C9h 00h W Linenumber interrupt CAh 00h R/W PixelalignmentLSB CBh 4Eh R/W PixelalignmentHSB CCh 00h R/W FIFO outputcontrol CDh 01h R/W (2) These registersareused forfirmwarepatchcode and shouldnotbe writtentoorreadfromduring normaloperation. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 27 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com Table3-11.RegisterSummary (continued) REGISTER ADDRESS DEFAULT R/W (1) Reserved CEh Fullfieldenable CFh 00h R/W D0h 00hLinemode R/WD1h –FBh FFh Fullfieldmode FCh 7Fh R/W Reserved FDh –FFh

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3.21 RegisterDefinitions

3.21.1 Video InputSource Selection#1 Register

Reserved Blackoutput Reserved Channel1 S-video source selection selection Channel1 sourceselection 0 = AIP1A selected(default) 1 = AIP1B selected Table3-12.Analog Channel and Video Mode Selection ADDRESS 00 INPUT(S) SELECTED BIT 1 BIT 0 AIP1A (default) 0 0 Composite AIP1B 1 0 AIP1A (luminance),S-Video x 1AIP1B (chrominance) Blackoutput 0 = Normal operation(default) 1 = Forceblackscreenoutput(outputssynchronized) a.Forcedto10h innormalmode b.Forcedto01h inextendedmode

3.21.2 Analog Channel ControlsRegister

Reserved 1 0 1 Automaticgaincontrol Automaticgaincontrol(AGC) 00 = AGC disabled(fixedgainvalue) 01 = AGC enabled(default) 10 = Reserved 11 = AGC frozentothepreviouslysetvalue Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 29 SubmitDocumentationFeedback

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3.21.3 OperationMode ControlsRegister

Reserved Colorburst TV/VCR mode Composite Color Luminance Power-down reference peak disable subcarrierPLL peak disable mode enable frozen Colorburstreferenceenable 0 = ColorburstreferenceforAGC disabled(default) 1 = ColorburstreferenceforAGC enabled(notrecommended) TV/VCR mode 00 = Automaticmode determinedby theinternaldetectioncircuit(default) 01 = Reserved 10 = VCR (nonstandardvideo)mode 11 = TV (standardvideo)mode With automaticdetectionenabled,unstableor nonstandardsyncs on the inputvideo forcesthe detectorintotheVCR mode. Thisturnsoffthecomb filtersand turnson thechrominancetrapfilter. Compositepeak disable 0 = Compositepeak protectionenabled(default) 1 = Compositepeak protectiondisabled ColorsubcarrierPLL frozen 0 = ColorsubcarrierPLL incrementsby theinternallygeneratedphase increment(default).GLCO pin outputsthefrequencyincrement. 1 = ColorsubcarrierPLL stopsoperating.GLCO pinoutputsthefrozenfrequencyincrement. Luminance peak disable 0 = Luminance peak processingenabled(default) 1 = Luminance peak processingdisabled Power-down mode 0 = Normal operation(default) 1 = Power-down mode. A/Ds areturnedoffand internalclocksarereducedtominimum.

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3.21.4 MiscellaneousControlsRegister

VBLK/GPCL GPCL logic INTREQ/GPCL/ Lock status YCbCr output HSYNC, Vertical Clockoutput select level VBLK output (HVLK) enable VSYNC/PALI, blankingon/off enable enable (TVPOE) AVID, FID/GLCO outputenable VBLK/GPCL functionselect(affectsINTREQ/GPCL/VBLK outputonlyifbit1 ofI2C register0Fh issetto 0 = GPCL (default) 1 = VBLK GPCL logiclevel(affectsINTREQ/GPCL/VBLK outputonlyifbit7 issetto0 and bit5 issetto1) 0 = GPCL issettologic0 (default) 1 = GPCL issettologic1 INTREQ/GPCL/VBLK outputenable 0 = Outputdisabled(default) 1 = Outputenabled(recommended) Note:The INTREQ/GPCL/VBLK output(pin27) must neverbe leftfloating.An external10-kΩ pulldown resistorisrequiredwhen theINTREQ/GPCL/VBLK outputisdisabled(bit5 ofI2C register03h issetto0). Lock status(HVLK) (configuredalongwithregister0Fh,see Figure3-12fortherelationshipbetween the configurationsharedpins) 0 = TerminalVSYNC/PALI outputsthePAL indicator(PALI)signaland terminalFID/GLCO outputsthe fieldID (FID)signal(default)(ifterminalsareconfiguredtooutputPALI and FID inregister0Fh). 1 = TerminalVSYNC/PALI outputsthe horizontallockindicator(HLK) and terminalFID outputsthe verticallockindicator(VLK)(ifterminalsareconfiguredtooutputPALI and FID inregister0Fh). These areadditionalfunctionsthatareprovidedforease ofuse. YCbCr outputenable 0 = YOUT[7:0]highimpedance (default) 1 = YOUT[7:0]active Note:YOUT7 must be pulledhighorlowfordeviceI2C addressselect. HSYNC, VSYNC/PALI, activevideoindicator(AVID),and FID/GLCO outputenables 0 = HSYNC, VSYNC/PALI, AVID,and FID/GLCO arehigh-impedance(default). 1 = HSYNC, VSYNC/PALI, AVID,and FID/GLCO areactive. Note:Thiscontrolbithas no effecton the FID/GLCO outputwhen itisprogrammed to outputthe GLCO signal(seebit3 ofaddress0Fh).When theGLCO signalisselected,theFID/GLCO outputis alwaysactive. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 31 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com Verticalblankingon/off 0 = Verticalblanking(VBLK) off(default) 1 = Verticalblanking(VBLK) on Clockoutputenable 0 = SCLK outputishighimpedance (default) 1 = SCLK outputisenabled Note:To achievelowestpower consumption,outputsplacedinthehigh-impedancestateshouldnotbe leftfloating.A 10-kΩ pulldownresistorisrecommended ifnotdrivenexternally. Note:When enablingtheoutputs,ensuretheclockoutputisnotaccidentlydisabled. Table3-13.DigitalOutput Control(1) REGISTER 03h,BIT 3 REGISTER C2h, BIT 2 YCbCr OUTPUT NOTES(TVPOE) (VDPOE)

0 X Highimpedance AfterbothYCbCr outputenablebitsareprogrammed

X 0 Highimpedance AfterbothYCbCr outputenablebitsareprogrammed 1 1 Active AfterbothYCbCr outputenablebitsareprogrammed (1) VDPOE defaultis1,and TVPOE defaultis0.

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U X PALI 0 PALI/HLK/HVLK HLK/HVLK M U X VSYNC 0 VSYNC/PALI/HLK/HVLK 0F(Bit 2) VSYNC/PALI Pin 23 M U X VLK/HVLK 1 GLCO FID M U X FID/VLK/HVLK 0 FID/GLCO/VLK/HVLK 0F(Bit 3) FID/GLCO03(Bit 4) HVLK M U X HLK 0 1HVLK 0F(Bit 4) LOCK24B M U X HVLK 1 0VLK 0F(Bit 6) LOCK23 Pin 27 M U X VBLK 1 INTREQ GPCL M U X VBLK/GPCL 1 INTREQ/GPCL/VBLK 03(Bit 7) VBKO 0F(Bit 1) INTREQ/GPCL/VBLK 03(Bit 5) GPCL Ouput Enable TVP5151 www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 Figure3-12.ConfigurationShared Pins NOTE Alsosee theconfigurationsharedpinsregisteratsubaddress0Fh. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 33 SubmitDocumentationFeedback

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3.21.5 AutoswitchMask Register

Reserved SEC_OFF N4.43_OFF PALN_OFF PALM_OFF Reserved N4.43_OFF 0 = NTSC4.43 isunmasked fromtheautoswitchprocess.Autoswitchdoes switchtoNTSC4.43. 1 = NTSC4.43 ismasked from the autoswitchprocess.Autoswitchdoes not switchto NTSC4.43 (default). PALN_OFF 0 = PAL-N isunmasked fromtheautoswitchprocess.Autoswitchdoes switchtoPAL-N. 1 = PAL-N ismasked fromtheautoswitchprocess.Autoswitchdoes notswitchtoPAL-N (default). PALM_OFF 0 = PAL-M isunmasked fromtheautoswitchprocess.Autoswitchdoes switchtoPAL-M. 1 = PAL-M ismasked fromtheautoswitchprocess.Autoswitchdoes notswitchtoPAL-M (default). SEC_OFF 0 = SECAM isunmasked fromtheautoswitchprocess.Autoswitchdoes switchtoSECAM (default). 1 = SECAM ismasked fromtheautoswitchprocess.Autoswitchdoes notswitchtoSECAM.

3.21.6 MiscellaneousOutput ControlsRegister

Reserved AVID/CLK_IN Reserved functionselect AVID/CLK_IN functionselect 0 = CLK_IN (default) 1 = AVID

3.21.7 ColorKillerThresholdControlRegister

Reserved Automaticcolorkiller Colorkillerthreshold Automaticcolorkiller 00 = Automaticmode (default) 01 = Reserved 10 = Colorkillerenabled,CbCr terminalsforcedtoa zerocolorstate 11 = Colorkillerdisabled Colorkillerthreshold 11111 = –30 dB (minimum) 10000 = –24 dB (default) 00000 = –18 dB (maximum)

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3.21.8 Luminance ProcessingControl#1 Register

2× luminance Pedestalnot Disableraw Luminance bypass Luminance signaldelaywithrespecttochrominancesignal outputenable present header enabledduring verticalblanking 2× luminanceoutputenable 0 = Outputdepends on bit4,luminancebypassenabledduringverticalblanking(default). 1 = Outputs2x luminancesamplesduringtheentireframe.Thisbittakesprecedenceoverbit4. Pedestalnotpresent 0 = 7.5IRE pedestalispresenton theanalogvideoinputsignal. 1 = Pedestalisnotpresenton theanalogvideoinputsignal(default). Disableraw header 0 = Insert656 ancillaryheadersforraw data 1 = Disable656 ancillaryheadersand insteadforcedummy ones (40h)(default) Luminance bypassenabledduringverticalblanking 0 = Disabled.Ifbit7, 2× luminanceoutputenable,is0, normal luminanceprocessingoccursand YCbCr samplesareoutputduringtheentireframe(default). 1 = Enabled.Ifbit7, 2× luminanceoutputenable,is0, normal luminanceprocessingoccursand YCbCr samples are outputduringVACTIVE and 2× luminancesamples are outputduringVBLK. Luminance bypassoccursforthedurationoftheverticalblankingas definedby registers18h and 19h. Luminance bypassoccursforthedurationoftheverticalblankingas definedby registers18h and 19h. Luminance signaldelaywithrespecttochrominancesignalinpixelclockincrements(range–8 to+7 pixel clocks) 1111 = –8 pixelclocksdelay 1011 = –4 pixelclocksdelay 1000 = –1 pixelclocksdelay 0000 = 0 pixelclocksdelay(default) 0011 = +3 pixelclocksdelay 0111 = +7 pixelclocksdelay Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 35 SubmitDocumentationFeedback

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3.21.9 Luminance ProcessingControl#2 Register

Reserved Luminance filter Reserved Peakinggain Mac AGC control select Luminance filterselect 0 = Luminance comb filterenabled(default) 1 = Luminance chrominancetrapfilterenabled Peakinggain(sharpness) 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Informationon peakingfrequency: ITU-R BT.601 samplingrate:allstandards Peakingcenterfrequencyis2.6MHz. Mac AGC control 00 = Automode 01 = Automode 10 = ForceMacrovisionAGC pulsedetectionoff 11 = ForceMacrovisionAGC pulsedetectionon

3.21.10 BrightnessControlRegister

Brightness[7:0] Brightness[7:0]:ThisregisterworksforCVBS and S-Videoluminance. 1111 1111 = 255 (bright) 1000 0000 = 128 (default) 0000 0000 = 0 (dark) The outputblack levelrelativeto the nominal black level(64 out of 1024) as a functionof the Brightness[7:0]settingisas follows: BlackLevel= nominal_black_level+ (Brightness[7:0]– 128)

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3.21.11 ColorSaturationControlRegister

Saturation[7:0] Saturation[7:0]:ThisregisterworksforCVBS and S-Videochrominance. 1111 1111 = 255 (maximum) 1000 0000 = 128 (default) 0000 0000 = 0 (nocolor) The totalchrominancegainrelativetothenominalchrominancegainas a functionoftheSaturation[7:0] settingisas follows: ChrominanceGain = nominal_chrominance_gain× (Saturation[7:0]/128)

3.21.12 Hue ControlRegister

Hue control(doesnotapplytoSECAM) 0111 1111 = +180 degrees 0000 0000 = 0 degrees(default) 1000 0000 = –180 degrees Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 37 SubmitDocumentationFeedback

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3.21.13 Outputs and Data Rates SelectRegister

Reserved YCbCr output CbCr code YCbCr datapathbypass YCbCr outputformat code range format YCbCr outputcode range 0 = ITU-R BT.601 codingrange(Y rangesfrom16 to235.U and V rangefrom16 to240) 1 = Extendedcodingrange(Y,U, and V rangefrom1 to254)(default) CbCr code format 0 = Offsetbinarycode (2scomplement + 128)(default) 1 = Straightbinarycode (2scomplement) YCbCr datapathbypass 00 = Normal operation(default) 01 = Decimationfilteroutputconnectsdirectlyto the YCbCr outputpins.Thisdata issimilarto the digitizedcompositedata,buttheHBLANK areaisreplacedwithITU-R BT.656 digitalblanking. 10 = Digitizedcomposite(ordigitizedS-videoluminance).A/D outputconnectsdirectlyto YCbCr outputpins. 11 = Reserved YCbCr outputformat 000 = 8-bit4:2:2YCbCr withdiscretesyncoutput 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = 8-bitITU-R BT.656 interfacewithembedded syncoutput(default)

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3.21.14 Luminance ProcessingControl#3 Register

Reserved Luminance trapfilterselect Luminance filterstopband bandwidth(MHz) 00 = No notch(default) 01 = Notch1 10 = Notch2 11 = Notch3 Luminance filterselect[1:0]selectsone ofthefourchrominancetrap(notch)filterstoproduceluminance signalby removing the chrominance signalfrom the composite video signal.The stopband of the chrominancetrapfilteriscenteredat the chrominancesubcarrierfrequencywithstopband bandwidth controlledby the two controlbits.See the followingtableforthe stopbandbandwidths.The WCF bitis controlledinthechrominancecontrol#2 register,see Section3.21.25. NTSC/PAL/SECAMWCF FILTER SELECT ITU-R BT.601 00 1.2244 01 0.8782 10 0.7297 11 0.4986 00 1.4170 01 1.0303 10 0.8438 11 0.5537 Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 39 SubmitDocumentationFeedback

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3.21.15 ConfigurationShared Pins Register

Reserved LOCK23 Reserved LOCK24B FID/GLCO VSYNC/PALI INTREQ/ Reserved,must GPCL/VBLK be setto0 LOCK23 (pin23)functionselect 0 = FID (default,ifbit3 isselectedtooutputFID) 1 = Lock indicator(indicateswhetherthedeviceislockedvertically) LOCK24B (pin24)functionselect 0 = PALI (default,ifbit2 isselectedtooutputPALI) 1 = Lock indicator(indicateswhetherthedeviceislockedhorizontally) FID/GLCO (pin23)functionselect(alsosee register03h forenhanced functionality) 0 = FID (default) 1 = GLCO VSYNC/PALI (pin24)functionselect(alsosee register03h forenhanced functionality) 0 = VSYNC (default) 1 = PALI INTREQ/GPCL/VBLK (pin27)functionselect 0 = INTREQ (default) 1 = GPCL orVBLK dependingon bit7 ofregister03h See Figure3-12fortherelationshipbetween theconfigurationsharedpins.

3.21.16 ActiveVideo Cropping StartPixelMSB Register

AVID startpixelMSB [9:2] ActivevideocroppingstartpixelMSB [9:2],setthisregisterfirstbeforesettingregister12h.The TVP5151 decoderupdatestheAVID startvaluesonlywhen register12h iswrittento.Thisstartpixelvalueisrelative tothedefaultvaluesoftheAVID startpixel.

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3.21.17 ActiveVideo Cropping StartPixelLSB Register

Reserved AVID active AVID startpixelLSB [1:0] AVID active 0 = AVID outactiveinVBLK (default) 1 = AVID outinactiveinVBLK ActivevideocroppingstartpixelLSB [1:0]:The TVP5151 decoderupdatestheAVID startvaluesonly when thisregisteriswrittento. AVID start[9:0](combinedregisters11h and 12h) 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) 11 1111 1111 = –1 10 0000 0000 = –512

3.21.18 ActiveVideo Cropping Stop PixelMSB Register

AVID stoppixelMSB [9:2] Activevideocroppingstop pixelMSB [9:2],set thisregisterfirstbeforesettingthe register14h. The TVP5151 decoderupdatestheAVID stopvaluesonlywhen register14h iswrittento.Thisstoppixelvalue isrelativetothedefaultvaluesoftheAVID stoppixel.

3.21.19 ActiveVideo Cropping Stop PixelLSB Register

Reserved AVID stoppixelLSB ActivevideocroppingstoppixelLSB [1:0]:The number ofpixelsofactivevideomust be an even number. The TVP5151 decoderupdatestheAVID stopvaluesonlywhen thisregisteriswrittento. AVID stop[9:0](combinedregisters13h and 14h) 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default)(seeFigure3-6and Figure3-7) 11 1111 1111 = –1 10 0000 0000 = –512 Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 41 SubmitDocumentationFeedback

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3.21.20 Genlock and RTC Register

Reserved F/V bitcontrol Reserved GLCO/RTC F/V bitcontrol BIT 5 BIT 4 NUMBER OF LINES F BIT V BIT Standard ITU-R BT.656 ITU-R BT.656 0 0 Nonstandardeven Forceto1 Switchatfieldboundary Nonstandardodd Toggles Switchatfieldboundary Standard ITU-R BT.656 ITU-R BT.656 0 1 Nonstandard Toggles Switchatfieldboundary Standard ITU-R BT.656 ITU-R BT.656 1 0 Nonstandard Pulsemode Switchatfieldboundary 1 1 Illegal GLCO/RTC. The followingtableshows thedifferentmodes. BIT 2 BIT 1 BIT 0 GENLOCK/RTC MODE

0 X 0 GLCO

RTC outputmode 00 X 1 (default)

1 X 0 GLCO

1 X 1 RTC outputmode 1

Allothervaluesarereserved. Figure3-9shows thetimingofGLCO, and Figure3-10shows thetimingofRTC.

3.21.21 HorizontalSync StartRegister

Horizontalsync(HSYNC) start 1111 1111 = –127 × 4 pixelclocks 1111 1110 = –126 × 4 pixelclocks 1000 0001 = –1 × 4 pixelclocks 1000 0000 = 0 pixelclocks(default) 0111 1111 = 1 × 4 pixelclocks 0111 1110 = 2 × 4 pixelclocks 0000 0000 = 128 × 4 pixelclocks

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U BT .656 EAV Code YOUT[7:0] HSYNC Y V Y F F X Y F F X Y U Y AVID

128 SCLK

BT .656 SAV Code TVP5151 www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 Figure3-13.HorizontalSync Table3-14.Clock Delays (SCLKs) STANDARD N hbhs N hb NTSC 28 272 PAL 32 284 SECAM 32 284 DetailedtiminginformationisalsoavailableinSection3.12.

3.21.22 VerticalBlankingStartRegister

Verticalblanking(VBLK) start 0111 1111 = 127 linesafterstartofverticalblankinginterval 0000 0001 = 1 lineafterstartofverticalblankinginterval 0000 0000 = Same timeas startofverticalblankinginterval(default)(seeFigure3-5) 1111 1111 = 1 linebeforestartofverticalblankinginterval 1000 0000 = 128 linesbeforestartofverticalblankinginterval Verticalblankingisadjustablewithrespecttothestandardverticalblankingintervals.The settinginthis registerdeterminesthetimingoftheINTREQ/GPCL/VBLK signalwhen itisconfiguredtooutputvertical blank(seeregister03h).The settinginthisregisteralsodeterminesthedurationoftheluminancebypass function(seeregister07h). Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 43 SubmitDocumentationFeedback

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3.21.23 VerticalBlankingStop Register

Verticalblanking(VBLK) stop 0111 1111 = 127 linesafterstopofverticalblankinginterval 0000 0001 = 1 lineafterstopofverticalblankinginterval 0000 0000 = Same timeas stopofverticalblankinginterval(default)(seeFigure3-5) 1111 1111 = 1 linebeforestopofverticalblankinginterval 1000 0000 = 128 linesbeforestopofverticalblankinginterval Verticalblankingisadjustablewithrespecttothestandardverticalblankingintervals.The settinginthis registerdeterminesthetimingoftheINTREQ/GPCL/VBLK signalwhen itisconfiguredtooutputvertical blank(seeregister03h).The settinginthisregisteralsodeterminesthedurationoftheluminancebypass function(seeregister07h).

3.21.24 Chrominance Control#1 Register

Reserved ColorPLL reset Chrominance Chrominance Automaticcolorgaincontrol adaptivecomb comb filter filterenable enable(CE) (ACE) ColorPLL reset 0 = ColorPLL notreset(default) 1 = ColorPLL reset When a 1 iswrittentothisbit,thecolorPLL phase isresettozeroand thesubcarrierPLL phase reset bitistransmittedon terminal23 (GLCO) on thenextline(NTSC orPAL). Chrominanceadaptivecomb filterenable(ACE) 0 = Disable 1 = Enable(default) Chrominancecomb filterenable(CE) 0 = Disable 1 = Enable(default) Automaticcolorgaincontrol(ACGC) 00 = ACGC enabled(default) 01 = Reserved 10 = ACGC disabled 11 = ACGC frozentothepreviouslysetvalue

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3.21.25 Chrominance Control#2 Register

Reserved WCF Chrominancefilterselect Wideband chrominancefilter(WCF) 0 = Disable 1 = Enable(default) Chrominancelowpass filterselect 00 = No notch(default) 01 = Notch1 10 = Notch2 11 = Notch3 Chrominanceoutputbandwidth(MHz) NTSC/PAL/SECAMWCF FILTER SELECT ITU-R BT.601 00 1.2214 01 0.8782 10 0.7297 11 0.4986 00 1.4170 01 1.0303 10 0.8438 11 0.5537 Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 45 SubmitDocumentationFeedback

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3.21.26 InterruptReset RegisterB

Software Macrovision Reserved Fieldrate Linealternation Colorlock H/V lock TV/VCR initializationdetectchanged changed reset changed reset changed reset changed reset changed reset reset reset InterruptresetregisterB isused by the externalprocessorto resetthe interruptstatusbitsininterrupt statusregisterB. Bitsloadedwitha 1 allowthecorrespondinginterruptstatusbittoresetto0.Bitsloaded witha 0 have no effecton theinterruptstatusbits. Softwareinitializationreset 0 = No effect(default) 1 = Resetsoftwareinitializationbit Macrovisiondetectchanged reset 0 = No effect(default) 1 = ResetMacrovisiondetectchanged bit Fieldratechanged reset 0 = No effect(default) 1 = Resetfieldratechanged bit Linealternationchanged reset 0 = No effect(default) 1 = Resetlinealternationchanged bit Colorlockchanged reset 0 = No effect(default) 1 = Resetcolorlockchanged bit H/V lockchanged reset 0 = No effect(default) 1 = ResetH/V lockchanged bit TV/VCR changed reset[TV/VCR mode isdeterminedby countingthe totalnumber of lines/frame.The mode switchestoVCR fornonstandardnumber oflines] 0 = No effect(default) 1 = ResetTV/VCR changed bit

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3.21.27 InterruptEnable RegisterB

Software Macrovision Reserved Fieldrate Linealternation Colorlock H/V lock TV/VCR initializationdetectchanged changed changed changed changed changed occurred InterruptenableregisterB isused by theexternalprocessortomask unnecessaryinterruptsourcesfor interruptB. Bitsloadedwitha 1 allowthecorrespondinginterruptconditiontogeneratean interrupton the externalpin.Conversely,bitsloaded with zeros mask the correspondinginterruptconditionfrom generatingan interrupton theexternalpin.Thisregisteronlyaffectstheexternalpin,itdoes notaffectthe bitsintheinterruptstatusregister.A givenconditioncan settheappropriatebitinthestatusregisterand not cause an interrupton the externalpin.To determineifthisdeviceisdrivingthe interruptpineither AND interruptstatusregisterB withinterruptenableregisterB or check the stateof interruptB inthe interruptB activeregister. Softwareinitializationoccurred 0 = Disabled(default) 1 = Enabled Macrovisiondetectchanged 0 = Disabled(default) 1 = Enabled Fieldratechanged 0 = Disabled(default) 1 = Enabled Linealternationchanged 0 = Disabled(default) 1 = Enabled Colorlockchanged 0 = Disabled(default) 1 = Enabled H/V lockchanged 0 = Disabled(default) 1 = Enabled TV/VCR changed 0 = Disabled(default) 1 = Enabled Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 47 SubmitDocumentationFeedback

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3.21.28 InterruptConfigurationRegisterB

0 = InterruptB isactivelow(default). 1 = InterruptB isactivehigh. InterruptpolarityB must be the same as interruptpolarityA of InterruptConfigurationRegisterA at AddressC2h. InterruptConfigurationRegisterB isused toconfigurethepolarityofinterruptB on theexternalinterrupt pin.When the interruptB is configuredforactivelow,the pin is drivenlow when activeand high impedance when inactive(open-drain).Conversely,when theinterruptB isconfiguredforactivehigh,itis drivenhighforactiveand drivenlowforinactive. Note:An externalpullupresistor(4.7kΩ to10 kΩ) isrequiredwhen thepolarityoftheexternalinterrupt terminal(pin27)isconfiguredas activelow.

3.21.29 IndirectRegisterData

22h Data[15:8] 21h Data[7:0] I2C registers21h and 22h can be used to writedata to or read data from indirectregisters.See I2C registers23h and 24h.

3.21.30 IndirectRegisterAddress

ADDR[7:0] ADDR[7:0]= LSB ofindirectaddress

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3.21.31 IndirectRegisterRead/WriteStrobe

R/W[7:0] This registerselectsthe most significantbitsof the indirectregisteraddress and performseitheran indirectread or writeoperation.Data willbe writtenfrom are read to IndirectRegisterData registers 21h-22h. R/W[7:0]: 01h = readfrom00h-1FFh addressbank 02h = writeto00h-1FFh addressbank 03h = readfrom200h-3FFh addressbank 04h = writeto200h-3FFh addressbank 05h = readfrom300h-3FFh addressbank 06h = writeto300h-3FFh addressbank

3.21.32 Video Standard Register

0000 = Autoswitchmode (default) 0001 = Reserved 0010 = (M,J)NTSC ITU-R BT.601 0011 = Reserved 0100 = (B,G, H, I,N) PAL ITU-R BT.601 0101 = Reserved 0110 = (M)PAL ITU-R BT.601 0111 = Reserved 1000 = (Combination-N)PAL ITU-R BT.601 1001 = Reserved 1010 = NTSC 4.43ITU-R BT.601 1011 = Reserved 1100 = SECAM ITU-R BT.601 With the autoswitchcode running,the applicationcan forcethe deviceto operateina particularvideo standardmode by writingtheappropriatevalueintothisregister. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 49 SubmitDocumentationFeedback

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3.21.33 Cb Gain FactorRegister

Thisisa read-onlyregisterthatprovidesthegainappliedtotheCb intheYCbCr datastream.

3.21.34 Cr Gain FactorRegister

Thisisa read-onlyregisterthatprovidesthegainappliedtotheCr intheYCbCr datastream.

3.21.35 MacrovisionOn Counter Register

Thisregisterallowstheusertodeterminehow many consecutiveframesinwhich theMacrovisionAGC pulsesaredetectedbeforethedecoderdecidesthattheMacrovisionAGC pulsesarepresent.

3.21.36 MacrovisionOffCounter Register

Thisregisterallowstheusertodeterminehow many consecutiveframesinwhich theMacrovisionAGC pulsesarenotdetectedbeforethedecoderdecidesthattheMacrovisionAGC pulsesarenotpresent. 3.21.37 656 RevisionSelectRegister Address 30h Default 00h 7 6 5 4 3 2 1 0 Reserved 656 revision select 656 revisionselect 0 = AdherestoITU-R BT.656.4and BT.656.5timing(default) 1 = AdherestoITU-R BT.656.3timing

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3.21.38 Patch WriteAddress

R/W[7:0] Thisregisterisused fordownloadingfirmwarepatchcode.Pleaserefertothepatchloadapplicationnote formore detail.Thisregistermust notbe writtentoorreadfromduringnormaloperation.

3.21.39 Patch Code Execute

R/W[7:0] Writingtothisregisterfollowinga firmwarepatchloadrestartstheCPU and initiatesexecutionofthepatch code.Thisregistermust notbe writtentoorreadfromduringnormaloperation.

3.21.40 MSB ofDevice ID Register

ThisregisteridentifiestheMSB ofthedeviceID.Value= 51h.

3.21.41 LSB ofDevice ID Register

ThisregisteridentifiestheLSB ofthedeviceID.Value= 51h. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 51 SubmitDocumentationFeedback

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3.21.42 ROM VersionRegister

ROM version[7:0] ROM Version[7:0]:ThisregisteridentifiestheROM code revisionnumber.

3.21.43 RAM VersionRegister

RAM version[7:0] RAM Version[7:0]:ThisregisteridentifiestheRAM code revisionnumber. Example: PatchRelease= v01.25 ROM Version= 01h RAM Version= 25h Note:Use ofthelatestpatchreleaseishighlyrecommended.

3.21.44 VerticalLineCount MSB Register

Reserved VerticallinecountMSB Verticallinecountbits[9:8]

3.21.45 VerticalLineCount LSB Register

Verticallinecountbits[7:0] Registers84h and 85h can be readand combined toextractthedetectednumber oflinesperframe.This can be used with nonstandardvideo signalssuch as a VCR in fast-forwardor rewind modes to synchronizethedownstream videocircuitry.

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3.21.46 InterruptStatusRegisterB

Software Macrovision Reserved Fieldrate Linealternation Colorlock H/V lock TV/VCR initializationdetectchanged changed changed changed changed changed Softwareinitialization 0 = Softwareinitializationisnotready. 1 = Softwareinitializationisready. Macrovisiondetectchanged 0 = Macrovisiondetectstatushas notchanged. 1 = Macrovisiondetectstatushas changed. Fieldratechanged 0 = Fieldratehas notchanged. 1 = Fieldratehas changed. Linealternationchanged 0 = Linealterationhas notchanged. 1 = Linealternationhas changed. Colorlockchanged 0 = Colorlockstatushas notchanged. 1 = Colorlockstatushas changed. H/V lockchanged 0 = H/V lockstatushas notchanged. 1 = H/V lockstatushas changed. TV/VCR changed 0 = TV/VCR statushas notchanged. 1 = TV/VCR statushas changed. InterruptstatusregisterB ispolledby theexternalprocessortodeterminetheinterruptsourceforinterrupt B. Afteran interruptconditionis set,itcan be resetby writingto the interruptresetregisterB at subaddress1Ch witha 1 intheappropriatebit. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 53 SubmitDocumentationFeedback

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3.21.47 InterruptActiveRegisterB

0 = InterruptB isnotactiveon theexternalterminal(default). 1 = InterruptB isactiveon theexternalterminal. The interruptactiveregisterB ispolledby theexternalprocessortodetermineifinterruptB isactive.

3.21.48 StatusRegister#1

Peak white Line-alternating Fieldrate Lostlockdetect Color Verticalsync Horizontalsync TV/VCR status detectstatus status status subcarrierlock lockstatus lockstatus status Peak whitedetectstatus 0 = Peak whiteisnotdetected. 1 = Peak whiteisdetected. Line-alternatingstatus 0 = Nonlinealternating 1 = Linealternating Fieldratestatus 0 = 60 Hz 1 = 50 Hz Lostlockdetect 0 = No lostlocksincestatusregister#1 was lastread. 1 = Lostlocksincestatusregister#1 was lastread. Colorsubcarrierlockstatus 0 = Colorsubcarrierisnotlocked. 1 = Colorsubcarrierislocked. Verticalsynclockstatus 0 = Verticalsyncisnotlocked. 1 = Verticalsyncislocked. Horizontalsynclockstatus 0 = Horizontalsyncisnotlocked. 1 = Horizontalsyncislocked. TV/VCR status.TV mode is determinedby detectingstandardline-to-linevariationsand specific chrominance SCH phases based on the standardinputvideo format.VCR mode is determinedby detectingvariationsinthe chrominanceSCH phases compared to the chrominanceSCH phases of the standardinputvideoformat. 0 = TV 1 = VCR

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3.21.49 StatusRegister#2

Reserved Weak signal PAL switch Fieldsequence AGC and offset Macrovisiondetection detection polarity status frozenstatus Weak signaldetection 0 = No weak signal 1 = Weak signalmode PAL switchpolarityoffirstlineofodd field 0 = PAL switchis0. 1 = PAL switchis1. Fieldsequence status 0 = Even field 1 = Odd field AGC and offsetfrozenstatus 0 = AGC and offsetarenotfrozen. 1 = AGC and offsetarefrozen. Macrovisiondetection 000 = No copy protection 001 = AGC processpresent(MacrovisionType 1 present) 010 = ColorstripeprocessType 2 present 011 = AGC processand colorstripeprocessType 2 present 100 = Reserved 101 = Reserved 110 = ColorstripeprocessType 3 present 111 = AGC processand colorstripeprocessType 3 present Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 55 SubmitDocumentationFeedback

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3.21.50 StatusRegister#3

Analoggain:4-bitfront-endAGC analoggainsetting Digitalgain:4 MSBs of6-bitfront-endAGC digitalgainsetting The productoftheanalogand digitalgainisas follows: Gain Product= (1+ 3 × analog_gain/15)× (1+ gain_step× digital_gain/4096) Where, 0 ≤ analog_gain≤ 15 0 ≤ digital_gain≤ 63 The gain_stepsettingas a functionoftheanalog_gainsettingisshown inTable3-15. Table3-15.gain_stepSetting analog_gain gain_step 0 61 1 55 2 48 3 44 4 38 5 33 6 29 7 26 8 24 9 22 10 20 11 19 12 18 13 17 14 16 15 15

3.21.51 StatusRegister#4

Subcarriertohorizontal(SCH) phase SCH (colorPLL subcarrierphase at50% ofthefallingedge ofhorizontalsyncoflineone ofodd field;step size360°/256) 0000 0000 = 0.00° 0000 0001 = 1.41° 0000 0010 = 2.81° 1111 1110 = 357.2° 1111 1111 = 358.6°

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3.21.52 StatusRegister#5

Autoswitch Reserved Videostandard Samplingrate mode (SR) This registercontainsinformationabout the detectedvideostandardat which the deviceiscurrently operating.When autoswitchcode is running,thisregistermust be testedto determinewhich video standardhas been detected. Autoswitchmode 0 = Forcedvideostandard 1 = Autoswitchmode Videostandard VIDEO STANDARD [3:1] SR VIDEO STANDARD BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 Reserved 0 0 0 1 (M,J)NTSC ITU-R BT.601 0 0 1 0 Reserved 0 0 1 1 (B,D, G, H, I,N) PAL ITU-R BT.601 0 1 0 0 Reserved 0 1 0 1 (M)PAL ITU-R BT.601 0 1 1 0 Reserved 0 1 1 1 PAL-Nc ITU-R BT.601 1 0 0 0 Reserved 1 0 0 1 NTSC 4.43ITU-R BT.601 1 0 1 0 Reserved 1 0 1 1 SECAM ITU-R BT.601

3.21.53 Patch Read Address

R/W[7:0] Thisregistercan be used forpatchcode read-back.Thisregistermust not be writtento or read from duringnormaloperation. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 57 SubmitDocumentationFeedback

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3.21.54 Closed CaptionData Registers

Address 90h–93h Address 7 6 5 4 3 2 1 0 90h Closedcaptionfield1 byte1 91h Closedcaptionfield1 byte2 92h Closedcaptionfield2 byte1 93h Closedcaptionfield2 byte2 These registerscontaintheclosedcaptiondataarrangedinbytesperfield.

3.21.55 WSS/CGMS-A Data Registers

Address 94h–99h NTSC Address 7 6 5 4 3 2 1 0 BYTE 94h b5 b4 b3 b2 b1 b0 WSS field1 byte1 95h b13 b12 b11 b10 b9 b8 b7 b6 WSS field1 byte2 96h b19 b18 b17 b16 b15 b14 WSS field1 byte3 97h b5 b4 b3 b2 b1 b0 WSS field2 byte1 98h b13 b12 b11 b10 b9 b8 b7 b6 WSS field2 byte2 99h b19 b18 b17 b16 b15 b14 WSS field2 byte3 These registerscontainthewidescreensignaling(WSS/CGMS-A) dataforNTSC. ForNTSC, thebitsare: Bits0–1 representword 0,aspectratio. Bits2–5 representword 1,headercode forword 2. Bits6–13 representword 2,copy control. Bits14–19 representword 3,CRC. PAL/SECAM Address 7 6 5 4 3 2 1 0 BYTE 94h b7 b6 b5 b4 b3 b2 b1 b0 WSS field1 byte1 95h b13 b12 b11 b10 b9 b8 WSS field1 byte2 96h Reserved 97h b7 b6 b5 b4 b3 b2 b1 b0 WSS field2 byte1 98h b13 b12 b11 b10 b9 b8 WSS field2 byte2 99h Reserved ForPAL/SECAM, thebitsare: Bits0–3 representgroup1,aspectratio. Bits4–7 representgroup2,enhanced services. Bits8–10 representgroup3,subtitles. Bits11–13 representgroup4,others.

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3.21.56 VPS Data Registers

Address 9Ah–A6h Address 7 6 5 4 3 2 1 0 9Ah VPS byte1 9Bh VPS byte2 9Ch VPS byte3 9Dh VPS byte4 9Eh VPS byte5 9Fh VPS byte6 A0h VPS byte7 A1h VPS byte8 A2h VPS byte9 A3h VPS byte10 A4h VPS byte11 A5h VPS byte12 A6h VPS byte13 These registerscontaintheentireVPS datalineexcepttheclockrun-incode and thestartcode.

3.21.57 VITC Data Registers

Address A7h–AFh Address 7 6 5 4 3 2 1 0 A7h VITC byte1,framebyte1 A8h VITC byte2,framebyte2 A9h VITC byte3,secondsbyte1 AAh VITC byte4,secondsbyte2 ABh VITC byte5,minutesbyte1 ACh VITC byte6,minutesbyte2 ADh VITC byte7,hourbyte1 AEh VITC byte8,hourbyte2 AFh VITC byte9,CRC These registerscontaintheVITC data.

3.21.58 VBI FIFO Read Data Register

Thisaddressisprovidedtoaccess VBI dataintheFIFO throughthehostport.Allformsofteletextdata come directlyfrom the FIFO, whileallotherforms of VBI data can be programmed to come from the registersor from theFIFO. CurrentstatusoftheFIFO can be foundataddressC6h and thenumber of bytesintheFIFO islocatedataddressC7h. Ifthehostportistobe used toreaddatafromtheFIFO,then thehostaccessenablebitataddressCDh must be setto1.The formatused fortheVBI FIFO isshown in Section3.9. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 59 SubmitDocumentationFeedback

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3.21.59 TeletextFilterand Mask Registers

Address B1h–BAh Default 00h Address 7 6 5 4 3 2 1 0 B1h Filter1 mask 1 Filter1 pattern1 B2h Filter1 mask 2 Filter1 pattern2 B3h Filter1 mask 3 Filter1 pattern3 B4h Filter1 mask 4 Filter1 pattern4 B5h Filter1 mask 5 Filter1 pattern5 B6h Filter2 mask 1 Filter2 pattern1 B7h Filter2 mask 2 Filter2 pattern2 B8h Filter2 mask 3 Filter2 pattern3 B9h Filter2 mask 4 Filter2 pattern4 BAh Filter2 mask 5 Filter2 pattern5 For an NABTS system,thepacketprefixconsistsoffivebytes.Each bytecontainsfourdatabits(D[3:0]) interlacedwithfourHamming protectionbits(H[3:0]): 7 6 5 4 3 2 1 0 Only thedataportionD[3:0]from each byteisappliedtoa teletextfilterfunctionwiththecorresponding patternbitsP[3:0]and mask bitsM[3:0].Hamming protectionbitsareignoredby thefilter. For a WST system (PAL orNTSC), thepacketprefixconsistsoftwo bytesso thattwo patternsareused. Patterns3,4,and 5 areignored. The mask bitsenablefilteringusingthecorrespondingbitinthepatternregister.For example,a 1 inthe LSB ofmask 1 means thatthefiltermodule must compare theLSB ofnibble1 inthepatternregisterto thefirstdatabiton thetransaction.Ifthesematch,a trueresultisreturned.A 0 ina bitofmask 1 means thatthefiltermodule must ignorethatdatabitofthetransaction.Ifallzerosareprogrammed inthemask bits,thefiltermatches allpatternsreturninga trueresult(default00h). Patternand mask foreach byteand filterarereferredas <1,2><P,M><1,2,3,4,5>,where: <1,2> identifiesthefilter1 or2 <P,M> identifiesthepatternormask <1,2,3,4,5> identifiesthebytenumber

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3.21.60 TeletextFilterControlRegister

Reserved Filterlogic Mode TTX filter2 TTX filter1 enable enable Filterlogicallowsdifferentlogictobe appliedwhen combiningthedecisionoffilter1 and filter2 as follows: 00 = NOR (Default) 01 = NAND 10 = OR 11 = AND Mode 0 = TeletextWST PAL mode B (2headerbytes)(default) 1 = TeletextNABTS NTSC mode C (5headerbytes) TTX filter2 enable 0 = Disabled(default) 1 = Enabled TTX filter1 enable 0 = Disabled(default) 1 = Enabled Ifthefiltermatches orifthefiltermask isallzeros,a trueresultisreturned. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 61 SubmitDocumentationFeedback

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3.21.61 InterruptStatusRegisterA

Lock state Lock interrupt Reserved FIFO threshold Lineinterrupt Data interrupt interrupt interrupt The interruptstatusregisterA can be polledby thehostprocessortodeterminethesourceofan interrupt. Afteran interruptconditionissetitcan be resetby writingtothisregisterwitha 1 intheappropriatebit(s). Lock stateinterrupt 0 = TVP5151 isnotlockedtothevideosignal(default). 1 = TVP5151 islockedtothevideosignal. Lock interrupt 0 = A transitionhas notoccurredon thelocksignal(default). 1 = A transitionhas occurredon thelocksignal. FIFO thresholdinterrupt 0 = The amount ofdataintheFIFO has notyetcrossedthethresholdprogrammed ataddressC8h (default). 1 = The amount ofdataintheFIFO has crossedthethresholdprogrammed ataddressC8h. Lineinterrupt 0 = The videolinenumber has notyetbeen reached(default). 1 = The videolinenumber programmed inaddressCAh has occurred. Data interrupt 0 = No dataisavailable(default). 1 = VBI dataisavailableeitherintheFIFO orintheVBI dataregisters.

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3.21.62 InterruptEnable RegisterA

Reserved Lock interrupt Reserved FIFO threshold Lineinterrupt Data interrupt enable interruptenable enable enable The interruptenableregisterA isused by thehostprocessortomask unnecessaryinterruptsources.Bits loadedwitha 1 allowthecorrespondinginterruptconditiontogeneratean interrupton theexternalpin. Conversely,bitsloadedwitha 0 mask thecorrespondinginterruptconditionfrom generatingan interrupt on theexternalpin.Thisregisteronlyaffectstheinterrupton theexternalterminal,itdoes notaffectthe bitsininterruptstatusregisterA.A givenconditioncan settheappropriatebitinthestatusregisterand not cause an interrupton the externalterminal.To determineifthisdeviceisdrivingthe interruptterminal, eitherperforma logicalAND of interruptstatusregisterA withinterruptenableregisterA, or check the stateoftheinterruptA bitintheinterruptconfigurationregisterataddressC2h. Lock interruptenable 0 = Disabled(default) 1 = Enabled FIFO thresholdinterruptenable 0 = Disabled(default) 1 = Enabled Lineinterruptenable 0 = Disabled(default) 1 = Enabled Data interruptenable 0 = Disabled(default) 1 = Enabled Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 63 SubmitDocumentationFeedback

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3.21.63 InterruptConfigurationRegisterA

Reserved YCbCr enable InterruptA Interrupt (VDPOE) polarityA YCbCr enable(VDPOE) 0 = YCbCr pinsarehighimpedance. 1 = YCbCr pinsareactiveifotherconditionsaremet (default)(seeTable3-13). InterruptA (readonly) 0 = InterruptA isnotactiveon theexternalpin(default). 1 = InterruptA isactiveon theexternalpin. InterruptpolarityA must be the same as interruptpolarityB of InterruptConfigurationRegisterB at Address1Eh. InterruptpolarityA 0 = InterruptA isactivelow(default). 1 = InterruptA isactivehigh. InterruptconfigurationregisterA isused toconfigurethepolarityoftheexternalinterruptterminal.When interruptA isconfiguredas activelow,theterminalisdrivenlow when activeand highimpedance when inactive(open drain).Conversely,when theterminalisconfiguredas activehigh,itisdrivenhighwhen activeand drivenlowwhen inactive. Note:An externalpullupresistor(4.7kΩ to10 kΩ) isrequiredwhen thepolarityoftheexternalinterrupt terminal(pin27)isconfiguredas activelow.

3.21.64 VDP ConfigurationRAM Register

C4h RAM address(7:0) C5h Reserved RAM address8 The configurationRAM dataisprovidedtoinitializetheVDP withinitialconstants.The configurationRAM is512 bytesorganizedas 32 differentconfigurationsof 16 byteseach.The first12 configurationsare definedforthe currentVBI standards.An additionaltwo configurationscan be used as a custom programmed mode foruniquestandardssuch as Gemstar. Address C3h isused to read or writeto the RAM. The RAM internaladdresscounterisautomatically incrementedwitheach transaction.AddressesC5h and C4h make up a 9-bitaddresstoloadtheinternal addresscounterwitha specificstartaddress.Thiscan be used to writea subsetof the RAM foronly thosestandardsofinterest. NOTE RegistersD0h –FBh must allbe programmed with FFh before writingor readingthe configurationRAM. Fullfieldmode (CFh)must be disabledas well.

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www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 The suggestedRAM contentsareshown inTable3-16.Allvaluesarehexadecimal. Table3-16.VBI ConfigurationRAM forSignalsWith Pedestal INDEX ADDRESS 0 1 2 3 4 5 6 7 8 9 A B C D E F WST SECAM 000 AA AA FF FF E7 2E 20 A6 E4 B4 0E 0 7 0 10 0 WST SECAM 010 AA AA FF FF E7 2E 20 A6 E4 B4 0E 0 7 0 10 0 WST PAL B 020 AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0 WST PAL B 030 AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0 WST PAL C 040 AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0 WST PAL C 050 AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0 WST NTSC 060 AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0 WST NTSC 070 AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0 NABTS, NTSC 080 AA AA FF FF E7 2E 20 A2 63 93 0D 0 7 0 15 0 NABTS, NTSC 090 AA AA FF FF E7 2E 20 A2 63 93 0D 0 7 0 15 0 NABTS, NTSC-J 0A0 AA AA FF FF A7 2E 20 A3 63 93 0D 0 7 0 10 0 NABTS, NTSC-J 0B0 AA AA FF FF A7 2E 20 A3 63 93 0D 0 7 0 10 0 CC, PAL/SECAM 0C0 AA 2A FF 3F 04 51 6E 02 A4 7B 09 0 0 0 27 0 CC, PAL/SECAM 0D0 AA 2A FF 3F 04 51 6E 02 A4 7B 09 0 0 0 27 0 CC, NTSC 0E0 AA 2A FF 3F 04 51 6E 02 63 8C 09 0 0 0 27 0 CC, NTSC 0F0 AA 2A FF 3F 04 51 6E 02 63 8C 09 0 0 0 27 0 WSS/CGMS-A, 100 5B 55 C5 FF 0 71 6E 42 A4 CD 0F 0 0 0 3A 0PAL/SECAM WSS/CGMS-A, 110 5B 55 C5 FF 0 71 6E 42 A4 CD 0F 0 0 0 3A 0PAL/SECAM WSS/CGMS-A, 120 38 00 3F 00 0 71 6E 43 63 7C 08 0 0 0 39 0NTSC C WSS/CGMS-A, 130 38 00 3F 00 0 71 6E 43 63 7C 08 0 0 0 39 0NTSC C VITC,PAL/SECAM 140 0 0 0 0 0 8F 6D 49 A4 85 08 0 0 0 4C 0 VITC,PAL/SECAM 150 0 0 0 0 0 8F 6D 49 A4 85 08 0 0 0 4C 0 VITC,NTSC 160 0 0 0 0 0 8F 6D 49 63 94 08 0 0 0 4C 0 VITC,NTSC 170 0 0 0 0 0 8F 6D 49 63 94 08 0 0 0 4C 0 VPS, PAL 180 AA AA FF FF BA CE 2B 8D A4 DA 0B 0 7 0 60 0 VPS, PAL 190 AA AA FF FF BA CE 2B 8D A4 DA 0B 0 7 0 60 0 Gemstar 2x 1A0 99 99 FF FF 05 51 6E 05 63 18 13 80 00 00 60 00Custom 1 Gemstar 2x 1B0 ProgrammableCustom 1 Custom 2 1C0 Programmable Custom 2 1D0 Programmable Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 65 SubmitDocumentationFeedback

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3.21.65 VDP StatusRegister

FIFO fullerror FIFO empty TTX available CC field1 CC field2 WSS available VPS available VITC available available available The VDP statusregisterindicateswhetherdataisavailableineithertheFIFO ordataregisters,and status informationabouttheFIFO.Reading datafromthecorrespondingregisterdoes notclearthestatusflags automatically.These flagsare onlyresetby writinga 1 totherespectivebit.However, bit6 isupdated automatically. FIFO fullerror 0 = No FIFO fullerror 1 = FIFO was fullduringa writetoFIFO. The FIFO fullerrorflagissetwhen thecurrentlineofVBI datacan notentertheFIFO.For example,if theFIFO has onlytenbytesleftand teletextisthecurrentVBI line,theFIFO fullerrorflagisset,butno data iswrittenbecause the entireteletextlinedoes not fit.However, ifthe nextVBI lineisclosed captionrequiringonlytwo bytesofdataplustheheader,thisgoes intotheFIFO,even ifthefullerror flagisset. FIFO empty 0 = FIFO isnotempty. 1 = FIFO isempty. TTX available 0 = Teletextdataisnotavailable. 1 = Teletextdataisavailable. CC field1 available 0 = Closedcaptiondatafromfield1 isnotavailable. 1 = Closedcaptiondatafromfield1 isavailable. CC field2 available 0 = Closedcaptiondatafromfield2 isnotavailable. 1 = Closedcaptiondatafromfield2 isavailable. WSS available 0 = WSS dataisnotavailable. 1 = WSS dataisavailable. VPS available 0 = VPS dataisnotavailable. 1 = VPS dataisavailable. VITC available 0 = VITC dataisnotavailable. 1 = VITC dataisavailable.

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3.21.66 FIFO Word Count Register

Thisregisterprovidesthenumber ofwords intheFIFO.One word equalstwo bytes.

3.21.67 FIFO InterruptThresholdRegister

Thisregisterisprogrammed totriggeran interruptwhen thenumber ofwords intheFIFO exceeds this value(default80h).Thisinterruptmust be enabledataddressC1h. One word equalstwo bytes.

3.21.68 FIFO Reset Register

Writingany datatothisregisterresetstheFIFO and clearsany datapresentinallVBI readregisters.

3.21.69 LineNumber InterruptRegister

Field1 enable Field2 enable Linenumber Thisregisterisprogrammed totriggeran interruptwhen thevideolinenumber matches thisvalueinbits 5:0.Thisinterruptmust be enabledataddressC1h. The valueof0 or1 does notgeneratean interrupt. Field1 enable 0 = Disabled(default) 1 = Enabled Field2 enable 0 = Disabled(default) 1 = Enabled Linenumber defaultis00h. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 67 SubmitDocumentationFeedback

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3.21.70 PixelAlignment Registers

CBh Switchpixel[7:0] CCh Reserved Switchpixel[9:8] These registersform a 10-bithorizontalpixelpositionfrom the fallingedge of sync,where the VDP controllerinitiatestheprogram fromone linestandardtothenextlinestandard;forexample,theprevious lineofteletexttothenextlineofclosedcaption.Thisvaluemust be setso thattheswitchoccursafterthe previoustransactionhas clearedthedelayintheVDP, butearlyenough toallowthenew valuestobe programmed beforethecurrentsettingsarerequired.

3.21.71 FIFO Output ControlRegister

Thisregisterisprogrammed toallowI2C accesstotheFIFO ortoallowallVDP datatogo outthevideo portas ancillarydata. Hostaccessenable 0 = OutputFIFO datatothevideooutputYOUT[7:0]as ancillarydata 1 = Read FIFO dataviaI2C registerB0h (default)

3.21.72 FullFieldEnable Register

Thisregisterenablesthefullfieldmode. Inthismode, alllinesoutsidetheverticalblankareaand alllines inthelinemode registersprogrammed withFFh areslicedwiththedefinitionofregisterFCh. Valuesother thanFFh inthelinemode registersallowa differentslicemode forthatparticularline. Fullfieldenable 0 = Disablefullfieldmode (default) 1 = Enablefullfieldmode

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3.21.73 LineMode Registers

Address D0h D1h –FBh Default 00h FFh Address 7 6 5 4 3 2 1 0 D0 Line6 Field1 D1 Line6 Field2 D2 Line7 Field1 D3 Line7 Field2 D4 Line8 Field1 D5 Line8 Field2 D6 Line9 Field1 D7 Line9 Field2 D8 Line10 Field1 D9 Line10 Field2 DA Line11 Field1 DB Line11 Field2 DC Line12 Field1 DD Line12 Field2 DE Line13 Field1 DF Line13 Field2 E0 Line14 Field1 E1 Line14 Field2 E2 Line15 Field1 E3 Line15 Field2 E4 Line16 Field1 E5 Line16 Field2 E6 Line17 Field1 E7 Line17 Field2 E8 Line18 Field1 E9 Line18 Field2 EA Line19 Field1 EB Line19 Field2 EC Line20 Field1 ED Line20 Field2 EE Line21 Field1 EF Line21 Field2 F0 Line22 Field1 F1 Line22 Field2 F2 Line23 Field1 F3 Line23 Field2 F4 Line24 Field1 F5 Line24 Field2 F6 Line25 Field1 F7 Line25 Field2 F8 Line26 Field1 F9 Line26 Field2 FA Line27 Field1 FB Line27 Field2 These registersprogramthespecificVBI standardata specificlineinthevideofield. Copyright© 2009–2011,Texas InstrumentsIncorporated FunctionalDescription 69 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com Bit7 0 = Disablefilteringofnullbytesinclosedcaptionmodes 1 = Enablefilteringofnullbytesinclosedcaptionmodes (default) Inteletextmodes, bit7 enablesthedatafilterfunctionforthatparticularline.Ifitissetto0,thedata filterpassesalldataon thatline. Bit6 0 = Send VBI datatoregistersonly 1 = Send VBI datatoFIFO and theregisters.Teletextdataonlygoes toFIFO (default). Bit5 0 = AllowVBI datawitherrorsintheFIFO 1 = Do notallowVBI datawitherrorsintheFIFO (default) Bit4 0 = Do notenableerrordetectionand correction 1 = Enableerrordetectionand correction(default) Bits[3:0] 0000 = WST SECAM 0001 = WST PAL B 0010 = WST PAL C 0011 = WST NTSC 0100 = NABTS NTSC 0101 = TTX NTSC-J 0110 = CC PAL 0111 = CC NTSC 1000 = WSS/CGMS-A PAL 1001 = WSS/CGMS-A NTSC 1010 = VITC PAL 1011 = VITC NTSC 1100 = VPS PAL 1101 = Gemstar 2x Custom 1 1110 = Custom 2 1111 = Activevideo(VDP off)(default) A valueofFFh inthelinemode registersisrequiredforany linetobe slicedas partofthefullfieldmode.

3.21.74 FullFieldMode Register

ThisregisterprogramsthespecificVBI standardforfullfieldmode. Itcan be any VBI standard.Individual linesettingstake priorityover the fullfieldregister.This allowseach VBI lineto be programmed independentlybuthave theremaininglinesinfullfieldmode. The fullfieldmode registerhas thesame definitionsas thelinemode registers(default7Fh).

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4 ElectricalSpecifications

4.1 AbsoluteMaximum Ratings(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted) IO_DVDD toDGND –0.5V to4.5V DVDD toDGND –0.5V to2.3V Supplyvoltagerange PLL_AVDD toPLL_AGND –0.5V to2.3V CH_AVDD toCH_AGND –0.5V to2.3V Digitalinputvoltagerange,VItoDGND –0.5V to4.5V Inputvoltagerange,XTAL1 toPLL_GND –0.5V to2.3V AnaloginputvoltagerangeAItoCH_AGND –0.2V to2.0V Digitaloutputvoltagerange,VO toDGND –0.5V to4.5V Commercial 0°C to70°C Operatingfree-airtemperature,TA Industrial –40°C to85°C Storagetemperaturerange,Tstg –65°C to150°C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotrecommended. Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.

4.2 Recommended OperatingConditions

1.8IO_DVDD DigitalI/Osupplyvoltage 1.65 3.6 V3.3 DVDD Digitalsupplyvoltage 1.65 1.8 1.95 V PLL_AVDD AnalogPLL supplyvoltage 1.65 1.8 1.95 V CH_AVDD Analogcoresupplyvoltage 1.65 1.8 1.95 V VI(P-P) Analoginputvoltage(ac-couplingnecessary) 0 0.75 V VIH Digitalinputvoltagehigh(1) 0.7IO_DVDD V VIL Digitalinputvoltagelow(1) 0.3IO_DVDD V VIH_XTAL XTAL inputvoltagehigh(1) 0.7PLL_AVDD V VIL_XTAL XTAL inputvoltagelow(1) 0.3PLL_AVDD V IOH High-leveloutputcurrent(1) 2 mA IOL Low-leveloutputcurrent(1) –2 mA IOH_SCLK SCLK high-leveloutputcurrent(1) 4 mA IOL_SCLK SCLK low-leveloutputcurrent(1) –4 mA Commercial 0 70 TA Operatingfree-airtemperature °C Industrial –40 85 (1) Specifiedby design

4.3 ReferenceClock Specifications

Δf Frequencytolerance(1) –50 +50 ppm (1) Specifiedby design Copyright© 2009–2011,Texas InstrumentsIncorporated ElectricalSpecifications 71 SubmitDocumentationFeedback

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4.4 ElectricalCharacteristics

Typicalsupply voltages:DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V, For minimum/maximum values:TA = 0°C to 70°C forcommercial or TA = –40°C to 85°C forindustrial, Fortypicalvalues:TA = 25°C (unlessotherwisenoted)

4.5 DC ElectricalCharacteristics

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT IDD(IO_D) 3.3-VI/Odigitalsupplycurrent 100% colorbarinput 6.9 7.9 mA IDD(D) 1.8-Vdigitalsupplycurrent 100% colorbarinput 30 33.5 mA IDD(PLL_A) 1.8-VanalogPLL supplycurrent 100% colorbarinput 5.7 7.9 mA IDD(CH_A) 1.8-Vanalogcoresupplycurrent 100% colorbarinput 27.9 39.2 mA PTOT Totalpower dissipation,normalmode 100% colorbarinput 137 185 mW PDOWN Totalpower dissipation,power-down mode (2) 100% colorbarinput 1 mW C i Inputcapacitance(3) By design 8 pF VOH Outputvoltagehigh(3) IOH = 2 mA 0.8IO_DVDD V VOL Outputvoltagelow(3) IOL = –2 mA 0.22IO_DVDD V VOH_SCLK SCLK outputvoltagehigh(3) IOH = 4 mA 0.8IO_DVDD V VOL_SCLK SCLK outputvoltagelow(3) IOL = –4 mA 0.22IO_DVDD V IIH High-levelinputcurrent(4) VI= VIH ±20 µA IIL Low-levelinputcurrent(4) VI= VIL ±20 µA (1) Measured with22-Ω seriesterminationresistorsand 10-pFload. (2) Assuredby devicecharacterization (3) Specifiedby design (4) YOUT7 isa bidirectionalterminalwithan internalpulldownresistor.Thisterminalmay sinkmore thanthespecifiedcurrentwhen in RESET mode.

4.6 Analog ElectricalCharacteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Zi Inputimpedance,analogvideoinputs(1) 500 kΩ C i Inputcapacitance,analogvideoinputs(1) 10 pF Vi(pp) Inputvoltagerange(2) C coupling= 0.1µF 0 0.75 V ΔG Gain controlmaximum 12 dB ΔG Gain controlminimum 0 dB DNL Absolutedifferentialnonlinearity A/D only 0.5 1 LSB INL Absoluteintegralnonlinearity A/D only 1 2.5 LSB Fr Frequencyresponse 6 MHz, Specifiedby design –0.9 dB SNR Signal-to-noiseratio 6 MHz, 1.0VP-P 50 dB NS Noisespectrum 50% flatfield 50 dB DP Differentialphase Modulatedramp 0.5 ° DG Differentialgain Modulatedramp 1.5 % (1) Specifiedby design (2) The 0.75-Vmaximum appliestothesync-chrominanceamplitude,notsync-white.The recommended terminationresistorsare37.4Ω, as seen inSection6.

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VOHYOUT[7:0], AVID, VSYNC, HSYNC, FID/GLCO VOL Valid DataValid Data SCLK t1 t2 TVP5151 www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011

4.7 Clocks,Video Data,Sync Timing

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Dutycycle,SCLK 47 50 53 % t1 SCLK hightime ≥90% 18.5 ns t2 SCLK lowtime ≤10% 18.5 ns t3 SCLK falltime 90% to10% 5 ns t4 SCLK risetime 10% to90% 5 ns t5 Propagationdelaytime 3 8 ns (1) Measured with22-Ω seriesterminationresistorsand 10-pFload. Figure4-1.Clocks,Video Data,and Sync Timing Copyright© 2009–2011,Texas InstrumentsIncorporated ElectricalSpecifications 73 SubmitDocumentationFeedback

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4.8 I2C Host InterfaceTiming(1)

NO. PARAMETER MIN TYP MAX UNIT t1 Bus freetimebetween STOP and START 1.3 µs t2 Data Holdtime 0 0.9 µs t3 Data Setuptime 100 ns t4 Setuptimefora (repeated)START condition 0.6 µs t5 Setuptimefora STOP condition 0.6 ns t6 Holdtime(repeated)START condition 0.6 µs t7 RisetimeSDA and SCL signal 250 ns t8 FalltimeSDA and SCL signal 250 ns C b Capacitiveloadforeach bus line 400 pF fI2C I2C clockfrequency 400 kHz (1) Specifiedby design Figure4-2.I2C Host InterfaceTiming

4.9 Thermal Specifications

PARAMETER PACKAGE BOARD MIN TYP MAX UNIT JEDEC Low-K 125.3 ºC/W θJA Junction-to-ambientthermalresistance,stillair TQFP-32 (PBS) JEDEC High-K 91.1 ºC/W θJC Junction-to-casethermalresistance,stillair TQFP-32 (PBS) 39.3 ºC/W TJ(MAX) Maximum junctiontemperatureforreliableoperation TQFP-32 (PBS) 105 ºC

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5 Example RegisterSettings

The followingexample registersettingsare providedonly as a reference.These settings,given the assumed inputconnector,videoformat,and outputformat,set up the TVP5151 decoder and provide videooutput.Example registersettingsforotherfeaturesand the VBI data processorare not provided here.

5.1 Example 1

5.1.1 Assumptions

Device:TVP5151 Inputconnector:Composite(AIP1A) Videoformat:NTSC-M, PAL (B,G, H, I),orSECAM NOTE NTSC-4.43,PAL-N, and PAL-M aremasked fromtheautoswitchprocessby default.See the autoswitchmask registerataddress04h. Outputformat:8-bitITU-R BT.656 withembedded syncs

5.1.2 Recommended Settings

Recommended I2C writes:For thissetup,onlyone writeisrequired.Allotherregistersare setup by default. I2C registeraddress03h = Miscellaneouscontrolsregisteraddress I2C data09h = EnablesYCbCr outputand theclockoutput NOTE HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default.See the miscellaneouscontrolregisterataddress03h. Copyright© 2009–2011,Texas InstrumentsIncorporated Example RegisterSettings 75 SubmitDocumentationFeedback

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5.2 Example 2

5.2.1 Assumptions

Device:TVP5151 Inputconnector:S-video(AIP1A(luminance),AIP1B (chrominance)) VideoFormat:NTSC (M,4.43),PAL (B,G, H, I,M, N, Nc) orSECAM (B,D, G, K1,L) Outputformat:8-bit4:2:2YCbCr withdiscretesyncoutputs

5.2.2 Recommended Settings

Recommended I2C writes:This setup requiresadditionalwritesto outputthe discretesync 4:2:2data outputs,theHSYNC, and theVSYNC, and toautoswitchbetween allvideoformatsmentionedabove. I2C registeraddress00h = Videoinputsourceselection#1 register I2C data01h = SelectstheS-Videoinput,AIP1A (luminance),and AIP1B (chrominance) I2C registeraddress03h = Miscellaneouscontrolsregisteraddress I2C data0Dh = EnablestheYCbCr outputdata,HSYNC, VSYNC/PALI, AVID,and FID/GLCO I2C registeraddress04h = Autoswitchmask register I2C dataC0h = Unmask NTSC-4.43,PAL-N, and PAL-M fromtheautoswitchprocess I2C registeraddress0Dh = Outputsand dataratesselectregister I2C data40h = Enables8-bit4:2:2YCbCr withdiscretesyncoutput

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IO_DVDD IO_DVDD AVDD AVID AVDD HSYNC PDN IO_DVDD INTREQ/GPCL/VBLK PDN INTREQ/GPCL/VBLK AVID HSYNC VSYNC/PALI FID/GLCO SCLK OSC_IN YOUT[7:0] RESETB VSYNC/PALI SCL SCLK CH1_IN CH2_IN OSC_IN SDA FID/GLCO 1 µF 0.1 µF 0.1 µF 37.4 Ω 37.4 Ω 2.2 k/c87 2.2 k/c87 C10 0.1 µF 0.1 µF

27.000 MHz ± 50 ppm

1 µF CL1 1 µF CL2 1 2 0.1 µF 10 k/c87 TVP5151 12 13 14 15 16 AIP1A AIP1B PLL_AGND PLL_AVDD XTAL1/OSC_IN XTAL2 AGND RESETB SCLK IO_DVDD YOUT7/I2CSEL YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 YOUT1 YOUT0 DGND DVDD SCL SDA FID/GLCO VSYNC/PALI HSYNC AVID/CLK_IN INTREQ/GPCL/VBLK PDNREFPREFM CH_AGNDCH_AVDD Implies I C address is BAh. If B8h is to be used, connect pulldown resistor to digital ground. 0.1 µF C11 37.4 Ω 37.4 Ω R AAF AAF IO_DVDD 10 k See Note I /c87 10 k/c87 See Note H TVP5151 www.ti.com SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011

6 ApplicationInformation

6.1 ApplicationExample

A. The use ofINTREQ/GPCL/VBLK, AVID,HSYNC, and VSYNC/PALI isoptional. B. When OSC_IN isconnectedthroughS1,remove thecapacitorsforthecrystal. C. PDN needs tobe high,ifdevicehas tobe alwaysoperational. D. RESETB isoperationalonlywhen PDN ishigh.Thisallowsan active-lowresettothedevice. E. 100-kΩ resistor(R)inparallelwiththecrystalisrecommended formost crystaltypes. F. Anti-aliasingfilter(AAF)highlyrecommended forbestvideoquality. G. System levelESD protectionisnot includedinthisapplicationcircuit,but itishighlyrecommended on the analog videoinputs. H. An external10-kΩ pulldownresistorisrequiredwhen theINTREQ/GPCL/VBLK output(pin27)isdisabled(bit5 ofI2C register03h issetto0). I. An external10-kΩ pullupresistoris requiredwhen the INTREQ/GPCL/VBLK output(pin27) is enabled and configuredas an active-lowinterrupt(bit5 ofI2C register03h issetto1,bit1 ofI2C register0Fh issetto0,and bit0 ofI2C register1Eh issetto0). Figure6-1.ApplicationExample Copyright© 2009–2011,Texas InstrumentsIncorporated ApplicationInformation 77 SubmitDocumentationFeedback

SLES241E –SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com

7 RevisionHistory

Table7-1.RevisionHistory REVISION COMMENTS SLES241 Initialrelease Section1.4,RelatedProductsadded Section1.5,Trademarksmodified Section3.16,Figure3-8changed todepictvariousclockingoptions.Changed crystalparallelresistorrecommendation. Section3.21.10,Luminance Brightnessdescriptionmodified SLES241A Section3.21.11,ChrominanceSaturationdescriptionmodified Section3.21.50,StatusRegister#3 descriptionmodified Section6.1,Changed recommendationforresistorinparallelwiththecrystal Minoreditorialchanges throughout Section3.3,Figure3-2,Chroma trapfiltercharacteristicsforNTSC added. Section3.3,Figure3-3,Chroma trapfiltercharacteristicsforPAL added. Section3.4,Figure3-4,Colorlow-passfiltercharacteristicsadded. SLES241B Section3.8,Table3-1,Modifiedname forregister1100b. Section3.20,Table3-11,Added I2C indirectregistersataddress21h-24h. Section4.9,Added Power DissipationRatings. AEC-Q100 qualificationadded. Section3.13,Updated description. Section3.21.29,Added IndirectRegisterData Section3.21.30,Added IndirectRegisterAddress SLES241C Section3.21.31,Added IndirectRegisterRead/WriteStrobe Section3.21.38,Added PatchWriteAddress Section3.21.39,Added PatchCode Execute Section3.21.53,Added PatchRead Address SLES241D Removed AEC-Q100 qualification. Table2-1,Modifieddescriptionforterminal27. Table3-11,Modifiedregisters82h and 83h. Section3.21.4,Modifieddescriptionforbits7:5ofI2C register03h. SLES241E Section3.21.15,Removed supportfor1x outputclockfrequency(bit0 ofregister0Fh). Section3.21.42,Modifiedtheregisterdescriptionforregister82h. Section3.21.43,Modifiedtheregisterdescriptionforregister83h. Figure6-1,Added noteconcerningESD protection.Added pulldownand pullupresistorstopin27 output.

78 RevisionHistory Copyright© 2009–2011,Texas InstrumentsIncorporated

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TVP5151IPBS Active Production TQFP (PBS) | 32 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 5151I TVP5151IPBS.A Active Production TQFP (PBS) | 32 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 5151I TVP5151IPBSR Active Production TQFP (PBS) | 32 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 5151I TVP5151IPBSR.A Active Production TQFP (PBS) | 32 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 5151I TVP5151PBS Active Production TQFP (PBS) | 32 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 5151 TVP5151PBS.A Active Production TQFP (PBS) | 32 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 5151 TVP5151PBSR Active Production TQFP (PBS) | 32 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 5151 TVP5151PBSR.A Active Production TQFP (PBS) | 32 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 5151 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

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PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVP5151IPBSR TQFP PBS 32 1000 367.0 367.0 38.0 TVP5151PBSR TQFP PBS 32 1000 367.0 367.0 38.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TVP5151IPBS PBS TQFP 32 250 10 X 25 150 315 135.9 7620 12.2 11.1 11.25 TVP5151PBS PBS TQFP 32 250 10 X 25 150 315 135.9 7620 12.2 11.1 11.25 Pack Materials-Page 3

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