Logic IC

TVP5146M2IPFP

Texas Instruments

NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support Revised February 2012

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PDF pages: 109

Technical content

Datasheet sections

1 Introduction
1.1 Features
1.2 Description
1.3 Applications
1.4 RelatedProducts
1.5 Document Conventions
1.6 OrderingInformation
1.7 FunctionalBlockDiagram
1.8 TerminalAssignments
1.9 TerminalFunctions
2 FunctionalDescription
2.1 AnalogProcessingand A/D Converters
2.1.1 VideoInputSwitchControl
2.1.2 AnalogInputClamping
2.1.3 AutomaticGain Control
2.1.4 ADCs
2.2 DigitalVideoProcessing
2.2.2 CompositeProcessor
2.2.2.1 ColorLow-Pass Filter
2.2.2.2 Y/C Separation
2.2.3 Luminance Processing
2.2.4 ColorTransientImprovement(CTI)
2.2.5 Component VideoProcessor
2.2.6 ColorSpace Conversion
2.3 ClockCircuits
2.4 Real-TimeControl(RTC)
2.5 OutputFormatter
2.5.1 FastSwitchesforSCART
2.5.2 SeparateSyncs
2.5.3 Embedded Syncs
2.6 I2C HostInterface
2.6.1 Resetand I2C Bus AddressSelection
2.6.2 I2C Operation
2.6.3 VBUS Access
2.6.4 I2C TimingRequirements
2.7 VBI Data Processor
2.7.1 VBI FIFO and AncillaryData inVideoStream
2.7.2 VBI Raw Data Output
2.8 Resetand Initialization
2.9 AdjustingExternalSyncs
2.10 InternalControlRegisters
2.11 RegisterDefinitions
2.12 VBUS RegisterDefinitions
3 ElectricalSpecifications
2 Contents Copyright© 2005–2012,Texas InstrumentsIncorporated

NTSC/PAL/SECAM 4×10-BitDigitalVideo Decoder With Macrovision™ Detection,YPbPr Inputs,5-LineComb Filter,and SCART Support Data Manual PRODUCTION DATA informationiscurrentas of publicationdate. Products conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters. LiteratureNumber: SLES141H July2005–RevisedFebruary2012

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com ListofFigures

4 ListofFigures Copyright© 2005–2012,Texas InstrumentsIncorporated

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6 ListofTables Copyright© 2005–2012,Texas InstrumentsIncorporated

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

8 ListofTables Copyright© 2005–2012,Texas InstrumentsIncorporated

www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 NTSC/PAL/SECAM 4×10-BitDigitalVideo Decoder With Macrovision™ Detection,YPbPr Inputs,5-LineComb Filter, and SCART Support Check forSamples: TVP5146M2

1 Introduction

1.1 Features

– PatentedArchitectureforLocking toWeak,• Four 30-MSPS 11-BitA/D Channels With Noisy,or UnstableSignalsProgrammable Gain Control – Single14.31818-MHz ReferenceCrystalfor• Supports NTSC (J,M, 4.43),PAL (B,D, G, H, I, AllStandardsM, N, Nc, 60),SECAM (B,D, G, K, K1, L),CVBS, and S-Video – Line-LockedInternalPixelSampling Clock GenerationWith Horizontaland VerticalLock• Supports Analog SD YPbPr Component and SignalOutputsSCART (RGB/YPbPr + CVBS) Video Formats With Embedded Sync – Genlock Output RTC Format forDownstream Video Encoder Synchronization• Ten Analog Video InputTerminalsfor MultisourceConnection • CertifiedMacrovision™ Copy Protection Detection• User-Programmable Video Output Formats

AvailableinCommercial (0°C to70°C) and– 10-BitITU-R BT.656 4:2:2YCbCr With Industrial(−40°C to85°C) Temperature RangesEmbedded Syncs
VBI Data Processor– 10-Bit4:2:2YCbCr With SeparateSyncs – Teletext(NABTS, WST)– 20-Bit4:2:2YCbCr With SeparateSyncs – CC and Extended Data Service(EDS)– 2× Sampled Raw VBI Data inActiveVideo During VerticalBlankingPeriod – Wide Screen Signaling(WSS) – SlicedVBI Data During VerticalBlanking – Copy GenerationManagement System Periodor ActiveVideo Period(Full-Field (CGMS) Mode) – Video Program System (VPS/PDC)
HSYNC/VSYNC Outputs With Programmable – VerticalIntervalTime Code (VITC) Position,Polarity,Width,and FieldID (FID) – Gemstar ™ 1×/2× ModeOutput – V-Chip Decoding• Component Video Processing – RegisterReadback ofCC, WSS (CGMS),– Gain (Contrast)and Offset(Brightness) VPS/PDC, VITC and Gemstar 1×/2× SlicedAdjustments Data – Automatic Component Video Detection • I2C Host PortInterface(525/625) • Reduced Power Consumption: 1.8-VDigital– ColorSpace Conversion from RGB toYCbCr Core,3.3-VDigitalI/O,and 1.8-VAnalog Core
Composite and S-VideoProcessing With Power-Save and Power-Down Modes – Adaptive2-D 5-LineAdaptiveComb Filterfor • 80-TerminalTQFP PowerPAD ™ Package Composite Video Inputs;Chroma-Trap • RGB Sync on Green Not CurrentlySupported,Available AllReferencesto"RGB" inThisData Manual – Automatic Video Standard Detection Imply"SCART RGB" (NTSC/PAL/SECAM) and Switching – Luma Peaking With Programmable Gain – PatentedChroma TransientImprovement (CTI)Circuit Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PowerPAD isa trademarkofTexas Instruments. 3Gemstar isa trademarkofGemstar-TV Guide Intermational. 4Macrovisionisa trademarkofMacrovisionCorporation. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2005–2012,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

1.2 Description

The TVP5146M2 deviceisa high-qualitysingle-chipdigitalvideodecoderthatdigitizesand decodes all popularbaseband analogvideoformatsintodigitalcomponent video.The TVP5146M2 decodersupports the analog-to-digital(A/D) conversionof component RGB and YPbPr signals,as wellas the A/D conversionand decodingof NTSC, PAL, and SECAM compositeand S-Videointocomponent YCbCr. Thisdecoderincludesfour11-bit30-MSPS A/D converters(ADCs).Precedingeach ADC inthedevice, thecorrespondinganalogchannelcontainsan analogcircuitthatclamps theinputtoa referencevoltage and appliesa programmable gainand offset.A totaloftenvideoinputterminalscan be configuredtoa combinationofRGB, YPbPr,CVBS, orS-Videovideoinputs. Component, composite,or S-Videosignalsare sampled at 2× the ITU-R BT.601 clockfrequency,line locked,and arethendecimatedtothe1× pixelrate.CVBS decodingutilizes5-lineadaptivecomb filtering forboththeluma and chroma datapathstoreducebothcross-lumaand cross-chromaartifacts.A chroma trapfilterisalsoavailable.On CVBS and S-Videoinputs,theusercan controlvideocharacteristics,such as contrast,brightness,saturation,and hue viaan I2C hostportinterface.Furthermore,luma peaking (sharpness)withprogrammable gainisincluded,as wellas a patentedchroma transientimprovement (CTI)circuit. A built-incolorspace converterisappliedtodecoded component RGB data. Two outputformatscan be selected:20-bit4:2:2YCbCr or10-bit4:2:2YCbCr. The TVP5146M2 decodergeneratessynchronization,blanking,field,activevideowindow,horizontaland verticalsyncs,clock,genlock(fordownstream videoencoder synchronization),hostCPU interrupt,and programmablelogicI/Osignals,inadditiontodigitalvideooutputs. The TVP5146M2 decoder includesmethods foradvanced verticalblankinginterval(VBI)data retrieval. The VBI data processor(VDP) slices,parses,and performserrorcheckingon teletext,closedcaption (CC),and otherVBI data.A built-inFIFO storesup to11 linesofteletextdataand,withproperhostport synchronization,full-screenteletextretrievalispossible.The TVP5146M2 decodercan pass throughthe outputformatter2× thesampled raw luma dataforhost-basedVBI processing. The main blocksoftheTVP5146M2 decoderinclude:

Robustsyncdetectionforweak and noisysignalsas wellas VCR trickmodes
Y/C separationby 2-D 5-lineadaptivecomb orchroma trapfilter
Fast-switchinputforpixel-by-pixelswitchingbetween CVBS and YPbPr/RGB component videoinputs (SCART support)
Four11-bit30-MSPS ADCs withanalogpreprocessors[clampand automaticgaincontrol(AGC)]
Luminance processor
Chrominanceprocessor
Component processor
Clock/timingprocessorand power-down control
Software-controlledpower-savingstandbymode
Outputformatter
I2C hostportinterface
VBI dataprocessor
Macrovision™ copy protectiondetectioncircuit(Type1,2,3,and separatecolorstripedetection)
3.3-VtolerantdigitalI/Oports

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1.3 Applications

DigitalTV
LCD TV/monitors
DVD-R
PVR
PC videocards
Videocapture/videoediting
Videoconferencing
Automotive
Industrial

1.4 RelatedProducts

TVP5150AM1
TVP5151
TVP5154A
TVP5158
TVP5160
TVP5147M1

1.5 Document Conventions

Throughoutthisdatamanual,severalconventionsareused toconvey information.These conventionsare listedbelow:

To identifya binarynumber orfield,a lowercase b followsthenumbers.For example:000b isa 3-bit binaryfield.
To identifya hexadecimalnumber orfield,a lowercase h followsthenumbers.Forexample:8AFh isa 12-bithexadecimalfield.
Allothernumbers thatappear inthisdocument thatdo nothave eithera b or h followingthenumber areassumed tobe decimalformat.
Ifthesignalor terminalname has a bar above thename (forexample,RESETB), thenthisindicates thelogicalNOT function.When asserted,thissignalisa logiclow,0,or0b.
RSVD indicatesthatthereferenceditemisreserved.

1.6 OrderingInformation

PACKAGED DEVICES (1)(2) TA 80-TERMINAL PLASTIC PACKAGE OPTION FLAT-PACK PowerPAD ™ PACKAGE TVP5146M2PFP Tray 0°C to70°C TVP5146M2PFPR Tape and reel TVP5146M2IPFP Tray -40°C to85°C TVP5146M2IPFPR Tape and reel (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTIweb siteatwww.ti.com. (2) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB design guidelinesareavailableatwww.ti.com/package. Copyright© 2005–2012,Texas InstrumentsIncorporated Introduction 11 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

Composite and S-V ideo Processor Y/C Separation 5-line Adaptive Comb Luma Processing Chroma Processing ADC1 ADC2 ADC3 ADC4 M U X Component Processor CVBS/Y C Y/G Pb/B Pr/R Gain/Offset Color Space Conversion C Y Output Formatter Y[9:0] YCbCr VBI Data Slicer Copy Protection Detector C[9:0] Host Interface Timing Processor With Sync Detector VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A CVBS/ Y/G CVBS/ Pb/B/C CVBS/ Pr/R/C CVBS/Y CVBS/Y/G Analog Front End Sampling Clock GPIO FSS HS/CS VS/VBLK FID AVID XTAL1 XTAL2 DATACLK RESETB GLCO PWDN SCL SDA YCbCr TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

1.7 FunctionalBlock Diagram

Figure1-1.FunctionalBlock Diagram

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C_6/GPIO C_7/GPIO C_8/GPIO C_9/GPIO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD 1 1 VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD 25 26 27 28 PFP P ACKAGE (TOP VIEW) 79 78 77 76 7580 74 72 71 7073 29 30 31 32 33 69 68 67 66 65 64 34 35 36 37 38 39 40 63 62 61 VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XT AL2 XT AL1 VS/VBLK/GPIO HS/CS/GPIO FID C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD CH4_A33VDD CH4_A33GND VI_4_A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS/GPIO A VID/GPIO GLCO/I2CA IOVDD IOGND DA T ACLK TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012

1.8 TerminalAssignments

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1.9 TerminalFunctions

Table1-1.TerminalFunctions TERMINAL I/O DESCRIPTION NAME NO. Analog Video VI_1_A 80 VI_1_B 1 VI_1_x:AnalogvideoinputforCVBS/Pb/B/CVI_1_C 2 VI_2_x:AnalogvideoinputforCVBS/Y/G VI_2_A 7 VI_3_x:AnalogvideoinputforCVBS/Pr/R/C VI_4_A:AnalogvideoinputforCVBS/YVI_2_B 8 I Up to10 composite,4 S-video,and 2 compositeor3 component videoinputs(ora combination VI_2_C 9 thereof)can be supported. The inputsmust be ac coupled.The recommended couplingcapacitoris0.1µF.VI_3_A 16 The possibleinputconfigurationsarelistedintheinputselectregisteratI2C subaddress00h (seeVI_3_B 17 Table2-12). VI_3_C 18 VI_4_A 23 Clock Signals DATACLK 40 O Line-lockeddataoutputclock Externalclockreference.Itcan be connectedtoan externaloscillatorwitha 1.8-VcompatibleclockXTAL1 74 I signalortoa 14.31818-MHz crystaloscillator. XTAL2 75 O Externalclockreference.Not connectedifXTAL1 isdrivenby an externalsingle-endedoscillator. DigitalVideo 57,58, 59,60, DigitalvideooutputofCbCr,C_9 isMSB and C_0 isLSB. C_0 and C_[9-2]can be used as C_[9:0]/GPIO 63,64, O programmablegeneralpurposeI/O.C_1 (pin69)requiresan externalpulldownresistorand should 65,66, notbe used forgeneralpurposeI/O. 69,70 43,44, 45,46, DigitalvideooutputofY/YCbCr;Y_9 isMSB and Y_0 isLSB.Y_[9:0] 47,50, O Forthe8-bitmode, thetwo LSBs areignored.Unused outputscan be leftunconnected.51,52, 53,54 MiscellaneousSignals Fast-switch(blanking)input.Switchingsignalbetween thesynchronouscomponent video FSS/GPIO 35 I/O (YPbPr/RGB) and thecompositevideoinput. Programmable general-purposeI/O Genlockcontroloutput(GLCO)GLCO/I2CA 37 I/O Duringreset,thisterminalisan inputused toprogramtheI2C addressLSB. INTREQ 30 O Interruptrequest Power-down input: PWDN 33 I 1 = Power down 0 = Normal mode RESETB 34 I Reset,activelow Host Interface SCL 28 I/O I2C clock SDA 29 I/O I2C databus

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table1-1.TerminalFunctions(continued) TERMINAL I/O DESCRIPTION NAME NO. Power Supplies AGND 26 G Analogground.Connecttoanalogground. A18GND_REF 13 G Analog1.8-Vreturn A18VDD_REF 12 P Analogpower forreference1.8V CH1_A18GND 79 CH2_A18GND 10 G Analog1.8-Vreturn CH3_A18GND 15 CH4_A18GND 24 CH1_A18VDD 78 CH2_A18VDD 11 P Analogpower.Connectto1.8V. CH3_A18VDD 14 CH4_A18VDD 25 CH1_A33GND 3 CH2_A33GND 6 G Analog3.3-Vreturn CH3_A33GND 19 CH4_A33GND 22 CH1_A33VDD 4 CH2_A33VDD 5 P Analogpower.Connectto3.3V. CH3_A33VDD 20 CH4_A33VDD 21 27,32, DGND 42,56, G Digitalreturn 31,41,DVDD P Digitalpower.Connectto1.8V.55,67 39,49,IOGND G Digitalpower return62 38,48,IOVDD P Digitalpower.Connectto3.3V orlessforreducednoise.61 PLL_A18GND 77 G Analogpower return PLL_A18VDD 76 P Analogpower.Connectto1.8V. Sync Signals HorizontalsyncoutputordigitalcompositesyncoutputHS/CS/GPIO 72 I/O Programmable general-purposeI/O Verticalsyncoutput(formodes withdedicatedVSYNC) orVBLK outputVS/VBLK/GPIO 73 I/O Programmable general-purposeI/O FID 71 I/O Odd/even fieldindicatoroutput.Thisterminalneeds a pulldownresistor(seeFigure5-1). ActivevideoindicatoroutputAVID/GPIO 36 I/O Programmable general-purposeI/O Copyright© 2005–2012,Texas InstrumentsIncorporated Introduction 15 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

TVP5146M2 Analog Front End VI_4_A M U X VI_1_A VI_1_B VI_1_C M U X VI_2_A VI_2_B VI_2_C M U X VI_3_A VI_3_B VI_3_C 11-Bit ADC 11-Bit ADC 11-Bit ADC Clamp Clamp Clamp TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

2 FunctionalDescription

2.1 Analog Processingand A/D Converters

Figure2-1 shows a functionaldiagram of the analog processorsand ADCs. This blockprovidesthe analog interfaceto allvideoinputs.Itacceptsup to ten inputsand performssource selection,video clamping,videoamplification,A/D conversion,and gain and offsetadjustmentsto centerthe digitized videosignal. Figure2-1.Analog Processors and A/D Converters

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2.1.1 Video InputSwitch Control

The TVP5146M2 decoder has fouranalogchannelsthatacceptup to ten videoinputs.The user can configuretheinternalanalogvideoswitchesviatheI2C interface.The tenanalogvideoinputscan be used fordifferentinputconfigurations,some ofwhichare:

Up to ten selectableindividualcompositevideo inputs,as wellas othercombinationsof YPbPr, S-Video,and SCART can be supported(seeTable2-12) The inputselectionisperformedby theinputselectregisteratI2C subaddress00h (seeTable2-12).

2.1.2 Analog InputClamping

An internalclampingcircuitrestorestheac-coupledvideosignaltoa fixeddc level.The clampingcircuit providesline-by-linerestorationof the videosync levelto a fixeddc referencevoltage.The selection between bottomand mid clamp isperformedautomaticallyby theTVP5146M2 decoder.

2.1.3 Automatic Gain Control

The TVP5146M2 decoder uses fourprogrammable gainamplifiers(PGAs),one per channel.The PGA can scalea signalwitha voltage-inputcomplianceof 0.5 VPP to 2 VPP to a full-scale10-bitA/D output code range.A 4-bitcode setsthe coarse gain withindividualadjustmentper channel.Minimum gain correspondstoa code 0x0 (2-VPP full-scaleinput,–6-dB gain)whilemaximum gaincorrespondstocode 0xF (0.5-VPPfullscale,+6-dB gain).The TVP5146M2 decoderalsohas 12-bitfinegaincontrolsforeach channeland appliesthem independentlyto coarsegaincontrols.For compositevideo,the inputvideo signalamplitudecan varysignificantlyfrom the nominallevelof 1 VPP . The TVP5146M2 decoder can adjustitsPGA settingautomatically:an AGC can be enabledand can adjustthesignalamplitudesuch thatthemaximum rangeoftheADC isreachedwithoutclipping.Some nonstandardvideosignalscontain peak whitelevelsthatsaturatetheADC. Inthesecases,theAGC automaticallycutsback gaintoavoid clipping.IftheAGC ison,thentheTVP5146M2 decodercan readthegaincurrentlybeingused. The TVP5146M2 AGC comprisesthefront-endAGC beforeY/C separationand theback-endAGC after Y/C separation.The back-endAGC restorestheoptimum system gainwhenever an amplitudereference, such as thecompositepeak (whichisonlyrelevantbeforeY/C separation),forcesthefront-endAGC to setthegaintoolow.The front-endand back-endAGC algorithmscan use up tofouramplitudereferences: syncheight,colorburstamplitude,compositepeak,and luma peak. The specificamplitudereferencesbeing used by the front-endand back-end AGC algorithmscan be independentlycontrolledusingtheAGC whitepeak processingregisterlocatedatsubaddress74h.The TVP5146M2 gainincrementspeed and gainincrementdelaycan be controlledusingtheAGC increment speed registerlocatedat subaddress78h and the AGC incrementdelayregisterlocatedat subaddress 79h,respectively.

2.1.4 ADCs

AllADCs have a resolutionof 11 bitsand can operateup to 30 MSPS. AllA/D channelsreceivean identicalclockfromtheon-chipphase-lockedloop(PLL)ata frequencybetween 24 MHz and 30 MHz. All ADC referencevoltagesaregeneratedinternally.

2.2 DigitalVideo Processing

Figure2-2isa blockdiagramoftheTVP5146M2 digitalvideodecoderprocessor.Thisprocessorreceives digitizedvideosignalsfromtheADCs and performscompositeprocessingforCVBS and S-Videoinputs, YCbCr signalenhancements forCVBS and S-Videoinputs,and YPbPr/RGB processingforcomponent videoinputs.Italsogenerateshorizontaland verticalsyncs and otheroutputcontrolsignals,such as genlockforCVBS and S-Videoinputs.Additionally,itcan providefieldidentification,horizontaland vertical lock,verticalblanking,and activevideo window indicationsignals.The digitaldata outputcan be Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 17 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

C YCbCr Y[9:0] Timing Processor AVID FID GLCO XTAL1 XTAL2 RESETB Component Processor CH1 A/D CH2 A/D CH3 A/D Pr/R Pb/B Y/G YCbCr FSS HS/CS VS/VBLK DATACLK C[9:0] CH4 A/D CVBS/Y/G Host Interface SCL SDA Slice VBI Data Decimation PWDN Decimation Decimation Decimation TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com programmed to two formats:20-bit4:2:2withexternalsyncs or 10-bit4:2:2withembedded/separate syncs.The circuitdetectspseudosync pulses,AGC pulses,and colorstripingin Macrovision-encoded copy-protectedmaterial.InformationpresentintheVBI intervalcan be retrievedand eitherinsertedinthe ITU-R BT.656 outputas ancillarydataorstoredininternalFIFO and/orregistersforretrievalviathehost portinterface. Figure2-2.DigitalVideo ProcessingBlock Diagram 2.2.1 2x DecimationFilter Allinputsignalsare oversampled by a factorof two (27 MHz). The A/D outputsfirstpass through decimationfiltersthatreducethedatarateto1× thepixelrate.The decimationfilterisa half-bandfilter. Oversamplingand decimationfilteringcan effectivelyincreasetheoverallsignal-to-noiseratioby 3 dB.

2.2.2 Composite Processor

Figure2-3 isa blockdiagram of the TVP5146M2 digitalcompositevideoprocessingcircuit.Thiscircuit receivesa digitizedcompositeor S-Videosignalfrom theADCs and performsY/C separation(bypassed forS-Videoinput),chroma demodulationforPAL/NTSC and SECAM, and YUV signalenhancements. The 10-bitcompositevideo is multipliedby the subcarriersignalsin the quadraturedemodulatorto generatecolordifferencesignalsU and V.The U and V signalsarethensenttolow-passfilterstoachieve thedesiredbandwidth.An adaptive5-linecomb filterseparatesUV fromY based on theuniqueproperty of colorphase shiftsfrom lineto line.The chroma isremodulatedthrougha quadraturemodulatorand subtractedfromline-delayedcompositevideotogenerateluma.ThisformofY/C separationiscompletely complementary,thusthereisno lossofinformation.However,insome applications,itisdesirabletolimit theU/V bandwidthtoavoidcrosstalk.Inthatcase,notchfilterscan be turnedon.To accommodate some viewingpreferences,a peakingfilterisalsoavailableintheluma path.Contrast,brightness,sharpness, hue,and saturationcontrolsareprogrammablethroughthehostport.

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Delay – Peaking NTSC/PAL Remodulation NTSC/PAL Demodulation Notch Filter Color LPF ↓ 2 5-Line Adaptive Comb Filter Notch Filter Notch Filter Notch Filter Contrast Brightness Saturation Adjust Cr Y Cb Y Burst Accumulator (U) U SECAM Color Demodulation V DelayCVBS/Y SECAM Luma CVBS CVBS/C Color LPF ↓ 2 Burst Accumulator (V) U V Delay Delay TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Figure2-3.Composite and S-VideoProcessor Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 19 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

f − Frequency − MHz −70 −60 −50 −40 −30 −20 −10 ITU-R BT.601 −3 dB at 1.42 MHz Amplitude − dB f − Frequency − MHz −70 −60 −50 −40 −30 −20 −10 Amplitude − dB Filter 3 −3 dB at 554 kHz Filter 2 −3 dB at 844 kHz Filter 1 −3 dB at 1.03 MHz Filter 0 −3 dB at 1.41 MHz TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

2.2.2.1 ColorLow-Pass Filter

High filterbandwidthpreservessharpcolortransitionsand producescrispcolorboundaries.However,for videosourcesthathave asymmetricalU and V sidebands,itisdesirabletolimitthefilterbandwidthto avoidUV crosstalk.The colorlow-passfilterbandwidthisprogrammabletoenableone ofthethreenotch filters.Figure2-4and Figure2-5representthefrequencyresponsesofthewidebandcolorlow-passfilters. Figure2-4.ColorLow-Pass FilterFrequency Figure2-5.ColorLow-Pass FilterWith Filter Response Characteristics,NTSC/PAL ITU-R BT.601 Sampling

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f − Frequency − MHz −40 −35 −30 −25 −20 −15 −10 0 1 2 3 4 5 6 7 No Notch Filter Notch 3 Filter Notch 1 Filter Amplitude − dBNotch 2 Filter −40 −35 −30 −25 −20 −15 −10 0 1 2 3 4 5 6 7 f − Frequency − MHz Amplitude − dB No Notch Filter Notch 2 Filter Notch 1 Filter Notch 3 Filter TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012

2.2.2.2 Y/C Separation

Y/C separationcan be done usingadaptive5-line(5-H delay)comb filtersor a chroma trapfilter.The comb filtercan be selectivelybypassed intheluma or chroma path.Ifthecomb filterisbypassed inthe luma path,chroma trapfiltersare used which are shown inFigure2-6 and Figure2-7.The TI patented adaptivecomb filteralgorithmreducesartifactssuch as hangingdotsatcolorboundaries.Itdetectsand properlyhandlesfalsecolorsinhighfrequencyluminanceimages,such as a multiburstpatternor circle pattern.Adaptivecomb filteringistherecommended mode ofoperation. Figure2-6.Chroma Trap FilterFrequency Response, Figure2-7.Chroma Trap FilterFrequency Response, NTSC ITU-R BT.601 Sampling PAL ITU-R BT.601 Sampling Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 21 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

+ OUTDelay Peak Detector f – Frequency – MHz 0 1 2 3 4 5 6 7 Gain = 0 Gain = 2 Gain = 1 Gain = 0.5 Peak at f = 2.64 MHz Amplitude − dB TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

2.2.3 Luminance Processing

The digitizedcompositevideosignalpasses througheithera luminancecomb filterora chroma trapfilter, eitherof which removes chrominanceinformationfrom the compositesignalto generatea luminance signal.The luminancesignalisthenfedintotheinputofa peakingcircuit.Figure2-8illustratesthebasic functionsof the luminancedata path.In the case of S-Video,the luminancesignalbypasses the comb filteror chroma trapfilterand isfeddirectlytothecircuit.High-frequencycomponents oftheluminance signalare enhanced by a peakingfilter(sharpness).Figure2-9shows thecharacteristicsofthepeaking filteratfourdifferentgainsettingsthatareprogrammableviathehostport. Figure2-8.Luminance Edge-Enhancer Peaking Block Diagram Figure2-9.Peaking FilterResponse, NTSC/PAL ITU-R BT.601 Sampling

2.2.4 ColorTransientImprovement (CTI)

CTI enhances horizontalcolortransientsby delay modulationforboth colordifferencesignals.The operationmust be performedonlyon YCbCr-formatteddata.The colordifferencesignaltransitionpoints aremaintained,buttheedges areenhanced forsignalsthathave bandwidth-limitedcolorcomponents (for example,CVBS and S-Video).

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x Gain Y YLimit+ Offset x Gain CbCr CbCrLimit TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012

2.2.5 Component Video Processor

The component videoprocessingblocksupportsa user-selectablecontrast,brightness,and saturation adjustmentinYCbCr outputformats.For YCbCr outputformats,gainand offsetvaluesareappliedtothe luma datapathtomap thepixelvaluestothecorrectoutputrange(for10-bitYmin = 64 and Ymax = 940), and toprovidea means ofadjustingcontrastand brightness.For Y, digitalcontrast(gain)and brightness (offset)factorscan varyfrom 0 to255.The contrastcontroladjuststheamplituderange oftheY output centeredatthemidpointoftheoutputcode range.The limitblocklimitstheoutputtotheITU-R BT.601 range(Ymin toYmax )oran extendedrange,dependingon a usersetting. Figure2-10.Y Component Gain,Offset,Limit For CbCr components,a saturation(gain)factorisappliedtotheCbCr inputstomap them totheCbCr outputcode rangeand providesaturationcontrol.Similarly,thelimitblockcan limitCbCr outputstoa valid range: Cb,Crmin = 64 /Cb,Crmax = 960 Figure2-11.CbCr Component Gain,Offset,Limit

2.2.6 ColorSpace Conversion

The formulasforRGB toYCbCr conversionaregivenas: Cr = 0.511× R – 0.428× G – 0.083× B + 512

2.3 Clock Circuits

An internalline-lockedPLL generatesthesystem and pixelclocks.A 14.31818-MHz clockisrequiredto drivethePLL. Thiscan be inputtotheTVP5146M2 decoderatthe1.8-Vlevelon terminal74 (XTAL1),or a crystalof14.31818-MHz fundamentalresonantfrequencycan be connectedacrossterminals74 and 75 (XTAL2).Ifa parallelresonantcircuitisused as shown inFigure2-12,thentheexternalcapacitorsmust have thefollowingrelationship: C L1 = C L2 = 2C L − C STRAY (1) Where, C STRAY istheterminalcapacitancewithrespecttoground C L isthecrystalloadcapacitancespecifiedby thecrystalmanufacturer Figure2-12shows thereferenceclockconfigurations.The TVP5146M2 decodergeneratestheDATACLK signalused forclockingdata. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 23 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

XTAL1 14.31818-MHz Crystal XTAL2 TVP5146M2 74 XTAL1 XTAL2 CL1 CL2 14.31818-MHz 1.8-V Clock NC R RTC

45 CLK18 CLK

L S B

3 CLK128 CLK

1 CLK

M S B Reserved TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com NOTE: The resistor(R)inparallelwiththecrystalisrecommended tosupporta widerangeofcrystaltypes.A 100-kΩ resistor may be used formost crystaltypes. Figure2-12.ReferenceClock Configurations

2.4 Real-TimeControl(RTC)

Although the TVP5146M2 decoder is a line-lockedsystem, the color-burstinformationis used to determineaccuratelythe colorsubcarrierfrequencyand phase. This ensures properoperationwith nonstandardvideo signalsthatdo not followexactlythe requiredfrequencymultiplebetween color subcarrierfrequencyand videolinefrequency.The frequencycontrolword oftheinternalcolorsubcarrier PLL and thesubcarrierresetbitaretransmittedviaterminal37 (GLCO) foroptionaluse inan end system (forexample, by a video encoder).The frequencycontrolword is a 23-bitbinarynumber. The instantaneousfrequencyofthecolorsubcarriercan be calculatedfromthefollowingequation: FPLL = (Fctrl/223)× Fsclk (2) Where, FPLL isthefrequencyofthesubcarrierPLL Fctrlisthe23-bitPLL frequencycontrolword Fsclkistwo timesthepixelfrequency Figure2-13shows thedetailedtimingdiagram. NOTE: RTC resetbit(R) isactive-low,Sequence bit(S)PAL: 1 = (R-Y)linenormal,0 = (R-Y)lineinverted,NTSC: 1 = no change Figure2-13.RTC Timing

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2.5 Output Formatter

The outputformattersetshow thedataisformattedforoutputon theTVP5146M2 outputbuses.Table2-1 shows theavailableoutputmodes. Table2-1.Output Format TERMINAL NAME TERMINAL NUMBER 10-Bit4:2:2YCbCr 20-Bit4:2:2YCbCr Y_9 43 Cb9, Y9,Cr9 Y9 Y_8 44 Cb8, Y8,Cr8 Y8 Y_7 45 Cb7, Y7,Cr7 Y7 Y_6 46 Cb6, Y6,Cr6 Y6 Y_5 47 Cb5, Y5,Cr5 Y5 Y_4 50 Cb4, Y4,Cr4 Y4 Y_3 51 Cb3, Y3,Cr3 Y3 Y_2 52 Cb2, Y2,Cr2 Y2 Y_1 53 Cb1, Y1,Cr1 Y1 Y_0 54 Cb0, Y0,Cr0 Y0 C_9 57 Cb9, Cr9 C_8 58 Cb8, Cr8 C_7 59 Cb7, Cr7 C_6 60 Cb6, Cr6 C_5 63 Cb5, Cr5 C_4 64 Cb4, Cr4 C_3 65 Cb3, Cr3 C_2 66 Cb2, Cr2 C_1 69 Cb1, Cr1 C_0 70 Cb0, Cr0 Table2-2.Summary ofLineFrequencies,Data Rates,and Pixel/LineCounts COLORPIXEL HORIZONTALPIXELS PER ACTIVE PIXELS LINES PER SUBCARRIERSTANDARDS FREQUENCY LINE RATELINE PER LINE FRAME FREQUENCY(MHz) (kHz)(MHz)

601 Sampling

NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426 PAL-M 858 720 525 13.5 3.57561149 15.73426 PAL-60 858 720 525 13.5 4.43361875 15.73426 PAL-B,D, G, H, I 864 720 625 13.5 4.43361875 15.625 PAL-N 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625 Dr = 4.406250SECAM 864 720 625 13.5 15.625Db = 4.250000 Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 25 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.5.1 FastSwitches forSCART

The TVP5146M2 decodersupportstheSCART interfaceused inEuropean audio/videoend equipmentto carrycompositevideo,S-Video,and RGB videoon thesame cable.Ifcompositevideoand RGB videoare presentsimultaneouslyon thevideoterminalsassignedtoa SCART interface,theTVP5146M2 decoder assumes theyarepixelsynchronoustoeach other.The timingforbothcompositevideoand RGB videois obtainedfrom the compositesource,and itsderivedclockisused to sample RGB videoas well.The fast-switchinputterminalallowsswitchingbetween these two inputvideosourceson a pixel-by-pixel basis.The fastswitchisa hardswitch;thereisno alphablendingbetween bothsources.

2.5.2 SeparateSyncs

VS, HS, and VBLK are independentlysoftwareprogrammable to a 1× pixelcount.This allowsany possiblealignmenttotheinternalpixelcountand linecount.The defaultsettingsfor525-lineand 625-line videooutputsaregiveninFigure2-14and Figure2-15.FID changes atthesame transienttimewhen the trailingedge ofverticalsyncoccurs.The polarityofFID isprogrammableby an I2C interface.

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1 2 3 4 5 6 7 8 9 10 11 21 22

525 Line

263 264 265 266 267 268 269 270 271 272 283 284 285 HS VS Start VS Stop CS VBLK Start VBLK Stop TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 NOTE: LinenumberingconformstoITU-R BT.470. Figure2-14.VerticalSynchronizationSignalsfor525-LineSystem Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 27 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

625 Line

311 312 313 314 315 316 317 318 319 320 321 336 337 HS VS Start VS Stop CS VBLK Start VBLK Stop 622 623 624 625 1 2 3 4 5 6 7 23 24 258 338 TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com NOTE: LinenumberingconformstoITU-R BT.470. Figure2-15.VerticalSynchronizationSignalsfor625-LineSystem

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Y[9:0] DATACLK = 2 Pixel Clock Mode A B C D Cb DATACLK EAV 1Y Cr Y EAV EAV EAV SAV SAV SAV SAV

4 Cb0 Y0 Cr0 Y1

B AVID D AVID Stop AVID Start TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 NOTE: ITU-R BT.656 10-bit4:2:2timingwith2× pixelclockreference Figure2-16.HorizontalSynchronizationSignalsfor10-Bit4:2:2Mode Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 29 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

CbCr[9:0] NTSC 601 PAL 601 DATACLK = 1 Pixel Clock Mode A B C 136 142 D Cb DATACLK Cr Cb Cr Cb0 Cr0 Cb1 Cr1 HS Start Horizontal Blanking HS HS Stop A C B AVID D NOTE: AVID rising edge occurs 2 clock cycles early . Y[9:0] Y Y Y Y Y0 Y1 Y2 Y3Horizontal Blanking AVID Stop AVID Start TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com NOTE: 20-bit4:2:2timingwith1× pixelclockreference Figure2-17.HorizontalSynchronizationSignalsfor20-Bit4:2:2Mode

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10-Bit (PCLK = 2 Pixel Clock) Mode B/2 First Field B/2 858 864 H/2 20-Bit (PCLK = 1 Pixel Clock) B/2 429 432 H/2 HS VS Second Field HS VS B/2 TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Figure2-18.VSYNC PositionWith Respect toHSYNC

2.5.3 Embedded Syncs

Standardswithembedded syncs inserttheSAV and EAV codes intothedatastreamon therisingand fallingedges ofAVID. These codes containtheV and F bits,whichalsodefineverticaltiming.Table2-3 givestheformatoftheSAV and EAV codes. H equals1 alwaysindicatesEAV. H equals0 alwaysindicatesSAV. The alignmentofV and F totheline and fieldcountervariesdependingon thestandard. The P bitsareprotectionbits: P3 = V xorH; P2 = F xorH; P1 = F xorV;P0 = F xorV xorH Table2-3.EAV and SAV Sequence D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 Preamble 1 1 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 0 0 Statusword 1 F V H P3 P2 P1 P0 0 0 Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 31 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.6 I2C Host Interface

CommunicationwiththeTVP5146M2 decoderisviaan I2C hostinterface.The I2C standardconsistsof two signals,the serialinput/outputdata (SDA) lineand the serialinputclockline(SCL),which carry informationbetween the devicesconnectedto the bus.A thirdsignal(I2CA)isused forslaveaddress selection.Althoughan I2C system can be multimastered,theTVP5146M2 decoderfunctionsas a slave deviceonly. Because SDA and SCL arekeptopen drainata logic-highoutputlevelorwhen thebus isnotdriven,the usermust connectSDA and SCL toa positivesupplyvoltageviaa pullupresistoron theboard.The slave addressesselectsignal,terminal37 (I2CA),enablestheuse oftwo TVP5146M2 devicestiedtothesame I2C bus,because itcontrolstheleast-significantbitoftheI2C deviceaddress. Table2-4.I2C Host InterfaceTerminalDescription SIGNAL TYPE DESCRIPTION I2CA I Slaveaddressselection SCL I/O Input/outputclockline SDA I/O Input/outputdataline

2.6.1 Reset and I2C Bus Address Selection

The TVP5146M2 decodercan respondtotwo possiblechipaddresses.The addressselectionismade at resetby an externallysuppliedlevelon theI2CA terminal.The TVP5146M2 decodersamples thelevelof terminal37 atpower up oratthetrailingedge ofRESETB and configurestheI2C bus addressbitA0. Table2-5.I2C Address Selection A6 A5 A4 A3 A2 A1 A0 (I2CA) R/W HEX 1 0 1 1 1 0 0 (default) 1/0 B9/B8 1 0 1 1 1 0 1(1) 1/0 BB/BA (1) Ifterminal37 isstrappedtoDVDD viaa 2.2-kΩ resistor,I2C deviceaddressA0 issetto1.

2.6.2 I2C Operation

Data transfersoccurusingthefollowingillustratedformats. S 10111000 ACK Subaddress ACK Send Data ACK P Read fromI2C controlregisters S 10111000 ACK Subaddress ACK S 10111001 ACK ReceiveData NAK P S = I2C bus startcondition P = I2C bus stopcondition ACK = Acknowledgegeneratedby theslave NAK = Acknowledgegeneratedby themaster,formultiple-bytereadmasterwithACK each byteexceptlastbyte Subaddress= Subaddressbyte Data = Data byte.Ifmore thanone byteofdataistransmitted(readand write),the subaddresspointerisautomaticallyincremented. I2C bus address= Example shown thatI2CA isindefaultmode [write(B8h),read(B9h)]

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B8S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P VBUS Write B8S ACK E0 ACK Send Data ACK P Multiple Bytes B8S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P B8S ACK E1 ACK Send Data ACK ACK PSend Data• •□• Single Byte B8S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P VBUS Read B8S ACK E0 ACK ACK Multiple Bytes B8S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P B8S ACK E1 ACK ACK NAK PRead Data•□•□• Read Data NAK PS B9 S B9 ACK Read Data HOST Processor I2C VBUS Data I2C Registers 00h E0h E1h VBUS Address E8h EAh FFh VBUS[23:0] Line Mode VBUS Registers 00 0000h FIFO VPS/Gemstar VITC WSS/CGMS CC 80 051Ch 80 0520h 80 052Ch 80 0600h 80 0700h 90 1904h FF FFFFh NOTE: Examples use default I 2C address. ACK = Acknowledge generated by the slave NAK = No Acknowledge generated by the master TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012

2.6.3 VBUS Access

The TVP5146M2 decoder has additionalinternalregistersaccessiblethroughan indirectaccess to an internal24-bitaddresswideVBUS. Figure2-19shows theVBUS registeraccess. Figure2-19.VBUS Access Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 33 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.6.4 I2C Timing Requirements

The TVP5146M2 decoder requiresdelaysinthe I2C accesses to accommodate the internalprocessor timing.InaccordancewithI2C specifications,theTVP5146M2 decoderholdstheI2C clockline(SCL) low toindicatethewaitperiodtotheI2C master.IftheI2C masterisnotdesignedtocheck fortheI2C clock lineheld-lowcondition,thenthemaximum delaysmust alwaysbe insertedwhere required.These delays areofvariablelength;maximum delaysareindicatedinthefollowingdiagram: Normal register

2.7 VBI Data Processor

The TVP5146M2 VDP slicesvariousdataservicessuch as teletext(WST, NABTS), closedcaption(CC), wide screensignaling(WSS), program deliverycontrol(PDC), verticalintervaltimecode (VITC),video programsystem(VPS),copy generationmanagement system(CGMS) data,and electronicprogram guide (EPG orGemstar)1x/2x.Table2-6shows thesupportedVBI system. These servicesare acquiredby programming theVDP toenablethereceptionofone or more VBI data standard(s)inthe VBI.The VDP can be programmed on a line-per-linebasisto enablesimultaneous receptionofdifferentVBI formats,one perline.The resultsarestoredina FIFO and/orregisters.Because ofitshighdatabandwidth,theteletextresultsarestoredinFIFO only.The TVP5146M2 decoderprovides fullydecoded V-Chip data to the dedicatedregistersat subaddresses 800540h to 800543h (see Table2-117throughTable2-120). Table2-6.Supported VBI System VBI SYSTEM STANDARD LINE NUMBER NUMBER OF BYTES TeletextWST A SECAM 6-23(Fields1 and 2) 38 TeletextWST B PAL 6-22(Fields1 and 2) 43 TeletextNABTS C NTSC 10-21(Fields1 and 2) 34 TeletextNABTS D NTSC-J 10-21(Fields1 and 2) 35 ClosedCaption PAL 22 (Fields1 and 2) 2 ClosedCaption NTSC 21 (Fields1 and 2) 2 WSS-CGMS PAL 23 (Fields1 and 2) 14 bits WSS-CGMS NTSC 20 (Fields1 and 2) 20 bits VITC PAL 6-22 9 VITC NTSC 10-20 9 VPS (PDC) PAL 16 13 V-Chip(decoded) NTSC 21 (Field2) 2 Gemstar 1x NTSC 2 Gemstar 2x NTSC 5 withframebyte User Any Programmable Programmable

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2.7.1 VBI FIFO and AncillaryData inVideo Stream

SlicedVBI datacan be outputas ancillarydatainthevideostreaminITU-R BT.656 mode. VBI datais outputon theY_[9:2]terminalsduringthehorizontalblankingperiod.Table2-7shows theheaderformat and sequence oftheancillarydatainsertedintothevideostream.Thisformatisalsoused tostoreany VBI dataintotheFIFO.The sizeoftheFIFO is512 bytes.Therefore,theFIFO can storeup to11 linesof teletextdatawiththeNTSC NABTS standard. Table2-7.AncillaryData Format and Sequence D7 D0BYTE NO. D6 D5 D4 D3 D2 D1 DESCRIPTION(MSB) (LSB) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Ancillarydatapreamble 2 1 1 1 1 1 1 1 1

3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID)

4 NEP EP F5 F4 F3 F2 F1 F0 SecondarydataID (SDID)

5 NEP EP N5 N4 N3 N2 N1 N0 Number of32 bitdata(NN)

6 Videoline# [7:0] InternaldataID0 (IDID0)

7 0 0 0 Data error Match #1 Match #2 Videoline# [9:8] InternaldataID1 (IDID1) 8 1.Data Data byte 1stword 9 2.Data Data byte 10 3.Data Data byte 11 4.Data Data byte ⋮ ⋮ ⋮ m. Data Data byte Nth word CS[7:0] Check sum 4N+7 0 0 0 0 0 0 0 0 Fillbyte EP: Even parityforD0-D5 NEP: Negated even parity DID: 91h:SliceddataofVBI linesoffirstfield 53h:Sliceddataofline24 toend offirstfield 55h:SliceddataofVBI linesofsecond field 97h:Sliceddataofline24 toend ofsecond field SDID: Thisfieldholdsthedataformattakenfromthelinemode registerbits[2:0]ofthecorrespondingline. NN: Number ofDwords beginningwithbyte8 through4N+7. Thisvalueisthenumber ofDwords where each Dword is4 bytes. IDID0: Transactionvideolinenumber [7:0] IDID1: Bit0/1= Transactionvideolinenumber [9:8] Bit2 = Match 2 flag Bit3 = Match 1 flag Bit4 = 1 ifan errorwas detectedintheEDC block.0ifno errorwas detected. CS: Sum ofD0-D7 ofDID throughlastdatabyte Fillbyte: Fillbytesmake a multipleoffourbytesfrombyte0 tolastfillbyte.Forteletextmodes, byte8 isthesyncpatternbyte.Byte9 is thefirstdatabyte. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 35 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.7.2 VBI Raw Data Output

The TVP5146M2 decoder can outputraw A/D videodata at twicethe samplingrateforexternalVBI slicing.Thisistransmittedas an ancillarydata block,althoughsomewhat differentlyfrom the way the slicedVBI data is transmittedin the FIFO formatas describedin Section2.7.1. The samples are transmittedduringtheactiveportionoftheline.VBI raw datauses ITU-R BT.656 formathavingonlyluma data.The chroma samples are replacedby luma samples.The TVP5146M2 decoderinsertsa four-byte preamble 000h 3FFh 3FFh 180h beforedata start.There are no checksum bytesand fillbytesinthis mode. Table2-8.VBI Raw Data Output Format BYTE D9 D0D8 D7 D6 D5 D4 D3 D2 D1 DESCRIPTIONNO. (MSB) (LSB) 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VBI raw datapreamble 2 1 1 1 1 1 1 1 1 1 1 3 0 1 1 0 0 0 0 0 0 0 4 1.Data 5 2.Data 2× pixelrateluma data⋮ ⋮ (i.e.,NTSC 601:n = 1707) n-1 n-5.Data n n-4.Data

2.8 Reset and Initialization

Reset isinitiatedatpower up or any timeterminal34 (RESETB) isbroughtlow.Table2-9describesthe statusoftheTVP5146M2 terminalsduringand immediatelyafterreset. Table2-9.Reset Sequence SIGNAL NAME DURING RESET RESET COMPLETED Y_[9:0],C_[9:0]/GPIO Input Highimpedance RESETB, PWDN, SDA, SCL, FSS/GPIO, AVID/GPIO,GLCO/I2CA, Input InputHS/CS/GPIO, VS/VBLK/GPIO, FID INTREQ Input Output DATACLK Output Highimpedance

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3 ms (min) RESETB (Terminal 34) 1 ms (min) Invalid I 2C Cycle Valid Normal Operation 100 µs SDA (Terminal 29) Power (1.8 V) Power (3.3 V) Reset NOTE: All times shown are minimum values. Maximum time between 1.8 V and 3.3 V should be no longer than 1 second. TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 TIrecommends thefollowingpower-upsequence. Figure2-20.Reset Timing The followingregisterwritesmust be made beforenormaloperationofthedevice. I2C I2CSTEP SUBADDRESS DATA 1 0x03 0x01 2 0x03 0x00 When usingtheTVP5146M2I overtheindustrial(−40°C to85°C) temperaturerange,thefollowingregister writesare requiredfollowingdevicepower up and RESETB to write0x14 to VBUS register0xA00014. Thissetupisoptionalwhen usingtheTVP5146M2 overthecommercial(0°C to70°C) temperaturerange. I2C I2CSTEP SUBADDRESS DATA 1 0xE8 0x14 2 0xE9 0x00 3 0xEA 0xA0 4 0xE0 0x14

2.9 AdjustingExternalSyncs

The propersequence toprogramthefollowingexternalsyncsis:

To setNTSC, PAL-M, NTSC 443,PAL60 (525-linemodes): – SetthevideostandardtoNTSC (register02h). – SetHSYNC, VSYNC, VBLK, and AVID externalsyncs(registers16h through24h).
To setPAL, PAL-N, SECAM (625-linemodes): – SetthevideostandardtoPAL (register02h). – SetHSYNC, VSYNC, VBLK, and AVID externalsyncs(registers16h through24h).
Forautoswitch,setthevideostandardtoautoswitch(register02h). Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 37 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.10 InternalControlRegisters

The TVP5146M2 decoderisinitializedand controlledby a setofinternalregistersthatdefinetheoperating parametersoftheentiredevice.Communicationbetween theexternalcontrollerand theTVP5146M2 is througha standardI2C hostportinterface,as previouslydescribed.Table 2-10 shows the summary of theseregisters.Detailedprogramminginformationforeach registerisdescribedinthefollowingsections. Additionalregistersare accessiblethroughan indirectprocedureinvolvingaccess to an internal24-bit addresswideVBUS. Table2-11shows thesummary oftheVBUS registers. NOTE Do notwritetoreservedregisters.Reserved bitsinany definedregistermust be writtenwith zeros,unlessotherwisenoted. Table2-10.I2C RegisterSummary (1) I2CREGISTER NAME DEFAULT R/WSUBADDRESS Inputselect 00h 00h R/W AFE gaincontrol 01h 0Fh R/W Videostandard 02h 00h R/W Operationmode 03h 00h R/W Autoswitchmask 04h 23h R/W Colorkiller 05h 10h R/W Luminance processingcontrol1 06h 00h R/W Luminance processingcontrol2 07h 00h R/W Luminance processingcontrol3 08h 02h R/W Luminance brightness 09h 80h R/W Luminance contrast 0Ah 80h R/W Chrominancesaturation 0Bh 80h R/W Chroma hue 0Ch 00h R/W Chrominanceprocessingcontrol1 0Dh 00h R/W Chrominanceprocessingcontrol2 0Eh 0Eh R/W Reserved 0Fh Component Pr saturation 10h 80h R/W Component Y contrast 11h 80h R/W Component Pb saturation 12h 80h R/W Reserved 13h Component Y brightness 14h 80h R/W Reserved 15h AVID startpixel 16h-17h 055h R/W AVID stoppixel 18h-19h 325h R/W HSYNC startpixel 1Ah-1Bh 000h R/W HSYNC stoppixel 1Ch-1Dh 040h R/W VSYNC startline 1Eh-1Fh 004h R/W VSYNC stopline 20h-21h 007h R/W VBLK startline 22h-23h 001h R/W VBLK stopline 24h-25h 015h R/W Embedded Sync OffsetControl1 26h 00h R/W Embedded Sync OffsetControl2 27h 00h R/W (1) R = Read only,W = Writeonly,R/W = Read and write Reservedregisteraddressesmust notbe writtento.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-10.I2C RegisterSummary (1)(continued) I2CREGISTER NAME DEFAULT R/WSUBADDRESS Fast-switchcontrol 28h CCh R/W Reserved 29h Fast-switchSCART delay 2Ah 00h R/W Reserved 2Bh SCART delay 2Ch 00h R/W CTI delay 2Dh 00h R/W CTI control 2Eh 00h R/W Brightnessand ContrastRange Extender 2Fh 00h R/W Reserved 30h-31h Sync control 32h 00h R/W Outputformatter1 33h 40h R/W Outputformatter2 34h 00h R/W Outputformatter3 35h FFh R/W Outputformatter4 36h FFh R/W Outputformatter5 37h FFh R/W Outputformatter6 38h FFh R/W Clearlostlockdetect 39h 00h R/W Status1 3Ah R Status2 3Bh R AGC gainstatus 3Ch-3Dh R Reserved 3Eh Videostandardstatus 3Fh R GPIO input1 40h R GPIO input2 41h R Reserved 42h-45h R AFE coarsegainforCH1 46h 20h R/W AFE coarsegainforCH2 47h 20h R/W AFE coarsegainforCH3 48h 20h R/W AFE coarsegainforCH4 49h 20h R/W AFE finegainforPb_B 4Ah-4Bh 900h R/W AFE finegainforY_G_Chroma 4Ch-4Dh 900h R/W AFE finegainforPr_R 4Eh-4Fh 900h R/W AFE finegainforCVBS_Luma 50h-51h 900h R/W Reserved 52h-68h F-bitand V-bitcontrol1 69h 00h R/W Reserved 6Ah-6Bh Back-endAGC Control 6Ch 08h R/W Reserved 6Dh-6Eh AGC decrementspeed control 6Fh 04h R/W ROM version 70h R RAM VersionMSB 71h R Reserved 72h-73h AGC whitepeak processing 74h 00h R/W F-bitand V-bitcontrol2 75h 16h R/W VCR trickmode control 76h 8Ah R/W Horizontalshake increment 77h 64h R/W AGC incrementspeed 78h 05h R/W Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 39 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-10.I2C RegisterSummary (1)(continued) I2CREGISTER NAME DEFAULT R/WSUBADDRESS AGC incrementdelay 79h 1Eh R/W Reserved 7Ah-7Fh ChipID MSB 80h R ChipID LSB 81h R RAM VersionLSB 82h R CPLL speed control 83h 09h R/W Reserved 84h-96h Statusrequest 97h 00h R/W Reserved 98h-99h Verticallinecount 9Ah-9Bh R Reserved 9Ch-9Dh AGC decrementdelay 9Eh 00h R/W Reserved 9Fh-B0h VDP TTX filter1 mask 1 B1h 00h R/W VDP TTX filter1 mask 2 B2h 00h R/W VDP TTX filter1 mask 3 B3h 00h R/W VDP TTX filter1 mask 4 B4h 00h R/W VDP TTX filter1 mask 5 B5h 00h R/W VDP TTX filter2 mask 1 B6h 00h R/W VDP TTX filter2 mask 2 B7h 00h R/W VDP TTX filter2 mask 3 B8h 00h R/W VDP TTX filter2 mask 4 B9h 00h R/W VDP TTX filter2 mask 5 BAh 00h R/W VDP TTX filtercontrol BBh 00h R/W VDP FIFO word count BCh R VDP FIFO interruptthreshold BDh 80h R/W Reserved BEh VDP FIFO reset BFh 00h R/W VDP FIFO outputcontrol C0h 00h R/W VDP linenumber interrupt C1h 00h R/W VDP pixelalignment C2h-C3h 01Eh R/W Reserved C4h-D5h VDP linestart D6h 06h R/W VDP linestop D7h 1Bh R/W VDP globallinemode D8h FFh R/W VDP fullfieldenable D9h 00h R/W VDP fullfieldmode DAh FFh R/W Reserved DBh-DFh VBUS dataaccesswithno VBUS addressincrement E0h 00h R/W VBUS dataaccesswithVBUS addressincrement E1h 00h R/W FIFO readdata E2h R Reserved E3h-E7h VBUS addressaccess E8h-EAh 00 0000h R/W Reserved EBh-EFh Interruptraw status0 F0h Interruptraw status1 F1h Interruptstatus0 F2h R/W

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-10.I2C RegisterSummary (1)(continued) I2CREGISTER NAME DEFAULT R/WSUBADDRESS Interruptstatus1 F3h R/W Interruptmask 0 F4h 00h R/W Interruptmask 1 F5h 00h R/W Interruptclear0 F6h 00h R/W Interruptclear1 F7h 00h R/W Reserved F8h-FFh Table2-11.VBUS RegisterSummary (1) REGISTER NAME I2C SUBADDRESS DEFAULT R/W Reserved 00 0000h-80051Bh VDP closedcaptiondata 80 051Ch-80 051Fh R VDP WSS/CGMS data 80 0520h-800526h R Reserved 80 0527h-80052Bh VDP VITC data 80 052Ch-80 0534h R Reserved 80 0535h-80053Fh VDP V-Chipdata 80 0540h-800543h R Reserved 80 0544h-8005FFh VDP generallinemode and lineaddress 80 0600h-800611h 00h,FFh R/W Reserved 80 0612h-8006FFh VDP VPS/Gemstar data 80 070Dh-B0 005Fh R Interruptconfiguration B0 0060h 00h R/W Reserved B0 0061h-FF FFFFh (1) Writingany valuetoa reservedregistermay cause erroneousoperationoftheTVP5146M2 decoder.Itisrecommended nottoaccess any datato/fromreservedregisters. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 41 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.11 RegisterDefinitions

Table2-12.InputSelectRegister Subaddress 00h Default 00h 7 6 5 4 3 2 1 0 Inputselect[7:0] Ten inputterminalscan be configuredtosupportcomposite,S-Video,and component YPbPr orSCART as listedinTable2-13.Usersmust followthistableproperlyforS-Videoand component applications,because onlytheterminalconfigurationslistedinTable2-13are supported. Table2-13.Analog Channel and Video Mode Selection INPUT SELECT [7:0] MODE INPUT(S) SELECTED 7 6 5 4 3 2 1 0 HEX VI_1_A (default) 0 0 0 0 0 0 0 0 0 VI_1_B 0 0 0 0 0 0 0 1 1 VI_1_C 0 0 0 0 0 0 1 0 2 VI_2_A 0 0 0 0 0 1 0 0 4 VI_2_B 0 0 0 0 0 1 0 1 5 CVBS VI_2_C 0 0 0 0 0 1 1 0 6 VI_3_A 0 0 0 0 1 0 0 0 8 VI_3_B 0 0 0 0 1 0 0 1 9 VI_3_C 0 0 0 0 1 0 1 0 0A VI_4_A 0 0 0 0 1 1 0 0 0C VI_2_A(Y),VI_1_A(C) 0 1 0 0 0 1 0 0 44 VI_2_B(Y),VI_1_B(C) 0 1 0 0 0 1 0 1 45 VI_2_C(Y),VI_1_C(C) 0 1 0 0 0 1 1 0 46 VI_2_A(Y),VI_3_A(C) 0 1 0 1 0 1 0 0 54 VI_2_B(Y),VI_3_B(C) 0 1 0 1 0 1 0 1 55 VI_2_C(Y),VI_3_C(C) 0 1 0 1 0 1 1 0 56 S-Video VI_4_A(Y),VI_1_A(C) 0 1 0 0 1 1 0 0 4C VI_4_A(Y),VI_1_B(C) 0 1 0 0 1 1 0 1 4D VI_4_A(Y),VI_1_C(C) 0 1 0 0 1 1 1 0 4E VI_4_A(Y),VI_3_A(C) 0 1 0 1 1 1 0 0 5C VI_4_A(Y),VI_3_B(C) 0 1 0 1 1 1 0 1 5D VI_4_A(Y),VI_3_C(C) 0 1 0 1 1 1 1 0 5E VI_1_A(B),VI_2_A(G),VI_3_A(R) 1 0 0 0 0 1 0 0 84 RGB VI_1_B(B),VI_2_B(G),VI_3_B(R) 1 0 0 0 0 1 0 1 85 VI_1_C(B),VI_2_C(G),VI_3_C(R) 1 0 0 0 0 1 1 0 86 VI_1_A(Pb),VI_2_A(Y),VI_3_A(Pr) 1 0 0 1 0 1 0 0 94 YPbPr VI_1_B(Pb),VI_2_B(Y),VI_3_B(Pr) 1 0 0 1 0 1 0 1 95 VI_1_C(Pb),VI_2_C(Y),VI_3_C(Pr) 1 0 0 1 0 1 1 0 96 VI_1_A(B),VI_2_A(G),VI_3_A(R),VI_4_A(CVBS) 1 1 0 0 1 1 0 0 CC VI_1_B(B),VI_2_B(G),VI_3_B(R),VI_4_A(CVBS) 1 1 0 0 1 1 0 1 CD VI_1_C(B),VI_2_C(G),VI_3_C(R),VI_4_A(CVBS) 1 1 0 0 1 1 1 0 CE SCART VI_1_A(Pb),VI_2_A(Y),VI_3_A(Pr),VI_4_A(CVBS) 1 1 0 1 1 1 0 0 DC VI_1_B(Pb),VI_2_B(Y),VI_3_B(Pr),VI_4_A(CVBS) 1 1 0 1 1 1 0 1 DD VI_1_C(Pb),VI_2_C(Y),VI_3_C(Pr),VI_4_A(CVBS) 1 1 0 1 1 1 1 0 DE

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-14.AFE Gain ControlRegister Subaddress 01h Default 0Fh 7 6 5 4 3 2 1 0 Reserved 1 1 AGC chroma AGC luma Bit3: 1b must be writtentothisbit Bit2: 1b must be writtentothisbit AGC chroma: Controlsautomaticgaininthechroma/B/R/PbPrchannel: 0 = Manual (ifAGC luma issettomanual,AGC chroma isforcedtobe inmanual) 1 = Enabledautogain,appliesa gainvalueacquiredfromthesyncchannelforS-Videoand component mode. When AGC luma isset,thisstateisvalid(default). AGC luma enable: Controlsautomaticgainintheembedded syncchannelofCVBS, S-Video,component video 0 = Manual gain,AFE coarseand finegainfrozentothepreviousgainvaluesetby AGC when thisbitissetto0. 1 = Enabledautogainappliedtoonlytheembedded syncchannel(default) These settingsaffectonlytheanalogfront-end(AFE).The brightnessand contrastcontrolsarenotaffectedby thesesettings. Table2-15.Video Standard Register Subaddress 02h Default 00h 7 6 5 4 3 2 1 0 Reserved Videostandard[2:0] Withtheautoswitchcode running,theusercan forcethedecodertooperateina particularvideostandardmode by writingtheappropriate valueintothisregister.Changingthesebitscausestheregistersettingstobe reinitialized. Videostandard[2:0]: CVBS and S-Video Component Video

000 Autoswitchmode (default) Autoswitchmode (default)

001 (M,J)NTSC Interlaced525 010 (B,D, G, H, I,N) PAL Interlaced625 011 (M)PAL Reserved 100 (Combination-N)PAL Reserved 101 NTSC 4.43 Reserved

110 SECAM Reserved

111 PAL 60 Reserved

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-16.OperationMode ControlRegister Subaddress 03h Default 00h 7 6 5 4 3 2 1 0 Reserved H-PLL responsetime Reserved Power save H-PLL responsetime 00 = Adaptive(default) 01 = Reserved 10 = Fast 00 = Normal When intheNormal mode, thehorizontalPLL (H-PLL)responsetimeissettoitsslowestsetting.Thismode improvesnoiseimmunity and providesa more stableoutputlinefrequencyforstandardTV signalsources(forexample,TV tuners,DVD players,video surveillancecameras,etc.). When intheFastmode, theH-PLL responsetimeissettoitsfastestsetting.Thismode enablestheH-PLL torespondmore quicklyto largevariationsinthehorizontaltiming(forexample,VCR head switchingintervals).Thismode isrecommended forVCRs and also cameras lockedtotheAC power-linefrequency. When intheAdaptivemode, theH-PLL responsetimeisautomaticallyadjustedbased on themeasured horizontalphase error.Inthis mode, theH-PLL responsetimetypicallyapproachesitsslowestsettingformost standardTV signalsourcesand approachesitsfastest settingformost VCR signalsources. Power save 0 = Normal operation(default) 1 = Power save mode. Reduces theclockspeed oftheinternalprocessorand switchesofftheADCs. I2C interfaceisactiveand all currentoperatingsettingsarepreserved. Table2-17.AutoswitchMask Register Subaddress 04h Default 23h 7 6 5 4 3 2 1 0 Reserved SECAM NTSC 4.43 (Nc)PAL (M)PAL PAL (M,J)NTSC Autoswitchmode mask Limitsthevideoformatsbetween whichautoswitchispossible. SECAM 0 = Autoswitchdoes notincludeSECAM 1 = AutoswitchincludesSECAM (default) NTSC 4.43 0 = Autoswitchdoes notincludeNTSC 4.43(default) 1 = AutoswitchincludesNTSC 4.43 (Nc)PAL 0 = Autoswitchdoes notinclude(Nc)PAL (default) 1 = Autoswitchincludes(Nc)PAL (M)PAL 0 = Autoswitchdoes notinclude(M)PAL (default) 1 = Autoswitchincludes(M)PAL PAL 0 = Reserved 1 = Autoswitchincludes(B,D, G, H, I,N) PAL (default) (M,J)NTSC 0 = Reserved 1 = Autoswitchincludes(M,J)NTSC (default) Note:Bits1 and 0 must alwaysbe 11b.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-18.ColorKillerRegister Subaddress 05h Default 10h 7 6 5 4 3 2 1 0 Reserved Automaticcolorkiller Colorkillerthreshold[4:0] Automaticcolorkiller: 00 = Automaticmode (default) 01 = Reserved 10 = Colorkillerenabled,theC terminalsareforcedtoa zerocolorstate 11 = Colorkillerdisabled Colorkillerthreshold[4:0]: 11111 = 31 (maximum) 10000 = 16 (default) 00000 = 0 (minimum) Table2-19.Luminance ProcessingControl1 Register Subaddress 06h Default 00h 7 6 5 4 3 2 1 0 Reserved Pedestalnot Reserved VBI raw Luminance signaldelay[3:0] present Pedestalnotpresent: 0 = 7.5IRE pedestalispresenton theanalogvideoinputsignal(default) 1 = Pedestalisnotpresenton theanalogvideoinputsignal VBI raw: 0 = Disable(default) 1 = Enable Duringthedurationoftheverticalblankingas definedby VBLK startand stopregisters22h through25h,thechroma samplesare replacedby luma samples.Thisfeaturemay be used tosupportVBI processingperformedby an externaldeviceduringthevertical blankinginterval.To use thisbit,theoutputformatmust be the10-bitITU-R BT.656 mode. Luminance signaldelay[3:0]: Luminance signaldelaysrespecttochroma signalin1× pixelclockincrements. 0111 = Reserved 0110 = 5 pixelclocksdelay 0001 = 1 pixelclockdelay 0000 = 0 pixelclockdelay(default) 1111 = –1 pixelclockdelay 1000 = –8 pixelclockdelay Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 45 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-20.Luminance ProcessingControl2 Register Subaddress 07h Default 00h 7 6 5 4 3 2 1 0 Luma filterselect[1:0] Reserved Peakinggain(sharpness)[1:0] Reserved Luma filterselected[1:0]: 00 = Luminance adaptivecomb enable(defaulton CVBS) 01 = Luminance adaptivecomb disable(trapfilterselected) 10 = Luma comb/trapfilterbypassed(defaulton S-Video,component mode, and SECAM) 11 = Reserved Peakinggain(sharpness)[1:0]: 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Table2-21.Luminance ProcessingControl3 Register Subaddress 08h Default 02h 7 6 5 4 3 2 1 0 Reserved Trapfilterselect[1:0] Trapfilterselect[1:0]: Selectsone ofthefourtrapfilterstoproducetheluminancesignalby removingthechrominancesignalfromthecompositevideo signal.The stopbandofthechroma trapfilteriscenteredatthechroma subcarrierfrequencywiththestopbandbandwidthcontrolled by thetwo controlbits. Trapfilterstopband bandwidth(MHz): Filterselect[1:0] NTSC ITU-R 601 PAL ITU-R 601 00 1.2129 1.2129 01 0.8701 0.8701 10 (default) 0.7183 0.7383 11 0.5010 0.5010 Table2-22.Luminance BrightnessRegister Subaddress 09h Default 80h 7 6 5 4 3 2 1 0 Brightness[7:0] Brightness[7:0]: ThisregisterworksforCVBS and S-Videoluminance.See subaddress2Fh. 0000 0000 = 0 (dark) 1000 0000 = 128 (default) 1111 1111 = 255 (bright) Forcompositeand S-Videooutputs,theoutputblacklevelrelativetothenominalblacklevel(64outof1024)as a functionofthe Brightness[7:0]settingisas follows. BlackLevel= nominal_black_level+ (MB + 1)× (Brightness[7:0]– 128) Where M B isthebrightnessmultipliersettingintheBrightnessand ContrastRange ExtenderregisteratI2C subaddress2Fh.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-23.Luminance ContrastRegister Subaddress 0Ah Default 80h 7 6 5 4 3 2 1 0 Contrast[7:0] Contrast[7:0]: ThisregisterworksforCVBS and S-Videoluminance.See subaddress2Fh. 0000 0000 = 0 (minimum contrast) 1000 0000 = 128 (default) 1111 1111 = 255 (maximum contrast) Forcompositeand S-Videooutputs,thetotalluminancegainrelativetothenominalluminancegainas a functionoftheContrast[7:0] settingisas follows. Luminance Gain = (nominal_luminance_gain)× [Contrast[7:0]/64 /(2^MC )+ M C – 1] Where M C isthecontrastmultipliersettingintheBrightnessand ContrastRange ExtenderregisteratI2C subaddress2Fh. Table2-24.Chrominance SaturationRegister Subaddress 0Bh Default 80h 7 6 5 4 3 2 1 0 Saturation[7:0] Saturation[7:0]: ThisregisterworksforCVBS and S-Videochrominance. 0000 0000 = 0 (nocolor) 1000 0000 = 128 (default) 1111 1111 = 255 (maximum) Forcompositeand S-Videooutputs,thetotalchrominancegainrelativetothenominalchrominancegainas a functionoftheSaturation [7:0]settingisas follows. ChrominanceGain = (nominal_chrominance_gain)× (Saturation[7:0]/128) Table2-25.Chroma Hue Register Subaddress 0Ch Default 00h 7 6 5 4 3 2 1 0 Hue [7:0] Hue [7:0]: Does notapplytoa component orSECAM video.ThisregisterworksforCVBS and S-Videochrominance. 0111 1111 = +180 degrees 0000 0000 = 0 degrees(default) 1000 0000 = –180 degrees Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 47 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-26.Chrominance ProcessingControl1 Register Subaddress 0Dh Default 00h 7 6 5 4 3 2 1 0 Reserved ColorPLL reset Chroma Reserved Automaticcolorgaincontrol[1:0] adaptivecomb enable ColorPLL reset: 0 = ColorsubcarrierPLL notreset(default) 1 = ColorsubcarrierPLL reset Chrominanceadaptivecomb enable: Thisbitiseffectiveon compositevideoonly. 0 = Enable(default) 1 = Disable Automaticcolorgaincontrol(ACGC) [1:0]: 00 = ACGC enabled(default) 01 = Reserved 10 = ACGC disabled,ACGC settothenominalvalue 11 = ACGC frozentothepreviouslysetvalue Table2-27.Chrominance ProcessingControl2 Register Subaddress 0Eh Default 0Eh 7 6 5 4 3 2 1 0 Reserved PAL WCF Chrominancefilterselect[1:0] compensation PAL compensation: 0 = Disabled 1 = Enabled(default) WCF: Wideband chroma LPF filter 0 = Disabled 1 = Enabled(default) Chrominancefilterselect[1:0]: 00 = Disabled 01 = Notch1 10 = Notch2 (default) 11 = Notch3 See Figure2-6and Figure2-7forcharacteristics. Table2-28.Component Pr SaturationRegister Subaddress 10h Default 80h 7 6 5 4 3 2 1 0 Pr saturation[7:0] Pr saturation[7:0]: ThisregisterworksonlywithYPbPr component video.ForRGB video,use theAFE gainregisters. 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum Forcomponent video,thetotalPr gainrelativetothenominalPr gainas a functionofthePr saturation[7:0]settingisas follows: Pr Gain = (nominal_chrominance_gain)× (Prsaturation[7:0]/128)

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-29.Component Y ContrastRegister Subaddress 11h Default 80h 7 6 5 4 3 2 1 0 Y contrast[7:0] Y contrast[7:0]: ThisregisterworksonlywithYPbPr component video.ForRGB video,use theAFE gainregisters. 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum Forcomponent videooutputs,thetotalluminancegainrelativetothenominalluminancegainas a functionoftheY contrast[7:0]isas follows: Y Gain = (nominal_luminance_gain)× (Y contrast[7:0]/128) Table2-30.Component Pb SaturationRegister Subaddress 12h Default 80h 7 6 5 4 3 2 1 0 Pb saturation[7:0] Pb saturation: ThisregisterworksonlywithYPbPr component video.ForRGB video,use theAFE gainregisters. 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum Forcomponent video,thetotalPb gainrelativetothenominalPb gainas a functionofthePb saturation[7:0]settingisas follows: Pb Gain = (nominal_chrominance_gain)× (Pb saturation[7:0]/128) Table2-31.Component Y BrightnessRegister Subaddress 14h Default 80h 7 6 5 4 3 2 1 0 Y brightness[7:0] Y brightness: ThisregisterworksonlywithYPbPr component video.ForRGB video,use theAFE gainregisters. 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum Forcomponent video,theoutputblacklevelrelativetothenominalblacklevel(64outof1024)as a functionofY brightness[7:0]isas follows: BlackLevel= nominal_black_level+ (Y brightness[7:0]– 128) Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 49 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-32.AVID StartPixelRegister Subaddress 16h-17h Default 55h Subaddress 7 6 5 4 3 2 1 0 16h AVID start[7:0] 17h Reserved AVID active Reserved AVID start[9:8] AVID active: 0 = AVID outactiveinVBLK (default) 1 = AVID outinactiveinVBLK AVID start[9:0]: AVID startpixelnumber,thisisan absolutepixellocationfromHSYNC startpixel0. NTSC 601 default:is85 (55h) PAL 601 default:is95 (5Fh) The TVP5146M2 decoderupdatestheAVID startonlywhen theAVID startMSB byteiswrittento.Iftheuserchanges theseregisters, theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets.The AVID startpixelregisteralsocontrolsthe positionoftheSAV code. Table2-33.AVID Stop PixelRegister Subaddress 18h-19h Default 325h Subaddress 7 6 5 4 3 2 1 0 18h AVID stop[7:0] 19h Reserved AVID stop[9:8] AVID stop[9:0]: AVID stoppixelnumber.The number ofpixelsofactivevideomust be an even number.Thisisan absolutepixellocationfromHSYNC startpixel0. NTSC 601 default:805 (325h) PAL 601 default:815 (32Fh) The TVP5146M2 decoderupdatestheAVID stoponlywhen theAVID stopMSB byteiswrittento.Iftheuserchanges theseregisters, theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets.The AVID startpixelregisteralsocontrolsthe positionoftheEAV code. Table2-34.HSYNC StartPixelRegister Subaddress 1Ah-1Bh Default 000h Subaddress 7 6 5 4 3 2 1 0 1Ah HSYNC start[7:0] 1Bh Reserved HSYNC start[9:8] HSYNC startpixel[9:0]: Thisisan absolutepixellocationfromHSYNC startpixel0. The TVP5146M2 decoderupdatestheHSYNC startonlywhen theHSYNC startMSB byteiswrittento.Iftheuserchanges these registers,theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-35.HSYNC Stop PixelRegister Subaddress 1Ch-1Dh Default 040h Subaddress 7 6 5 4 3 2 1 0 1Ch HSYNC stop[7:0] 1Dh Reserved HSYNC stop[9:8] HSYNC stop[9:0]: Thisisan absolutepixellocationfromHSYNC startpixel0. The TVP5146M2 decoderupdatestheHSYNC stoponlywhen theHSYNC StopMSB byteiswrittento.Iftheuserchanges these registers,theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets. Table2-36.VSYNC StartLineRegister Subaddress 1Eh-1Fh Default 004h Subaddress 7 6 5 4 3 2 1 0 1Eh VSYNC start[7:0] 1Fh Reserved VSYNC start[9:8] VSYNC start[9:0]: Thisisan absolutelinenumber. The TVP5146M2 decoderupdatestheVSYNC startonlywhen theVSYNC startMSB byteiswrittento.Iftheuserchanges these registers,theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets. NTSC default:004h PAL default:001h Table2-37.VSYNC Stop LineRegister Subaddress 20h-21h Default 007h Subaddress 7 6 5 4 3 2 1 0 20h VSYNC stop[7:0] 21h Reserved VSYNC stop[9:8] VSYNC stop[9:0]: Thisisan absolutelinenumber. The TVP5146M2 decoderupdatestheVSYNC stoponlywhen theVSYNC stopMSB byteiswrittento.Iftheuserchanges these registers,theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets. NTSC default:007h PAL default:004h Table2-38.VBLK StartLineRegister Subaddress 22h-23h Default 001h Subaddress 7 6 5 4 3 2 1 0 22h VBLK start[7:0] 23h Reserved VBLK start[9:8] VBLK start[9:0]: Thisisan absolutelinenumber. The TVP5146M2 decoderupdatestheVBLK startlineonlywhen theVBLK startMSB byteiswrittento.Iftheuserchanges these registers,theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets. NTSC default:1 (001h) PAL default:623 (26Fh) Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 51 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-39.VBLK Stop LineRegister Subaddress 24h-25h Default 015h Subaddress 7 6 5 4 3 2 1 0 24h VBLK stop[7:0] 25h Reserved VBLK stop[9:8] VBLK stop[9:0]: Thisisan absolutelinenumber. The TVP5146M2 decoderupdatestheVBLK stoponlywhen theVBLK stopMSB byteiswrittento.Iftheuserchanges theseregisters, theTVP5146M2 decoderretainsvaluesindifferentmodes untilthisdecoderresets. NTSC default:21 (015h) PAL default:23 (017h) Table2-40.Embedded Sync OffsetControl1 Register Subaddress 26h Default 00h 7 6 5 4 3 2 1 0 Offset[7:0] Thisregisterallowsthelinepositionoftheembedded F bitand V bitsignalstobe offsetfromthe656 standardpositions.Thisregisteris onlyapplicabletoinputvideosignalswithstandardnumber oflines. 0111 1111 = 127 lines 0000 0001 = 1 line 0000 0000 = 0 line 1111 1111 = –1 line 1000 0000 = –128 lines Table2-41.Embedded Sync OffsetControl2 Register Subaddress 27h Default 00h 7 6 5 4 3 2 1 0 Offset[7:0] Thisregisterallowsthelinerelationshipbetween theembedded F bitand V bitsignalstobe offsetfromthe656 standardpositionsand moves F relativetoV.Thisregisterisonlyapplicabletoinputvideosignalswithstandardnumber oflines. 0111 1111 = 127 lines 0000 0001 = 1 line 0000 0000 = 0 line 1111 1111 = –1 line 1000 0000 = –128 lines

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-42.Fast-SwitchControlRegister Subaddress 28h Default CCh 7 6 5 4 3 2 1 0 Mode [2:0] Reserved FSS edge Reserved PolarityFSS Mode [2:0]: 000 = CVBS ↔ SCART 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Composite(default) 111 = Component only FSS edge: FSS issampled attherisingorfallingedge ofthesamplingclock 0 = Risingedge 1 = Fallingedge (default) PolarityFSS: 0 = 0:YCbCr/RGB, 1:CVBS (4A)(default) 1 = 0:CVBS (4A),1:YCbCr/RGB Table2-43.Fast-SwitchSCART Delay Register Subaddress 2Ah Default 00h 7 6 5 4 3 2 1 0 Reserved FSS delay[4:0] FSS delay[4:0]: Adjuststhedelaybetween theFSS and component RGB/YPbPr 0 1111 = 15 pixeldelay 0 0001 = 1 pixeldelay 0 0000 = 0 delay(default) 1 1111 = –1 pixeldelay 1 0000 = –26 pixeldelay Table2-44.SCART Delay Register Subaddress 2Ch Default 00h 7 6 5 4 3 2 1 0 Reserved SCART delay[6:0] SCART delay[4:0]: Adjustsdelaybetween theCVBS and component (RGB) video 0 1111 = 15 pixeldelay 0 0001 = 1 pixeldelay 0 0000 = 0 delay(default) 1 1111 = –1 pixeldelay 1 0000 = –16 pixeldelay Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 53 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-45.CTI Delay Register Subaddress 2Dh Default 00h 7 6 5 4 3 2 1 0 Reserved CTI delay[2:0] CTI delay[2:0]: SetsthedelayoftheY channelwithrespecttoCb/CrintheCTI block 011 = 3-pixeldelay 001 = 1-pixeldelay 000 = 0 delay(default) 111 = −1-pixeldelay 100 = −4-pixeldelay Table2-46.CTI ControlRegister Subaddress 2Eh Default 00h 7 6 5 4 3 2 1 0 CTI coring[3:0] CTI gain[3:0] CTI coring[3:0]: 4-bitCTI coringlimitcontrolvalues,unsigned,linearcontrolrangefrom0 to±60,stepsize= 4 1111 = ±60 0001 = ±4 0000 = 0 (default) CTI gain[3:0]: 4-bitCTI gaincontrolvalues,unsigned,linearcontrolrangefrom0 to15/16,stepsize= 1/16 1111 = 15/16 0001 = 1/16 0000 = 0 (default) Table2-47.Brightnessand ContrastRange ExtenderRegister Subaddress 2Fh Default 00h 7 6 5 4 3 2 1 0 Reserved Contrast Brightnessmultiplier[3:0] multiplier Contrastmultiplier(MC ): Increasesthecontrastcontrolrangeforcompositeand S-Videomodes. 0 = 2x contrastcontrolrange(default),Gain = n/64– 1 where n isthecontrastcontroland 64 ≤ n ≤ 255 1 = Normal contrastcontrolrange,Gain = n/128where n isthecontrastcontroland 0 ≤ n ≤ 255 Brightnessmultiplier3:0: Increasesthebrightnesscontrolrangeforcompositeand S-Videomodes from1x to16x. 0h = 1x 1h = 2x 3h = 4x 7h = 8x Fh = 16x Note:Ingeneral,thebrightnessmultipliershouldbe setto0h for10-bitoutputsand 3h for8-bitoutputs

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-48.Sync ControlRegister Subaddress 32h Default 00h 7 6 5 4 3 2 1 0 Reserved PolarityFID PolarityVS PolarityHS VS/VBLK HS/CS PolarityFID: DeterminespolarityofFID terminal 0 = Firstfieldhigh,second fieldlow(default) 1 = Firstfieldlow,second fieldhigh PolarityVS: DeterminespolarityofVS terminal 0 = Activelow(default) 1 = Activehigh PolarityHS: DeterminespolarityofHS terminal 0 = Activelow(default) 1 = Activehigh VS/VBLK: 0 = VS terminaloutputsverticalsync(default) 1 = VS terminaloutputsverticalblank HS/CS: 0 = HS terminaloutputshorizontalsync(default) 1 = HS terminaloutputscompositesync Table2-49.Output FormatterControl1 Register Subaddress 33h Default 40h 7 6 5 4 3 2 1 0 Reserved YCbCr code range CbCr code Reserved Outputformat[2:0] YCbCr outputcode range: 0 = ITU-R BT.601 codingrange(Y rangesfrom64 to940,Cb and Cr rangefrom64 to960) 1 = Extendedcodingrange(Y,Cb, and Cr rangefrom4 to1016)(default) CbCr code format: 0 = Offsetbinarycode (2scomplement + 512)(default) 1 = Straightbinarycode (2scomplement) Outputformat[2:0]: 000 = 10-bit4:2:2(pixelx 2 rate)withembedded syncs(ITU-RBT.656)(default) 001 = 20-bit4:2:2(pixelrate)withseparatesyncs 010 = Reserved 011 = 10-bit4:2:2withseparatesyncs 100-111= Reserved Note:10-bitmode isalsoused fortheraw VBI outputmode when bit4 (VBIraw)intheluminanceprocessingcontrol1 registerat subaddress06h isset(seeTable2-19). Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 55 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-50.Output FormatterControl2 Register Subaddress 34h Default 00h 7 6 5 4 3 2 1 0 Reserved Y [9:0]enable Reserved CLK polarity Clockenable Y [9:0]enable: Y_[9:0]and C_[9:0]outputenable 0 = Y_[9:0]and C_[9:0]high-impedance(default) 1 = Y_[9:0]and C_[9:0]active CLK polarity: 0 = Data clockedouton thefallingedge ofDATACLK (default) 1 = Data clockedouton therisingedge ofDATACLK Clockenable: 0 = DATACLK outputsarehigh-impedance(default) 1 = DATACLK outputsareenabled Table2-51.Output FormatterControl3 Register Subaddress 35h Default FFh 7 6 5 4 3 2 1 0 FSS [1:0] AVID [1:0] GLCO [1:0] FID [1:0] FSS [1:0]: FSS terminalfunctionselect 00 = FSS islogic0 output 01 = FSS islogic1 output 10 = Reserved 11 = FSS islogicinput(default) AVID [1:0]: AVID terminalfunctionselect 00 = AVID islogic0 output 01 = AVID islogic1 output 10 = AVID isactivevideoindicatoroutput 11 = AVID islogicinput(default) GLCO [1:0]: GLCO terminalfunctionselect 00 = GLCO islogic0 output 01 = GLCO islogic1 output 10 = GLCO isgenlockoutput 11 = GLCO islogicinput(default) FID [1:0]: FID terminalfunctionselect 00 = FID islogic0 output 01 = FID islogic1 output 10 = FID isFID output 11 = FID islogicinput(default)

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-52.Output FormatterControl4 Register Subaddress 36h Default FFh 7 6 5 4 3 2 1 0 VS/VBLK [1:0] HS/CS [1:0] C_1 [1:0] C_0 [1:0] VS/VBLK [1:0]: VS terminalfunctionselect 00 = VS islogic0 output 01 = VS islogic1 output 10 = VS/VBLK isverticalsyncorverticalblankoutputcorrespondingtobit1 (VS/VBLK)inthesynccontrolregisteratsubaddress32h (seeTable2-48) 11 = VS islogicinput(default) HS/CS [1:0]: HS terminalfunctionselect 00 = HS islogic0 output 01 = HS islogic1 output 10 = HS/CS ishorizontalsyncorcompositesyncoutputcorrespondingtobit0 (HS/CS)inthesynccontrolregisteratsubaddress32h (seeTable2-48) 11 = HS islogicinput(default) C_1 [1:0]: C_1 terminalfunctionselect 00 = C_1 islogic0 output 01 = C_1 islogic1 output 10 = Reserved 11 = C_1 islogicinput(default) C_0 [1:0]: C_0 terminalfunctionselect 00 = C_0 islogic0 output 01 = C_0 islogic1 output 10 = Reserved 11 = C_0 islogicinput(default) Note:C_x functionsareavailableonlyinthe10-bitoutputmode. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 57 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-53.Output FormatterControl5 Register Subaddress 37h Default FFh 7 6 5 4 3 2 1 0 C_5 [1:0]: C_5 terminalfunctionselect 00 = C_5 islogic0 output 01 = C_5 islogic1 output 10 = Reserved 11 = C_5 islogicinput(default) C_4 [1:0]: C_4 terminalfunctionselect 00 = C_4 islogic0 output 01 = C_4 islogic1 output 10 = Reserved 11 = C_4 islogicinput(default) C_3 [1:0]: C_3 terminalfunctionselect 00 = C_3 islogic0 output 01 = C_3 islogic1 output 10 = Reserved 11 = C_3 islogicinput(default) C_2 [1:0]: C_2 terminalfunctionselect 00 = C_2 islogic0 output 01 = C_2 islogic1 output 10 = Reserved 11 = C_2 islogicinput(default) Note:C_x functionsareavailableonlyinthe10-bitoutputmode.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-54.Output FormatterControl6 Register Subaddress 38h Default FFh 7 6 5 4 3 2 1 0 C_9 [1:0]: C_9 terminalfunctionselect 00 = C_9 islogic0 output 01 = C_9 islogic1 output 10 = Reserved 11 = C_9 islogicinput(default) C_8 [1:0]: C_8 terminalfunctionselect 00 = C_8 islogic0 output 01 = C_8 islogic1 output 10 = Reserved 11 = C_8 islogicinput(default) C_7 [1:0]: C_7 terminalfunctionselect 00 = C_7 islogic0 output 01 = C_7 islogic1 output 10 = Reserved 11 = C_7 islogicinput(default) C_6 [1:0]: C_6 terminalfunctionselect 00 = C_6 islogic0 output 01 = C_6 islogic1 output 10 = Reserved 11 = C_6 islogicinput(default) Table2-55.ClearLost Lock DetectRegister Subaddress 39h Default 00h 7 6 5 4 3 2 1 0 Reserved Clearlostlockdetect Clearlostlockdetect: Clearbit4 (lostlockdetect)inthestatus1 registeratsubaddress3Ah (seeTable2-56) 0 = No effect(default) 1 = Clearsbit4 inthestatus1 register Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 59 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-56.Status1 Register Subaddress 3Ah Read only 7 6 5 4 3 2 1 0 Peak white Line-alternating Fieldrate Lostlockdetect Color Verticalsync Horizontalsync TV/VCR status detectstatus status status subcarrierlock lockstatus lockstatus status Peak whitedetectstatus: 0 = Peak whiteisnotdetected 1 = Peak whiteisdetected Line-alternatingstatus: 0 = Non line-alternating 1 = Line-alternating Fieldratestatus: 0 = 60 Hz 1 = 50 Hz Lostlockdetect: 0 = No lostlocksincethisbitwas lastcleared 1 = Lostlocksincethisbitwas lastcleared Colorsubcarrierlockstatus: 0 = Colorsubcarrierisnotlocked 1 = Colorsubcarrierislocked Verticalsynclockstatus: 0 = Verticalsyncisnotlocked 1 = Verticalsyncislocked Horizontalsynclockstatus: 0 = Horizontalsyncisnotlocked 1 = Horizontalsyncislocked TV/VCR status: 0 = TV 1 = VCR

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-57.Status2 Register Subaddress 3Bh Read only 7 6 5 4 3 2 1 0 Reserved Weak signal PAL switch Fieldsequence Colorkilled Macrovisiondetection[2:0] detection polarity status Weak signaldetection: 0 = No weak signal 1 = Weak signalmode PAL switchpolarityoffirstlineofodd field: 0 = PAL switchis0b 1 = PAL switchis1b Fieldsequence status: 0 = Even field 1 = Odd field Colorkilled: 0 = Colorkillernotactive 1 = Colorkilleractivated Macrovisiondetection[2:0]: 000 = No copy protection 001 = AGC pulses/pseudosyncspresent(Type1) 010 = 2-linecolorstripeonlypresent 011 = AGC pulses/pseudosyncsand 2-linecolorstripepresent(Type2) 100 = Reserved 101 = Reserved 110 = 4-linecolorstripeonlypresent 111 = AGC pulses/pseudosyncsand 4-linecolorstripepresent(Type3) Table2-58.AGC Gain StatusRegister Subaddress 3Ch-3Dh Read only Subaddress 7 6 5 4 3 2 1 0 3Ch FineGain [7:0] 3Dh Coarse Gain [3:0] FineGain [11:8] Finegain[11:0]: Thisregisterprovidesthefinegainvalueofsyncchannel. 1111 1111 1111 = 1.9995 1000 0000 0000 = 1 0010 0000 0000 = 0.5 Coarse gain[3:0]: Thisregisterprovidesthecoarsegainvalueofsyncchannel. 1111 = 2 0101 = 1 0000 = 0.5 The AGC gainstatusregisterisupdatedautomaticallyby theTVP5146M2 decoderwhen AGC ison.Inmanual gaincontrolmode, these registervaluesarenotupdatedby theTVP5146M2 decoder. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 61 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-59.Video Standard StatusRegister Subaddress 3Fh Read only 7 6 5 4 3 2 1 0 Autoswitch Reserved Videostandard[2:0] Autoswitchmode 0 = Stand-alone(forcedvideostandard)mode 1 = Autoswitchmode enabled Videostandard[2:0]: CVBS and S-Video Component Video

000 Reserved Reserved

001 (M,J)NTSC Component 525 010 (B,D, G, H, I,N) PAL Component 625 011 (M)PAL Reserved 100 (Combination-N)PAL Reserved 101 NTSC 4.43 Reserved Thisregistercontainsinformationaboutthedetectedvideostandardthatthedeviceiscurrentlyoperating.When autoswitchcode is running,thisregistermust be testedtodeterminewhichvideostandardhas been detected. Table2-60.GPIO Input1 Register Subaddress 40h Read only 7 6 5 4 3 2 1 0 C_x inputstatus: 0 = Inputislow 1 = Inputishigh These statusbitsarevalidonlywhen terminalsareused as inputsand areupdatedateveryline.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-61.GPIO Input2 Register Subaddress 41h Read only 7 6 5 4 3 2 1 0 FSS AVID GLCO VS HS FID C_9 C_8 FSS inputterminalstatus: 0 = Inputisa low 1 = Inputisa high AVID inputterminalstatus: 0 = Inputisa low 1 = Inputisa high GLCO inputterminalstatus: 0 = Inputisa low 1 = Inputisa high VS inputterminalstatus: 0 = Inputisa low 1 = Inputisa high HS inputstatus: 0 = Inputisa low 1 = Inputisa high FID inputstatus: 0 = Inputisa low 1 = Inputisa high C_x inputstatus: 0 = Inputisa low 1 = Inputisa high These statusbitsarevalidonlywhen terminalsareused as inputsand areupdatedateveryline. Table2-62.VerticalLineCount Register Subaddress 42h-43h Read only Subaddress 7 6 5 4 3 2 1 0 3Ch V_CNT[7:0] 3Dh Reserved V_CNT[9:8] V_CNT[9:0]: Representsthedetectedtotalnumber oflinesfromthepreviousframe Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 63 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-63.AFE Coarse Gain forCH 1 Register Subaddress 46h Default 20h 7 6 5 4 3 2 1 0 CGAIN 1 [3:0] Reserved CGAIN 1 [3:0]: Coarse Gain = 0.5+ (CGAIN 1)/10where 0 ≤ CGAIN 1 ≤ 15 Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Table2-64.AFE Coarse Gain forCH 2 Register Subaddress 47h Default 20h 7 6 5 4 3 2 1 0 CGAIN 2 [3:0] Reserved CGAIN 2 [3:0]: Coarse Gain = 0.5+ (CGAIN 2)/10where 0 ≤ CGAIN 2 ≤ 15. Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-65.AFE Coarse Gain forCH 3 Register Subaddress 48h Default 20h 7 6 5 4 3 2 1 0 CGAIN 3 [3:0] Reserved CGAIN 3 [3:0]: Coarse Gain = 0.5+ (CGAIN 3)/10where 0 ≤ CGAIN 3 ≤ 15. Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Table2-66.AFE Coarse Gain forCH 4 Register Subaddress 49h Default 20h 7 6 5 4 3 2 1 0 CGAIN 4 [3:0] Reserved CGAIN 4 [3:0]: Coarse Gain = 0.5+ (CGAIN 4)/10where 0 ≤ CGAIN 4 ≤ 15. Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 65 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-67.AFE FineGain forPb_B Register Subaddress 4Ah-4Bh Default 900h Subaddress 7 6 5 4 3 2 1 0 4Ah FGAIN 1 [7:0] 4Bh Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: Thisfinegainappliestocomponent B/Pb. FineGain = (1/2048)× FGAIN 1,where 0 ≤ FGAIN 1 ≤ 4095 Thisregisterisonlyupdatedwhen theMSB (register4Bh) iswrittento. Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125(default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to0000 0000 0000 = Reserved Table2-68.AFE FineGain forY_G_Chroma Register Subaddress 4Ch-4Dh Default 900h Subaddress 7 6 5 4 3 2 1 0 4Ch FGAIN 2 [7:0] 4Dh Reserved FGAIN 2 [11:8] FGAIN 2 [11:0]: Thisgainappliestocomponent Y/G channelorS-videochroma. Fine_Gain= (1/2048)× FGAIN 2,where 0 ≤ FGAIN 2 ≤ 4095 Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125(default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to0000 0000 0000 = Reserved Table2-69.AFE FineGain forPr_R Register Subaddress 4Eh-4Fh Default 900h Subaddress 7 6 5 4 3 2 1 0 4Eh FGAIN 3 [7:0] 4Fh Reserved FGAIN 3 [11:8] FGAIN 3 [11:0]: Thisfinegainappliestocomponent Pb/B. Fine_Gain= (1/2048)× FGAIN 3,where 0 ≤ FGAIN 3 ≤ 4095 Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125(default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to0000 0000 0000 = Reserved

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-70.AFE FineGain forCVBS_Luma Register Subaddress 50h-51h Default 900h Subaddress 7 6 5 4 3 2 1 0 50h FGAIN 4 [7:0] 51h Reserved FGAIN 4 [11:8] FGAIN 4 [11:0]: ThisfinegainappliestoCVBS orS-videoluma. Fine_Gain= (1/2048)× FGAIN 4,where 0 ≤ FGAIN 4 ≤ 4095 Thisregisterworksonlyinmanual gaincontrolmode. When AGC isactive,writingtoany valueisignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125(default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to0000 0000 0000 = Reserved Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 67 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-71.F-Bitand V-BitDecode Control1 Register Subaddress 69h Default 00h 7 6 5 4 3 2 1 0 Reserved VPLL Adaptive Reserved F-bitMode [1:0] VPLL: VPLL timeconstantcontrol 0 = VPLL adaptsthetimeconstanttotheinputsignal(default) 1 = VPLL timeconstantsarefixed Adaptive: 0 = EnableF-bitand V-bitadaptationtodetectedlinesperframe(default) 1 = DisableF-bitand V-bitadaptationtodetectedlinesperframe F-bitmode: 00 = Automode. Iflinesperframeisstandarddecoded F and V bitsas perITU−R BT. 656 standardfromlinecount,decode F bitfrom VSYNC inputand setV-bit= 0 (default). 01 = Decode F and V bitsfrominputsyncs 10 = Reserved 11 = Alwaysdecode F and V bitsfromlinecount Thisregisterisused inconjunctionwiththeF-bitand V-bitcontrol2 register(subaddress75h)as indicated: REGISTER 69H REGISTER 75H STANDARD LPF NONSTANDARD LPFMODEBIT 1 BIT 0 BIT 3 BIT 2 F V F V 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 0 0 0 1 TVP5160 656 656 Toggle Switch9 0 0 1 0 TVP5160 656 656 Pulse 0 0 0 1 1 Reserved Reserved Reserved Reserved Reserved 0 1 0 0 Reserved Reserved Reserved Reserved Reserved 0 1 0 1 656 656 Toggle Switch9 0 1 1 0 656 656 Pulse 0 0 1 1 1 Reserved Reserved Reserved Reserved Reserved 1 0 0 0 Reserved Reserved Reserved Reserved Reserved 1 0 0 1 Reserved Reserved Reserved Reserved Reserved 1 0 1 0 Reserved Reserved Reserved Reserved Reserved 1 0 1 1 Reserved Reserved Reserved Reserved Reserved Even = 11 1 0 0 TVP5146 656 656 SwitchOdd = toggle 1 1 0 1 TVP5146 656 656 Toggle Switch 1 1 1 0 TVP5146 656 656 Pulse Switch 1 1 1 1 Reserved Reserved Reserved Reserved Reserved 656 = ITU-R BT.656 standard Toggle= Togglesfromfieldtofield Pulse= Pulseslowfor1 linepriortofieldtransition Switch= V bitswitcheshighbeforetheF-bittransitionand lowaftertheF-bittransition Switch9= V bitswitcheshigh1 linepriortotheF-bittransition,thenlowafterninelines Reserved= Not used

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-72.Back-End AGC ControlRegister Subaddress 6Ch Default 08h 7 6 5 4 3 2 1 0 Reserved 1 Peak Color Sync Thisregisterdisablestheback-endAGC when thefront-endAGC uses specificamplitudereferences(sync-height,colorburst,or compositepeak)todecrementthefront-endgain.Forexample,writing0x09 tothisregisterdisablestheback−end AGC when thefront-end AGC uses thesync-heighttodecrementthefront-endgain. Peak: Disablesback-endAGC when thefront-endAGC uses thecompositepeak as an amplitudereference. 0 = Disabled(default) 1 = Enabled Color: Disablesback-endAGC when thefront-endAGC uses thecolorburstas an amplitudereference. 0 = Disabled(default) 1 = Enabled Sync: Disablesback-endAGC when thefront-endAGC uses thesyncheightas an amplitudereference. 0 = Disabled(default) 1 = Enabled Table2-73.AGC Decrement Speed Register Subaddress 6Fh Default 04h 7 6 5 4 3 2 1 0 Reserved AGC decrementspeed [2:0] AGC decrementspeed: Adjustsgaindecrementspeed.Onlyused forcomposite/lumapeaks. 111 = 7 (slowest) 110 = 6 (default) 000 = 0 (fastest) Table2-74.ROM VersionRegister Subaddress 70h Read only 7 6 5 4 3 2 1 0 ROM version[7:0] ROM Version[7:0]: ROM revisionnumber Table2-75.RAM VersionMSB Register Subaddress 71h Read only 7 6 5 4 3 2 1 0 RAM versionMSB [7:0] RAM versionMSB [7:0]: ThisregisteridentifiestheMSB oftheRAM code revisionnumber. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 69 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-76.AGC White Peak ProcessingRegister Subaddress 74h Default 00h 7 6 5 4 3 2 1 0 Luma peak A Reserved ColorburstA Sync heightA Luma peak B Composite ColorburstB Sync heightB peak Luma peak A: Use oftheluma peak as a videoamplitudereferencefortheback-endfeed-forwardtypeAGC algorithm 0 = Enabled(default) 1 = Disabled ColorburstA: Use ofthecolorburstamplitudeas a videoamplitudereferencefortheback-end Note:Not availableforSECAM, component,and B/W videosources. 0 = Enabled(default) 1 = Disabled Sync heightA: Use ofthesyncheightas a videoamplitudereferencefortheback-endfeed-forwardtypeAGC algorithm 0 = Enabled(default) 1 = Disabled Luma peak B: Use oftheluma peak as a videoamplitudereferenceforfront-endfeedbacktypeAGC algorithm 0 = Enabled(default) 1 = Disabled Compositepeak: Use ofthecompositepeak as a videoamplitudereferenceforfront-endfeedbacktypeAGC algorithm Note:RequiredforCVBS and SCART (withcolorburst)videosources. 0 = Enabled(default) 1 = Disabled ColorburstB: Use ofthecolorburstamplitudeas a videoamplitudereferenceforfront-endfeedbacktypeAGC algorithm Note:Not availableforSECAM, component,and B/W videosources 0 = Enabled(default) 1 = Disabled Sync heightB: Use ofthesync-heightas a videoamplitudereferenceforfront-endfeedbacktypeAGC algorithm 0 = Enabled(default) 1 = Disabled Note:Ifall4 bitsofthelowernibblearesettologic1 (thatis,no amplitudereferenceselected),thenthefront-endanalogand digital gainsareautomaticallysettonominalvaluesof2 and 2304,respectively. Ifall4 bitsoftheuppernibblearesettologic1 (thatis,no amplitudereferenceselected),thentheback-endgainissetautomaticallyto unity. Iftheinputsyncheightisgreaterthan100% and theAGC-adjustedoutputvideoamplitudebecomes lessthan100%, thentheback-end scalefactorattemptstoincreasethecontrastintheback end torestorethevideoamplitudeto100%.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-77.F-Bitand V-BitControl2 Register Subaddress 75h Default 16h 7 6 5 4 3 2 1 0 Reserved Fastlock F and V [1:0] Phase detector HPLL Fastlock: Enablefastlockwhere verticalPLL isresetand a 2-secondtimerisinitializedwhen verticallockislost;duringtime-outthedetected inputVSYNC isoutput. 0 = Disabled 1 = Enabled(default) F and V [1:0] F AND V LINES PER FRAME F BIT V BIT Standard ITU-R BT 656 ITU-R BT 656

00 Nonstandardeven Forcedto1 Switchatfieldboundary

Nonstandardodd Toggles Switchatfieldboundary Standard ITU-R BT 656 ITU-R BT 65601 Nonstandard Toggles Switchatfieldboundary Standard ITU-R BT 656 ITU-R BT 65610 Nonstandard Pulsedmode Switchatfieldboundary

11 Reserved

Phase detector: Enableintegralwindow phase detector 0 = Disabled 1 = Enabled(default) HPLL: EnablehorizontalPLL tofreerun 0 = Disabled(default) 1 = Enabled Table2-78.VCR TrickMode ControlRegister Subaddress 76h Default 8Ah 7 6 5 4 3 2 1 0 Switchheader Horizontalshake threshold[6:0] Switchheader: When inVCR trickmode, theheadernoisyareaaroundthehead switchisskipped. 0 = Disabled 1 = Enabled(default) Horizontalshake threshold[6:0]: 000 0000 = Zerothreshold 000 1010 = 0Ah (default) 111 1111 = Largestthreshold Table2-79.HorizontalShake IncrementRegister Subaddress 77h Default 64h 7 6 5 4 3 2 1 0 Horizontalshake increment[7:0] Horizontalshake increment[7:0]: 000 0000 = 0 000 1010 = 64h (default) 111 1111 = FFh Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 71 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-80.AGC IncrementSpeed Register Subaddress 78h Default 06h 7 6 5 4 3 2 1 0 Reserved AGC incrementspeed [2:0] AGC incrementspeed [2:0]: Adjustsgainincrementspeed. 111 = 7 (slowest) 110 = 6 (default) 000 = 0 (fastest) Table2-81.AGC IncrementDelay Register Subaddress 79h Default 1Eh 7 6 5 4 3 2 1 0 AGC incrementdelay[7:0] AGC incrementdelay: Number offramestodelaygainincrements 1111 1111 = 255 0001 1110 = 30 (default) 0000 0000 = 0 Table2-82.Chip ID MSB Register Subaddress 80h Read only 7 6 5 4 3 2 1 0 CHIP ID MSB [7:0] CHIP ID MSB [7:0]: ThisregisteridentifiestheMSB ofthedeviceID.Value= 51h Table2-83.Chip ID LSB Register Subaddress 81h Read only 7 6 5 4 3 2 1 0 CHIP ID LSB [7:0] CHIP ID LSB [7:0]: ThisregisteridentifiestheLSB ofthedeviceID.Value= 46h

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-84.RAM VersionLSB Register Subaddress 82h Read only 7 6 5 4 3 2 1 0 RAM versionLSB [7:0] RAM versionLSB [7:0]: ThisregisteridentifiestheLSB oftheRAM code revisionnumber. Example: PatchRelease= v08.00.06 ROM Version= 08h RAM VersionMSB = 00h RAM VersionLSB = 06h Table2-85.ColorPLL Speed ControlRegister Subaddress 83h Default 09h 7 6 5 4 3 2 1 0 Reserved Speed [3:0] Speed [3:0]: ColorPLL speed control 1001 = Faster(default) 1010 = 1011 = Slower Other= Reserved Table2-86.StatusRequest Register Subaddress 97h Default 00h 7 6 5 4 3 2 1 0 Reserved Capture Capture: Settinga 1b inthisregistercausestheinternalprocessortocapturethecurrentsettingsoftheAGC statusand theverticallinecount registers.Because thiscaptureisnotimmediate,itisnecessarytocheckforcompletionofthecaptureby readingthecapturebit repeatedlyaftersettingitand waitingforittobe clearedby theinternalprocessor.Once thecapturebitis0b,theAGC statusand verticallinecounters(3Ch/3Dhand 9Ah/9Bh)have been updatedand can be safelyreadinany order. Table2-87.VerticalLineCount Register Subaddress 9Ah-9Bh Read only Subaddress 7 6 5 4 3 2 1 0 9Ah Verticalline[7:0] 9Bh Reserved Verticalline[9:8] Verticalline[9:0]: Representthedetecteda totalnumber oflinesfromthepreviousframe.Thiscan be used withnonstandardvideosignals,such as a VCR intrickmode, tosynchronizedownstream videocircuitry. Because thisregisterisa double-byteregister,itisnecessarytocapturethesettingintotheregistertoensurethatthevalueisnot updatedbetween readingthelowerand upperbytes.To cause thisregistertocapturethecurrentsettings,bit0 ofthestatusrequest register(subaddress97h)must be settoa 1b.Once theinternalprocessorhas updatedand can be read,eitherbytemay be readfirst, because no furtherupdatewilloccuruntilbit0 of97h issetto1b again. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 73 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-88.AGC Decrement Delay Register Subaddress 9Eh Default 1Eh 7 6 5 4 3 2 1 0 AGC decrementdelay[7:0] AGC decrementdelay: Number offramestodelaygaindecrements 1111 1111 = 255 0001 1110 = 30 (default) 0000 0000 = 0 Table2-89.VDP TTX Filterand Mask Register Subaddress B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh Default 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Subaddress 7 6 5 4 3 2 1 0 B1h Filter1 Mask 1 Filter1 Pattern1 B2h Filter1 Mask 2 Filter1 Pattern2 B3h Filter1 Mask 3 Filter1 Pattern3 B4h Filter1 Mask 4 Filter1 Pattern4 B5h Filter1 Mask 5 Filter1 Pattern5 B6h Filter2 Mask 1 Filter2 Pattern1 B7h Filter2 Mask 2 Filter2 Pattern2 B8h Filter2 Mask 3 Filter2 Pattern3 B9h Filter2 Mask 4 Filter2 Pattern4 BAh Filter2 Mask 5 Filter2 Pattern5 Foran NABTS system,thepacketprefixconsistsoffivebytes.Each bytecontainsfourdatabits(D[3:0])interlacedwithfourHamming protectionbits(H[3:0]): Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OnlythedataportionD[3:0]fromeach byteisappliedtoa teletextfilterfunctionwithcorrespondingpatternbitsP[3:0]and mask bitsM[3:0]. The filterignoreshamming protectionbits. Fora WST system(PAL orNTSC), thepacketprefixconsistsoftwo bytes.The two bytescontainthreebitsofmagazine number (M[2:0]) and fivebitsofrow address(R[4:0]),interlacedwitheightHamming protectionbitsH[7:0]: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 The mask bitsenablefilteringusingthecorrespondingbitinthepatternregister.Forexample,a 1 intheLSB ofmask 1 means thatthefilter module must compare theLSB ofnibble1 inthepatternregistertothefirstdatabiton thetransaction.Ifthesematch,thena trueresultis returned.A 0 ina bitofmask means thatthefiltermodule must ignorethatdatabitofthetransaction.Ifall0s areprogrammed inthemask bits,thenthefiltermatches allpatternsreturninga trueresult(default00h).

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-90.VDP TTX FilterControlRegister Subaddress BBh Default 00h 7 6 5 4 3 2 1 0 Reserved Filterlogic[1:0] Mode TTX filter2 TTX filter1 enable enable Filterlogic[1:0]: Allowdifferentlogictobe appliedwhen combiningthedecisionofFilter1 and Filter2 as follows: 00 = NOR (default) 01 = NAND 10 = OR 11 = AND Mode: Indicateswhichteletextmode isinuse: 0 = Teletextfilterappliesto2 headerbytes(default) 1 = Teletextfilterappliesto5 headerbytes TTX filter2 enable: ProvidesforenablingtheteletextfilterfunctionwithintheVDP. 0 = Disable(default) 1 = Enable TTX filter1 enable: ProvidesforenablingtheteletextfilterfunctionwithintheVDP. 0 = Disable(default) 1 = Enable Ifthefiltermatches orifthefiltermask isallzeros,thena trueresultisreturned. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 75 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

1P1[3] 1M1[0] 1M1[1] 1M1[2] 1M1[3] NIBBLE 1 FILTER 2 FILTER 1 PASS 1 Filter 1 Enable Filter Logic PASS 1P1[2] 1P1[1] 1P1[0] D1[3] D1[2] D1[1] D1[0] NIBBLE 2 D2[3:0] 1P2[3:0] 1M2[3:0] NIBBLE 3 NIBBLE 4 NIBBLE 5 D3[3:0] 1P3[3:0] 1M3[3:0] D4[3:0] 1P4[3:0] 1M4[3:0] D5[3:0] 1P5[3:0] 1M5[3:0] D1..D5 2P1..2P5 2M1..2M5 PASS 2 Filter 2 Enable TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Figure2-21.TeletextFilterFunction Table2-91.VDP FIFO Word Count Register Subaddress BCh Read only 7 6 5 4 3 2 1 0 FIFO word count[7:0] FIFO word count[7:0]: Thisregisterprovidesthenumber ofwords intheFIFO. Note:1 word equals2 bytes.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-92.VDP FIFO InterruptThresholdRegister Subaddress BDh Default 80h 7 6 5 4 3 2 1 0 Threshold[7:0] Threshold[7:0]: Thisregisterisprogrammed totriggeran interruptwhen thenumber ofwords intheFIFO exceedsthisvalue. Note:1 word equals2 bytes. Table2-93.VDP FIFO Reset Register Subaddress BFh Default 00h 7 6 5 4 3 2 1 0 Reserved FIFO reset FIFO reset: Writingany datatothisregisterclearstheFIFO and VDP dataregisters(CC,WSS/CGMS, VITC,and VPS/Gemstar).Afterclearing them,thisregisterisautomaticallycleared. Table2-94.VDP FIFO Output ControlRegister Subaddress C0h Default 00h 7 6 5 4 3 2 1 0 Reserved Hostaccess enable Hostaccessenable: Thisregisterisprogrammed toallowthehostportaccesstotheFIFO ortoallowallVDP datatogo outthevideooutput. 0 = OutputFIFO datatothevideooutputY_9:2 1 = AllowhostportaccesstotheFIFO data Table2-95.VDP LineNumber InterruptRegister Subaddress C1h Default 00h 7 6 5 4 3 2 1 0 Field1 enable Field2 enable Linenumber [5:0] Field1 interruptenable: 0 = Interruptdisabled(default) 1 = Interruptenabled Field2 interruptenable: 0 = Interruptdisabled(default) 1 = Interruptenabled Linenumber [5:0]: Interruptlinenumber (default00h) Thisregisterisprogrammed totriggeran interruptwhen thevideolinenumber exceedsthisvalueinbits[5:0].Thisinterruptmust be enabledataddressF4h. Note:The linenumber valueofzeroorone isinvalidand does notgeneratean interrupt. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 77 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-96.VDP PixelAlignment Register Subaddress C2h-C3h Default 01Eh Subaddress 7 6 5 4 3 2 1 0 C2h Pixelalignment[7:0] C3h Reserved Pixelalignment[9:0] Pixelalignment[9:0]: These registersforma 10-bithorizontalpixelpositionfromthefallingedge ofhorizontalsync,where theVDP controllerinitiatesthe programfromone linestandardtothenextlinestandard.Forexample,thepreviouslineofteletexttothenextlineofclosedcaption. Thisvaluemust be setso thattheswitchoccursaftertheprevioustransactionhas clearedthedelayintheVDP, butearlyenough to allowthenew valuestobe programmed beforethecurrentsettingsarerequired. The defaultvalueis0x1E and has been testedwitheverystandardsupportedhere.A new valueisneeded onlyifa custom standardis inuse. Table2-97.VDP LineStartRegister Subaddress D6h Default 06h 7 6 5 4 3 2 1 0 VDP linestart[7:0] VDP linestart[7:0]: SetstheVDP linestartingaddress Thisregistermust be setproperlybeforeenablingthelinemode registers.VDP processorworksonlyintheVBI regionsetby this registerand theVDP linestopregisteratsubaddressD7h. Table2-98.VDP LineStop Register Subaddress D7h Default 1Bh 7 6 5 4 3 2 1 0 VDP linestop[7:0] VDP linestop[7:0]: SetstheVDP stoplineaddress Table2-99.VDP GlobalLineMode Register Subaddress D8h Default FFh 7 6 5 4 3 2 1 0 Globallinemode [7:0] Globallinemode [7:0]: VDP processingformultiplelinessetby theVDP startlineregisteratsubaddressD6h and theVDP stoplineregisteratsubaddress D7h. Globallinemode registerhas thesame bitdefinitionsas thelinemode registers(seeTable2-121). Generallinemode has priorityoverthegloballinemode.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-100.VDP FullFieldEnable Register Subaddress D9h Default 00h 7 6 5 4 3 2 1 0 Reserved Fullfieldenable Fullfieldenable: 0 = Disabledfullfieldmode(default) 1 = Enabledfullfieldmode Thisregisterenablesthefullfieldmode. Inthismode, alllinesoutsidetheverticalblankareaand alllinesinthelinemode register programmed withFFh areslicedwiththedefinitionoftheVDP fullfieldmode registeratsubaddressDAh. ValuesotherthanFFh inthe linemode registersallowa differentslicemode forthatparticularline. Table2-101.VDP FullFieldMode Register Subaddress DAh Default FFh 7 6 5 4 3 2 1 0 Fullfieldmode [7:0] Fullfieldmode [7:0]: ThisregisterprogramsthespecificVBI standardforfullfieldmode. Itcan be any VBI standard.Individuallinesettingstakepriorityover thefullfieldregister.Thisallowseach VBI linetobe programmed independentlybuthave theremaininglinesinfullfieldmode. The full fieldmode registerhas thesame bitdefinitionas linemode registers(defaultFFh). Globallinemode has priorityoverthefullfieldmode. Table2-102.VBUS Data Access With No VBUS Address IncrementRegister Subaddress E0h Default 00h 7 6 5 4 3 2 1 0 VBUS data[7:0] VBUS data[7:0]: VBUS dataregisterforVBUS singlebyteread/writetransaction. Table2-103.VBUS Data Access With VBUS Address IncrementRegister Subaddress E1h Default 00h 7 6 5 4 3 2 1 0 VBUS data[7:0] VBUS data[7:0]: VBUS dataregisterforVBUS multi-byteread/writetransaction.VBUS addressisauto-incrementedaftereach databyteread/write. Table2-104.FIFO Read Data Register Subaddress E2h Read only 7 6 5 4 3 2 1 0 FIFO Read Data [7:0] FIFO Read Data [7:0]: ThisregisterisprovidedtoaccessVBI FIFO datathroughthehostport.Allformsofteletextdatacome directlyfromtheFIFO,whileall otherformsofVBI datacan be programmed tocome fromregistersorfromtheFIFO.Ifthehostportistobe used toreaddatafrom theFIFO,bit0 (hostaccessenable)intheVDP FIFO outputcontrolregisteratsubaddressC0h must be setto1 (seeTable2-94). Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 79 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-105.VBUS Address Register Subaddress E8h E9h EAh Default 00h 00h 00h Subaddress 7 6 5 4 3 2 1 0 E8h VBUS address[7:0] E9h VBUS address[15:8] EAh VBUS address[23:16] VBUS address[23:0]: VBUS isa 24-bitwideinternalbus.The usermust programintheseregistersthe24-bitaddressoftheinternalregistertobe accessed viahostportindirectaccessmode. Table2-106.InterruptRaw Status0 Register Subaddress F0h Read only 7 6 5 4 3 2 1 0 FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line The hostInterruptRaw Status0 and InterruptRaw Status1 registersrepresenttheinterruptstatuswithoutapplyingmask bits. See alsotheinterruptraw status1 registeratsubaddressF1h (Table2-107). FIFO THRS: FIFO thresholdpassed,unmasked 0 = Not passed 1 = Passed TTX: Teletextdataavailableunmasked 0 = Not available 1 = Available WSS/CGMS: WSS/CGMS dataavailableunmasked 0 = Not available 1 = Available VPS/Gemstar: VPS/Gemstar dataavailableunmasked 0 = Not available 1 = Available VITC: VITC dataavailableunmasked 0 = Not available 1 = Available CC F2: CC field2 dataavailableunmasked 0 = Not available 1 = Available CC F1: CC field1 dataavailableunmasked 0 = Not available 1 = Available Line: Linenumber interruptunmasked 0 = Not available 1 = Available

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-107.InterruptRaw Status1 Register Subaddress F1h Read only 7 6 5 4 3 2 1 0 Reserved Macrovision Standard FIFO full statuschanged changed Macrovisionstatuschanged: unmasked 0 = Macrovisionstatusunchanged 1 = Macrovisionstatuschanged Standardchanged: unmasked 0 = Videostandardunchanged 1 = Videostandardchanged FIFO full: 0 = FIFO notfull 1 = FIFO was fullduringwritetoFIFO The FIFO fullerrorflagissetwhen thecurrentlineofVBI datacannotentertheFIFO.Forexample,iftheFIFO has only10 bytesleft and teletextisthecurrentVBI line,theFIFO fullerrorflagisset,butno dataiswrittenbecause theentireteletextlinedoes notfit. However,ifthenextVBI lineisclosedcaptionrequiringonly2 bytesofdataplustheheader,thisgoes intotheFIFO even ifthefull errorflagisset. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 81 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-108.InterruptStatus0 Register Subaddress F2h Read only 7 6 5 4 3 2 1 0 FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line InterruptStatus0 and InterruptStatus1 (seeTable2-109)registersrepresenttheinterruptstatusafterapplyingmask bits.Therefore,the statusbitsaretheresultofa logicalAND between theraw statusand mask bits.The externalinterruptterminalisderivedfromthisregister as an OR functionofallnonmasked interruptsinthisregister. Readingdatafromthecorrespondingregisterdoes notclearthestatusflagsautomatically.These flagsareresetusingthecorresponding bitsintheInterruptClear0 and InterruptClear1 registers. FIFO THRS: FIFO thresholdpassed,masked 0 = Not passed 1 = Passed TTX: Teletextdataavailablemasked 0 = Not available 1 = Available WSS/CGMS: WSS/CGMS dataavailablemasked 0 = Not available 1 = Available VPS/Gemstar: VPS/Gemstar dataavailablemasked 0 = Not available 1 = Available VITC: VITC dataavailablemasked 0 = Not available 1 = Available CC F2: CC field2 dataavailablemasked 0 = Not available 1 = Available CC F1: CC field1 dataavailablemasked 0 = Not available 1 = Available Line: Linenumber interruptmasked 0 = Not available 1 = Available

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-109.InterruptStatus1 Register Subaddress F3h Read only 7 6 5 4 3 2 1 0 Reserved Macrovision Standard FIFO full statuschanged changed Macrovisionstatuschanged: Macrovisionstatuschanged masked 0 = Macrovisionstatusnotchanged 1 = Macrovisionstatuschanged Standardchanged: Standardchanged masked 0 = Videostandardnotchanged 1 = Videostandardchanged FIFO full: Masked statusofFIFO 0 = FIFO notfull 1 = FIFO was fullduringwritetoFIFO,see theinterruptmask 1 registeratsubaddressF5h fordetails(seeTable2-111) Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 83 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-110.InterruptMask 0 Register Subaddress F4h Read only 7 6 5 4 3 2 1 0 FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line The hostInterruptMask 0 and InterruptMask 1 (seeTable2-111)registerscan be used by theexternalprocessortomask unnecessary interruptsourcesfortheInterruptStatus0 and InterruptStatus1 registerbits,and fortheexternalinterruptterminal.The externalinterrupt isgeneratedfromallnonmasked interruptflags. FIFO THRS: FIFO thresholdpassed mask 0 = Disabled(default) 1 = EnabledFIFO_THRES interrupt TTX: Teletextdataavailablemask 0 = Disabled(default) 1 = EnabledTTX availableinterrupt WSS/CGMS: WSS/CGMS dataavailablemask 0 = Disabled(default) 1 = EnabledWSS/CGMS availableinterrupt VPS/Gemstar: VPS/Gemstar dataavailablemask 0 = Disabled(default) 1 = EnabledVPS/Gemstar availableinterrupt VITC: VITC dataavailablemask 0 = Disabled(default) 1 = EnabledVITC availableinterrupt CC F2: CC field2 dataavailablemask 0 = Disabled(default) 1 = EnabledCC field2 availableinterrupt CC F1: CC field1 dataavailablemask 0 = Disabled(default) 1 = EnabledCC field1 availableinterrupt LINE: Linenumber interruptmask 0 = Disabled(default) 1 = EnabledLine_INTinterrupt

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-111.InterruptMask 1 Register Subaddress F5h Read only 7 6 5 4 3 2 1 0 Reserved Macrovision Standard FIFO full statuschanged changed Macrovisionstatuschanged: Macrovisionstatuschanged mask 0 = Macrovisionstatusunchanged 1 = Macrovisionstatuschanged Standardchanged: Standardchanged mask 0 = Disabled(default) 1 = Enabledvideostandardchanged FIFO full: FIFO fullmask 0 = Disabled(default) 1 = EnabledFIFO fullinterrupt Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 85 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-112.InterruptClear0 Register Subaddress F6h Read only 7 6 5 4 3 2 1 0 FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line The hostInterruptClear0 and InterruptClear1 (seeTable2-113)registersareused by theexternalprocessortocleartheinterruptstatus bitsinthehostInterruptStatus0 and InterruptStatus1 registers.When no nonmasked interruptsremainsetintheregisters,theexternal interruptterminalalsobecomes inactive. FIFO THRS: FIFO thresholdpassed clear 0 = No effect(default) 1 = ClearFIFO_THRES bitinstatusregister0 bit7 TTX: Teletextdataavailableclear 0 = No effect(default) 1 = ClearTTX availablebitinstatusregister0 bit6 WSS/CGMS: WSS/CGMS dataavailableclear 0 = No effect(default) 1 = ClearWSS/CGMS availablebitinstatusregister0 bit5 VPS/Gemstar: VPS/Gemstar dataavailableclear 0 = No effect(default) 1 = ClearVPS/Gemstar availablebitinstatusregister0 bit4 VITC: VITC dataavailableclear 0 = Disabled(default) 1 = ClearVITC availablebitinstatusregister0 bit3 CC F2: CC field2 dataavailableclear 0 = Disabled(default) 1 = ClearCC field2 availablebitinstatusregister0 bit2 CC F1: CC field1 dataavailableclear 0 = Disabled(default) 1 = ClearCC field1 availablebitinstatusregister0 bit1 LINE: Linenumber interruptclear 0 = Disabled(default) 1 = ClearLineinterruptavailablebitinstatusregister0 bit0

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-113.InterruptClear1 Register Subaddress F7h Read only 7 6 5 4 3 2 1 0 Reserved Macrovision Standard FIFO full statuschanged changed Macrovisionstatuschanged: ClearMacrovisionstatuschanged flag 0 = No effect(default) 1 = Clearbit2 (Macrovisionstatuschanged)intheinterruptstatus1 registeratsubaddressF3h and theinterruptraw status1 register atsubaddressF1h Standardchanged: Clearstandardchanged flag 0 = No effect(default) 1 = Clearbit1 (videostandardchanged)intheinterruptstatus1 registeratsubaddressF3h and theinterruptraw status1 registerat subaddressF1h FIFO full: ClearFIFO fullflag 0 = No effect(default) 1 = Clearbit0 (FIFOfullflag)intheinterruptstatus1 registeratsubaddressF3h and theinterruptraw status1 registeratsubaddress F1h Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 87 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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2.12 VBUS RegisterDefinitions

Table2-114.VDP Closed CaptionData Register Subaddress 80 051Ch -80 051Fh Read only Subaddress 7 6 5 4 3 2 1 0 80 051Ch ClosedCaptionField1 byte1 80 051Dh ClosedCaptionField1 byte2 80 051Eh ClosedCaptionField2 byte1 80 051Fh ClosedCaptionField2 byte2 These registerscontaintheclosedcaptiondataarrangedinbytesperfield. Table2-115.VDP WSS Data Register Subaddress 80 0520h -80 0526h Read only WSS/CGMS NTSC (CGMS) Subaddress 7 6 5 4 3 2 1 0 Byte 80 0520h b5 b4 b3 b2 b1 b0 WSS/CGMS Field1 Byte1 80 0521h b13 b12 b11 b10 b9 b8 b7 b6 WSS/CGMS Field1 Byte2 80 0522h b19 b18 b17 b16 b15 b14 WSS/CGMS Field1 Byte3 80 0523h Reserved 80 0524h b5 b4 b3 b2 b1 b0 WSS/CGMS Field2 Byte1 80 0525h b13 b12 b11 b10 b9 b8 b7 b6 WSS/CGMS Field2 Byte2 80 0526h b19 b18 b17 b16 b15 b14 WSS/CGMS Field2 Byte3 These registerscontainthewidescreensignalingdataforNTSC. Bits0 to1 representword 0,aspectratio Bits2 to5 representword 1,headercode forword 2 Bits6 to13 representword 2,copy control Bits14 to19 representword 3,CRC WSS/CGMS PAL/SECAM Subaddress 7 6 5 4 3 2 1 0 Byte 80 0520h b7 b6 b5 b4 b3 b2 b1 b0 WSS/CGMS Field1 Byte1 80 0521h b13 b12 b11 b10 b9 b8 WSS/CGMS Field1 Byte2 80 0522h Reserved 80 0523h Reserved 80 0524h b7 b6 b5 b4 b3 b2 b1 b0 WSS/CGMS Field2 Byte1 80 0525h b13 b12 b11 b10 b9 b8 WSS/CGMS Field2 Byte2 80 0526h Reserved These registerscontainthewidescreensignalingdataforPAL/SECAM: Bits0 to3 representGroup 1,AspectRatio Bits4 to7 representGroup 2,Enhanced Services Bits8 to10 representGroup 3,Subtitles Bits11 to13 representGroup 4,Others

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-116.VDP VITC Data Register Subaddress 80 052Ch -80 0534h Read only Subaddress 7 6 5 4 3 2 1 0 80 052Ch VITC framebyte1 80 052Dh VITC framebyte2 80 052Eh VITC secondsbyte1 80 052Fh VITC secondsbyte2 80 0530h VITC minutesbyte1 80 0531h VITC minutesbyte2 80 0532h VITC hoursbyte1 80 0533h VITC hoursbyte2 80 0534h VITC CRC byte These registerscontaintheVITC data. Table2-117.VDP V-Chip TV RatingBlock 1 Register Subaddress 80 0540h Read only 7 6 5 4 3 2 1 0 Reserved 14-D PG-D Reserved MA-L 14-L PG-L Reserved TV ParentalGuidelinesRatingBlock3 14-D:When incomingvideoprogramisTV-14-D rated,thisbitissethigh. PG-D: When incomingvideoprogramisTV-PG-D rated,thisbitissethigh. MA-L: When incomingvideoprogramisTV-MA-L rated,thisbitissethigh. 14-L:When incomingvideoprogramisTV-14-Lrated,thisbitissethigh. PG-L:When incomingvideoprogramisTV-PG-L rated,thisbitissethigh. Table2-118.VDP V-Chip TV RatingBlock 2 Register Subaddress 80 0541h Read only 7 6 5 4 3 2 1 0 MA-S 14-S PG-S Reserved MA-V 14-V PG-V Y7-FV TV ParentalGuidelinesRatingBlock2 MA-S: When incomingvideoprogramisTV-MA-S rated,thisbitissethigh. 14-S:When incomingvideoprogramisTV-14-Srated,thisbitissethigh. PG-S: When incomingvideoprogramisTV-PG-S rated,thisbitissethigh. MA-V: When incomingvideoprogramisTV-MA-V rated,thisbitissethigh. 14-V:When incomingvideoprogramisTV-14-Vrated,thisbitissethigh. PG-V: When incomingvideoprogramisTV-PG-S rated,thisbitissethigh. Y7-FV:When incomingvideoprogramisTV-Y7-FV rated,thisbitissethigh. Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 89 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-119.VDP V-Chip TV RatingBlock 3 Register Subaddress 80 0542h Read only 7 6 5 4 3 2 1 0 None TV-MA TV-14 TV-PG TV-G TV-Y7 TV-Y None TV ParentalGuidelinesRatingBlock1 None: No blockintended TV-MA: When incomingvideoprogramisTV-MA ratedinTV ParentalGuidelinesRating,thisbitissethigh. TV-14:When incomingvideoprogramisTV-14 ratedinTV ParentalGuidelinesRating,thisbitissethigh. TV-PG: When incomingvideoprogramisTV-PG ratedinTV ParentalGuidelinesRating,thisbitissethigh. TV-G: When incomingvideoprogramisTV-G ratedinTV ParentalGuidelinesRating,thisbitissethigh. TV-Y7:When incomingvideoprogramisTV-Y7 ratedinTV ParentalGuidelinesRating,thisbitissethigh. TV-Y:When incomingvideoprogramisTV-G ratedinTV ParentalGuidelinesRating,thisbitissethigh. Table2-120.VDP V-Chip MPAA RatingData Register Subaddress 80 0543h Read only 7 6 5 4 3 2 1 0 Not Rated X NC-17 R PG-13 PG G NA MPAA RatingBlock(E5h) Not Rated:When incomingvideoprogramisNot Rated ratedinMPAA Rating,thisbitissethigh. X:When incomingvideoprogramisX ratedinMPAA Rating,thisbitissethigh. NC-17:When incomingvideoprogramisNC-17 ratedinMPAA Rating,thisbitissethigh. R: When incomingvideoprogramisR ratedinMPAA Rating,thisbitissethigh. PG-13:When incomingvideoprogramisPG-13 ratedinMPAA Rating,thisbitissethigh. PG: When incomingvideoprogramisPG ratedinMPAA Rating,thisbitissethigh. G: When incomingvideoprogramisG ratedinMPAA Rating,thisbitissethigh. N/A:When incomingvideoprogramisN/A ratedinMPAA Rating,thisbitissethigh.

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www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012 Table2-121.VDP GeneralLineMode and LineAddress Register Subaddress 80 0600h -80 0611h Defaultlinemode = FFh,lineaddress= 00h Subaddress 7 6 5 4 3 2 1 0 80 0600h Lineaddress1 80 0601h Linemode 1 80 0602h Lineaddress2 80 0603h Linemode 2 80 0604h Lineaddress3 80 0605h Linemode 3 80 0606h Lineaddress4 80 0607h Linemode 4 80 0608h Lineaddress5 80 0609h Linemode 5 80 060Ah Lineaddress6 80 060Bh Linemode 6 80 060Ch Lineaddress7 80 060Dh Linemode 7 80 060Eh Lineaddress8 80 060Fh Linemode 8 80 0610h Lineaddress9 80 0611h Linemode 9 Lineaddress[7:0]: Linenumber tobe processedby a VDP setby a linemode register(default00h) Linemode x [7:0] Bit7 0 = Disabledfilters 1 = Enabledfiltersforteletextand CC (nullbytefilter)(default) Bit6 0 = Send slicedVBI datatoregistersonly 1 = Send slicedVBI datatoFIFO and registers,teletextdataonlygoes toFIFO (default) Bit5 0 = AllowVBI datawitherrorsintheFIFO 1 = Do notallowVBI datawitherrorsintheFIFO (default) Bit4 0 = Disablederrordetectionand correction 1 = Enablederrordetectionand correction(teletextonly)(default) Bit3 0 = Field1 1 = Field2 (default) Bit[2:0] 000 = Teletext(WST625, ChineseTeletext,NABTS 525) 001 = CC (US,European,Japan,China) 010 = WSS/CGMS (525,625) 011 = VITC 100 = VPS (PAL only),Gemstar (NTSC only) 101 = USER 1 110 = USER 2 111 = Reserved(activevideo)(default) Copyright© 2005–2012,Texas InstrumentsIncorporated FunctionalDescription 91 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com Table2-122.VDP VPS/Gemstar Data Register Subaddress 80 0700h -80 070Ch Read only VPS Subaddress 7 6 5 4 3 2 1 0 80 0700h VPS byte1 80 0701h VPS byte2 80 0702h VPS byte3 80 0703h VPS byte4 80 0704h VPS byte5 80 0705h VPS byte6 80 0706h VPS byte7 80 0707h VPS byte8 80 0708h VPS byte9 80 0709h VPS byte10 80 070Ah VPS byte11 80 070Bh VPS byte12 80 070Ch VPS byte13 These registerscontaintheentireVPS datalineexcepttheclockrun-incode and theframecode. Gemstar Subaddress 7 6 5 4 3 2 1 0 80 0700h Gemstar Frame Code 80 0701h Gemstar byte1 80 0702h Gemstar byte2 80 0703h Gemstar byte3 80 0704h Gemstar byte4 80 0705h Reserved 80 0706h Reserved 80 0707h Reserved 80 0708h Reserved 80 0709h Reserved 80 070Ah Reserved 80 070Bh Reserved 80 070Ch Reserved Table2-123.InterruptConfigurationRegister Subaddress B0 0060h Default 00h 7 6 5 4 3 2 1 0 Reserved Polarity Reserved Polarity: Interruptterminalpolarity 0 = Activehigh(default) 1 = Activelow

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3 ElectricalSpecifications

3.1 AbsoluteMaximum Ratings

overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT IOVDD toIOGND 0.5 4 V DVDD toDGND –0.2 2 V Supplyvoltagerange A33VDD (2)toA33GND (3) –0.3 3.6 V A18VDD (4)toA18GND (5) –0.2 2 V VItoDGND Digitalinputvoltagerange –0.5 4.5 V VO toDGND Digitaloutputvoltagerange –0.5 4.5 V AIN toAGND Analoginputvoltagerange –0.2 2 V Commercial 0 70 TA Operatingfree-airtemperature °C Industrial −40 85 Tstg Storagetemperature –65 150 °C (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) CH1_A33VDD, CH2_A33VDD, CH3_A33VDD, CH4_A33VDD (3) CH1_A33GND, CH2_A33GND, CH3_A33GND, CH4_A33GND (4) CH1_A18VDD, CH2_A18VDD, CH3_A18VDD, CH4_A18VDD, A18VDD_REF, PLL_A18VDD (5) CH1_A18GND, CH2_A18GND, CH3_A18GND, CH4_A18GND

3.2 Recommended OperatingConditions

IOVDD Supplyvoltage,digital 3 3.3 3.6 V Commercial 1.65 1.8 1.95 DV DD Supplyvoltage,digital V Industrial 1.7 1.8 1.9 AV DD33 Supplyvoltage,analog 3 3.3 3.6 V Commercial 1.65 1.8 1.95 AV DD18 Supplyvoltage,analog V Industrial 1.7 1.8 1.9 VI(P-P) Analoginputvoltage,analog(ac-couplingnecessary) 0.5 1 2 V VIH Inputvoltagehigh,digital(1) 0.7IOVDD V VIL Inputvoltagelow,digital(2) 0.3IOVDD V IOH High-leveloutputcurrent(3) VOUT = 2.4V –4 –8 mA IOL Low-leveloutputcurrent VOUT = 2.4V 6 8 mA Commercial 0 70 TA Operatingfree-airtemperature °C Industrial –40 85 (1) Exception:0.7AV DD18 forXTAL1 terminal (2) Exception:0.3AV DD18 forXTAL1 terminal (3) Currentsoutofa terminalaregivenas a negativenumber

3.3 CrystalSpecifications

Frequency 14.31818 MHz Frequencytolerance(1) ±50 ppm (1) Thisnumber istherequiredspecificationfortheexternalcrystal/oscillatorand isnottested. Copyright© 2005–2012,Texas InstrumentsIncorporated ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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3.4 ElectricalCharacteristics

Forminimum/maximum values: IOVDD = 3 V to3.6V,AV DD33 = 3 V to3.6V, Commercial:AV DD18 = 1.65V to1.95V,DV DD = 1.65V to1.95V,TA = 0°C to70°C Industrial:AV DD18 = 1.7V to1.9V,DV DD = 1.7V to1.9V,TA = −40°C to85°C Fortypicalvalues: IOVDD = AV DD33 = 3.3V,AV DD18 = DV DD = 1.8V,TA = 25°C

3.5 DC ElectricalCharacteristics(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CVBS 6 IDDIO(D) 3.3-VIO digitalsupplycurrent mA RGB and CVBS 6 CVBS 66 IDD(D) 1.8-Vdigitalsupplycurrent mA RGB and CVBS 67 CVBS 16 IDD(33A) 3.3-Vanalogsupplycurrent mA RGB and CVBS 48 CVBS 79 IDD(18A) 1.8-Vanalogsupplycurrent mA S-Video 240 CVBS 335 PTOT Totalpower dissipation,normaloperation mW S-Video 730 PSAVE Totalpower dissipation,power save 100 mW PDOWN Totalpower dissipation,power down 11 mW Ilkg Inputleakagecurrent 10 µA C I Inputcapacitance(2) 8 pF VOH Outputvoltagehigh(2) 0.8IOVDD V VOL Outputvoltagelow(2) 0.2IOVDD V (1) Measured witha loadof10 kΩ inparallelto15 pF. (2) Specifiedby design

3.6 Analog Processingand A/D Converters

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Zi Inputimpedance,analogvideoinputs(1) 200 kΩ C i Inputcapacitance,analogvideoinputs(1) 10 pF Vi(PP) Inputvoltagerange C coupling= 47 nF 0.5 1 2 V ΔG Gain controlrange(1) –6 6 dB DNL Differentialnonlinearity AFE only –1 ±0.75 +1 LSB INL Integralnonlinearity AFE only –2.5 ±1 +2.5 LSB FR Frequencyresponse Multiburst(60IRE) –0.9 dB XTALK Crosstalk(2) 1 MHz –50 dB SNR Signal-to-noiseratio,allchannels 1 MHz, 1 VPP 54 dB GM Gain match(1)(3) Fullscale,1 MHz 1.1 1.5 % NS Noisespectrum Luma ramp (100kHz tofull,tiltnull) –58 dB DP Differentialphase Modulatedramp 0.5 ° DG Differentialgain Modulatedramp ±1.5 % (1) Specifiedby design (2) By characterizationonly (3) Component inputsonly

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Y, C, AVID, VS, HS, FID VOH VOL Valid Data Valid Data VOH VOL Stop Start VC1 (SDA) VC0 (SCL) Data Stop Change Data TVP5146M2 www.ti.com SLES141H –JULY 2005–REVISED FEBRUARY 2012

3.7 Clocks,Video Data,Sync Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dutycycle,DATACLK 45 50 55 % t1 Hightime,DATACLK 18.5 ns t2 Low time,DATACLK 18.5 ns t3 Falltime,DATACLK 90% to10% 4 ns t4 Risetime,DATACLK 10% to90% 4 ns Commercial 10 t5 Outputdelaytime ns Industrial 12 Figure3-1.Clocks,Video Data,and Sync Timing

3.8 I2C Host PortTiming

PARAMETER MIN TYP MAX UNIT t1 Bus freetimebetween STOP and START 1.3 µs t2 Data holdtime 0 0.9 µs t3 Data setuptime 100 ns t4 Setuptimefora (repeated)START condition 0.6 µs t5 Setuptimefora STOP condition 0.6 ns t6 Holdtime(repeated)START condition 0.6 µs t7 RisetimeVC1(SDA) and VC0(SCL) signal 250 ns t8 FalltimeVC1(SDA) and VC0(SCL) signal 250 ns C b Capacitiveloadforeach bus line 400 pF fI2C I2C clockfrequency 400 kHz Figure3-2.I2C Host PortTiming Copyright© 2005–2012,Texas InstrumentsIncorporated ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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3.9 Thermal Specifications

PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Junction-to-ambientthermalresistance,θJA Thermalpad solderedto4-layerHigh-KPCB 19.04 °C/Wstillair Junction-to-casethermalresistance,stillθJC Thermalpad solderedto4-layerHigh-KPCB 0.17 °C/Wair Maximum junctiontemperatureforTJ(MAX) 105 °Creliableoperation (1) The exposed thermalpad must be solderedtoa High-KPCB withadequategroundplane.

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4 Example RegisterSettings

The followingexample registersettingsare providedonly as a reference.These settings,given the assumed inputconnector,videoformat,and outputformat,setup theTVP5146M2 decoderand provide videooutput.Example registersettingsforotherfeaturesand the VBI data processorare not provided here.

4.1 Example 1

4.1.1 Assumptions

Inputconnector:Composite(VI_1_A)(default) Videoformat: NTSC (J,M),PAL (B,G, H, I,N),orSECAM (default) Note: NTSC-443, PAL-Nc, and PAL-M are masked from the autoswitchprocessby default.See theautoswitchmask registerataddress04h. Outputformat: 10-bitITU-R BT.656 withembedded syncs(default)

4.1.2 Recommended Settings

Recommended I2C writes:Forthegivenassumptions,onlyone writeisrequired.Allotherregistersareset up by default. I2C registeraddress08h = Luminance processingcontrol3 register I2C data00h = OptimizesthetrapfilterselectionforNTSC and PAL I2C registeraddress0Eh = Chrominanceprocessingcontrol2 register I2C data04h = OptimizesthechrominancefilterselectionforNTSC and PAL I2C registeraddress34h = Outputformatter2 register I2C data11h = EnablesYCbCr outputand theclockoutput Note:HS/CS, VS/VBLK, AVID,FID,and GLCO arelogicinputsby default.See outputformatter3 and 4 registersataddresses35h and 36h,respectively. Copyright© 2005–2012,Texas InstrumentsIncorporated Example RegisterSettings 97 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

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4.2 Example 2

4.2.1 Assumptions

Inputconnector:S-Video[VI_2_C(luma),VI_1_C (chroma)] Videoformat: NTSC (J,M, 443),PAL (B,D, G, H, I,N, Nc,60),orSECAM (default) Outputformat: 10-bitITU-R BT.656 withdiscretesyncoutputs

4.2.2 Recommended Settings

Recommended I2C writes:Thissetuprequiresadditionalwritesto outputthe discretesync 10-bit4:2:2 data,HS, and VS, and toautoswitchbetween allvideoformatsmentionedabove. I2C registeraddress00h = Inputselectregister I2C data46h = Setsluma toVI_2_C and chroma toVI_1_C I2C registeraddress04h = Autoswitchmask register I2C data3Fh = IncludesNTSC 443 and PAL (M,Nc,60)intheautoswitch I2C registeraddress08h = Luminance processingcontrol3 register I2C data00h = OptimizesthetrapfilterselectionforNTSC and PAL I2C registeraddress0Eh = Chrominanceprocessingcontrol2 register I2C data04h = OptimizesthechrominancefilterselectionforNTSC and PAL I2C registeraddress33h = Outputformatter1 register I2C data43h = Selectsthe10-bit4:2:2outputformat I2C registeraddress34h = Outputformatter2 register I2C data11h = EnablesYCbCr outputand theclockoutput I2C registeraddress36h = Outputformatter4 register I2C dataAFh = EnablesHS and VS syncoutputs

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4.3 Example 3

4.3.1 Assumptions

Inputconnector:Component [VI_1_B(Pb),VI_2_B (Y),VI_3_B (Pr)] Videoformat: NTSC (J,M, 443),PAL (B,G, H, I,M, N, Nc) and SECAM Outputformat: 20-bit4:2:2YCbCr withdiscretesyncoutputs

4.3.2 Recommended Settings

Recommended I2C writes:Thissetuprequiresadditionalwritesto outputthe discretesync 20-bit4:2:2 data,HS, and VS, and toautoswitchbetween allvideoformatsmentionedabove. I2C registeraddress00h = Inputselectregister I2C data95h = SetsPb toVI_1_B,Y toVI_2_B,and Pr toVI_3_B I2C registeraddress04h = Autoswitchmask register I2C data3Fh = IncludesNTSC 443 and PAL (M,Nc,60)intheautoswitch I2C registeraddress08h = Luminance processingcontrol3 register I2C data00h = OptimizesthetrapfilterselectionforNTSC and PAL I2C registeraddress0Eh = Chrominanceprocessingcontrol2 register I2C data04h = OptimizesthechrominancefilterselectionforNTSC and PAL I2C registeraddress33h = Outputformatter1 register I2C data41h = Selectsthe20-bit4:2:2outputformat I2C registeraddress34h = Outputformatter2 register I2C data11h = EnablesYCbCr outputand theclockoutput I2C registeraddress36h = Outputformatter4 register I2C dataAFh = EnablesHS and VS syncoutputs Copyright© 2005–2012,Texas InstrumentsIncorporated Example RegisterSettings 99 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK HS/CS FID C_0 C_1 DGND DVDD C_2 C_3 C_4 C_5 IOGND IOVDD C_6/RED C_7/GREEN C_8/BLUE C_9/FSO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD CH4_A33VDD CH4_A33GND VI_4A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS AVID GLCO/I2CA IOVDD IOGND DATACLK40 A3.3VDD GND C_7 C_8 C_9 FID VS/VBLK DATACLK GLCO/I2CA VI_1B VI_1C VI_2A VI_2B VI_3A VI_3B VI_2C VI_3C VI_4A AVID FSS RESETB PWDN CL1 CL2

14.31818 MHz

Y_0 Y_1 Y_2 Y_3 Y_4 Y_5 Y_6 Y_7 Y_8 Y_9 C_6 C_3 C_4 C_5 C_2 C_1 C_0 VI_1A HS/CS XTAL1 XTAL2 XTAL1 XTAL2 A1.8VDD I2C Address selection 1−2 Base Addr. 0xBA 2−3 Base Addr. 0xB8 GLCO/I2CA DVDD1.8V IOVDD3.3V IOVDD 2.2 kΩ (2)75 Ω 75 Ω (3) 75 Ω (3) 75 Ω (3) 2.2 kΩ 10 kΩ 10 kΩ 0.1 µF 0.1 µF 0.1 µF 0.1 µF (2) 0.1 µF 0.1 µF 0.1 µF (3) 0.1 µF 100 kΩ 0.1 µF (3) 0.1 µF (3) 0.1 µF (3) 0.1 µF 0.1 µF 0.1 µF 0.1 µF (2) 0.1 µF (2) 2.2 kΩ TVP5146M2 SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com

5 ApplicationInformation

5.1 ApplicationExample

A. IfXTAL1 isconnectedtoclocksource,inputvoltagehighmust be 1.8V. B. Terminals69 and 71 must be connectedtogroundthroughpulldownresistors. C. System levelESD protectionisnot includedinthisapplicationcircuit,but itishighlyrecommended on the analog videoinputs. Figure5-1.Example ApplicationCircuit

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5.2 DesigningWith PowerPAD ™ Devices

The TVP5146M2 deviceishoused in a high-performance,thermally-enhanced,80-terminalPowerPAD package (TIpackage designator:80PFP). Use of the PowerPAD package does not requireany special considerationsexceptto note thatthe thermalpad, which isan exposed diepad on the bottom of the device,isa metallicthermaland electricalconductor.Therefore,ifnotimplementingthePowerPAD PCB features,the use of soldermasks (orotherassembly techniques)may be requiredto preventany inadvertentshortingby the exposed thermalpad of connectionetchesor viasunder the package.The recommended option,however,isnottorunany etchesorsignalviasunderthedevice,buttohave onlya groundedthermallandas explainedinthefollowingparagraphs.Althoughtheactualsizeoftheexposed diepad may vary,theminimum sizerequiredforthekeep-outarea forthe80-terminalPFP PowerPAD package is8 mm × 8 mm. Itisrecommended thattherebe a thermalland,which isan area of solder-tinnedcopper,under the PowerPAD package.The thermallandvariesinsize,dependingon thePowerPAD package beingused, thePCB construction,and theamount ofheatthatneeds tobe removed.Inaddition,thethermallandmay ormay notcontainnumerous thermalviasdependingon PCB construction. Other requirementsforusingthermallandsand thermalviasare detailedin the TI applicationreport PowerPAD ™ ThermallyEnhanced Package (SLMA002 ),availableviatheTIweb siteathttp://www.ti.com. For theTVP5146M2 device,thisthermallandmust be grounded tothelow-impedanceground planeof thedevice.Thisimprovesnotonlythermalperformancebutalsotheelectricalgroundingofthedevice.It isalsorecommended thatthedevicegroundterminallandingpads be connecteddirectlytothegrounded thermalland.The landsizemust be as largeas possiblewithoutshortingdevicesignalterminals.The thermallandmay be solderedtotheexposed thermalpad usingstandardreflowsolderingtechniques. Whilethethermallandcan be electricallyfloatedand configuredtoremove heattoan externalheatsink,it isrecommended thatthethermallandbe connectedtothelow-impedanceground planeforthedevice. More informationcan be obtainedfromtheTIapplicationreportPHY Layout(SLLA020 ). Copyright© 2005–2012,Texas InstrumentsIncorporated ApplicationInformation 101 SubmitDocumentationFeedback ProductFolderLink(s):TVP5146M2

SLES141H –JULY 2005–REVISED FEBRUARY 2012 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. REVISION COMMENTS SLES141 Initialrelease SLES141A Updated Section2.8 SLES141B Added industrialtemperatureorderableand updatedrelevantspecificationsinChapter3 Updated Section1.2 SLES141C Updated Section2.11.16,Section2.11.17 Updated MAX supplyvoltagesforIndustrialtemperatureinRecommended OperatingConditions Added notesthroughoutElectricalCharacteristicstoindicateparametersspecifiedby designorspecifiedby characterizationonly Updated DNL Differentialnonlinearityspecificationand INL Integralnonlinearity Updated t5Outputdelaytime,Industrial SLES141D Updated Section2.8 SLES141E Added AEC-Q100 qualification Changed allinstancesof10-bitvideodecoderto11-bit Updated registerdescriptionsataddresses09h,0Ah,0Bh Added registersataddresses11h,12h,14h,26h,27h,2Fh Changes allinstancesofWSS toWSS/CGMS and VPS toVPS/Gemstar Changed A18GND (pin24)and A18VDD (pin25)toNC Added Section3.4ThermalSpecification Updated Figure5-1Example ApplicationCircuit SLES141F Section2.6.1,Removed statementaboutinternalpulldownon I2CA terminal. Table2-12,Added RGB rows Updated descriptionforregisterataddress03h Added registersataddresses26h,27h Updated Section3.9ThermalSpecifications SLES141G Table2-10,Added RAM versionMSB and LSB registers(subaddresses:71h,82h) Table2-75,Added RAM versionMSB register(subaddress:71h) Table2-84,Added RAM versionLSB register(subaddress:82h) SLES141H Figure2-12,Added noteconcerningresistor. Figure2-14and Figure2-15,Changed drawings Figure2-20,Correctedtypesettingerror(µ was notvisiblein"100µs"). Figure5-1,Added pulldownresistortoC_1 pin;added noteconcerningESD protection.

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TVP5146M2IPFP Active Production HTQFP (PFP) | 80 96 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2I TVP5146M2IPFP.A Active Production HTQFP (PFP) | 80 96 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2I TVP5146M2IPFPR Active Production HTQFP (PFP) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2I TVP5146M2IPFPR.A Active Production HTQFP (PFP) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2I TVP5146M2IPFPRG4.A Active Production HTQFP (PFP) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2I TVP5146M2PFP Active Production HTQFP (PFP) | 80 96 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR 0 to 70 TVP5146M2 TVP5146M2PFP.A Active Production HTQFP (PFP) | 80 96 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2 TVP5146M2PFPR Active Production HTQFP (PFP) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR 0 to 70 TVP5146M2 TVP5146M2PFPR.A Active Production HTQFP (PFP) | 80 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TVP5146M2 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TVP5146M2IPFP PFP HTQFP 80 96 6 x 16 150 315 135.9 7620 18.7 17.25 18.3 TVP5146M2PFP PFP HTQFP 80 96 6 x 16 150 315 135.9 7620 18.7 17.25 18.3 Pack Materials-Page 1

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Product Information

TVP5146M2IPFP specifications and overview.

Summary

NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support Revised February 2012

Description

NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support Revised February 2012

Source title TVP5146M2IPFP Datasheet(PDF) - Texas Instruments

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