TVP3703_05 TI1 | Alldatasheet
Document overview
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Technical content
SLAS100 – MARCH 1996 Copyright 1996, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
- Fully Integrated Dual Clock Synthesizer and 16-Bit Pixel Port True-Color RAMDAC
- Two Phase-Locked-Loop (PLL) Synthesizers Provide Independently Controlled Video and Memory Clock Outputs
- Functionally Interchangeable with STG1703
- On-Chip PLL Clock Reference Requires Single External Crystal
- 16-Bit Pixel Port Supports VGA High-Color and True-Color Standards Up to 170 MHz
- Programmable Power-Down Features
- On-Chip Cyclic Redundancy Check (CRC) Test
description
The TVP3703 is a super video graphics array (SVGA) compatible, true-color CMOS RAMDAC with integrated clock synthesizers that can provide the memory and pixel clock signals for a PC graphics subsystem. The video clock can be one of two VGA base frequencies or fourteen Video Electronics Standards Association (VESA) standard frequencies which can also be reprogrammed through the standard micro port interface. The memory clock output is also user programmable at frequencies up to 80 MHz. The pixel modes supported by the TVP3703 include:
- Serializing 16-bit pixel port providing 170 MHz, 8-bit and 73 MHz, 24-bit packed pixel modes using an internal PLL
- 16-bit pixel port providing faster, high-color/true-color operation up to the 110 MHz sampling rate
- 8-bit pixel port providing standard SVGA and high-color/true-color modes up to the 110 MHz sampling rate The 68 terminal FN package is designed to be interchangeable with the STG1703. 28 29 GND REF RS2 COMP RSET VS3 VS2 VS1 VS0 GND BLANK WR RS0 RS1 P14 PIXMIX P15 NC 31 32 33 34 FN PACKAGE (TOP VIEW) SENSE P11 87 6 5493 XIN XOUT RD P13 GND P12 GND GND RED GREEN NC NC NC NC NC NC 16 8 6 72 35 36 37 38 39 66 65 NC P10 64 63 62 61 40 41 42 43BLUE GND STROBE PCLK MCLK VCLK DDV DDVA DDV DDV DDV DDVA NC – No internal connection PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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applications
- Screen resolutions (noninterlaced) – 1600 × 1280, 8-bit/pixel, 60 Hz – 1280 × 1024, 16-bit/pixel, 60 Hz – 1024 × 768, 16-bit/pixel, 85 Hz – 1024 × 768, 24-bit/pixel, packed, 70 Hz – 800 × 600, 24-bit/pixel, unpacked, 72 Hz
- True-color desktop, PC add-in cards functional block diagram Multiplexor Mask 256× 8 Bit Color Palette 256× 8 Bit Color Palette 256× 8 Bit Color Palette Bypass Multiplexor DAC DAC DAC DAC Comparators DAC Control RED BLUE Micro Port MCLK PLL MCLK Registers Crystal Oscillator VCLK PLL VCLK Registers Internal REF Pipeline Timing Pixel Latches D0–D7 RD WR RS0-RS2 VS0-VS3 STROBE PIXMIX P0–P15 PCLK REF RSET BLANK COMP SENSE MCLK XIN XOUT VCLK GREEN
SLAS100 – MARCH 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions micro port TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION RD , 5, I Read enable and write enable. RD or WR control the timing of read and write operations on the micro port. WR 20 Most of the operations on the micro port can take place asynchronously to the pixel stream being processed by the color palette. Various minimum periods between operations are specified (in terms of pixel clocks) to allow this asynchronous behavior. RD and WR should not be low at the same time. RS0–RS2 21, 22, I Register select. RS0–RS2 specify which internal register is to be accessed. The RS0–RS2 inputs are sampled on the falling edge of the active enable signal (RD or WR). Information on register access and contents is given in the micro port section. The additional RS2 signal allows access to the extended features without the need for performing an indirect access sequence. D0–D7 12–19 I/O Input/output data. Data transfers between the 8-bit wide program data bus and the registers within the TVP3703 under control of the active enable signal (RD or WR). In a write cycle, the rising edge of WR validates the data on the program data bus and causes it to be written to the register selected. The rising edge of RD signifies the end of a read cycle, after which the program data bus ceases to carry the contents of the register addressed and goes to a high impedance state. VS0–VS3 44–47 I Video clock PLL select.VS0–VS3 select the frequency (default or user programmed) of the video clock PLL. VS0–VS3 are ignored if the video clock frequency is selected by register control. STROBE 43 I Strobe input.The falling edge of STROBE latches VS0–VS3. pixel port TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION PCLK 63 I Pixel clock. The rising edge of PCLK controls the sampling of data on P0–P15, BLANK, and PIXMIX in all modes. P0–P15 1, 4, 23, 25, 52–59, 64–67 I Pixel data word. The selected pixel mode determines how this pixel data is interpreted. PIXMIX 24 I Pixel mode select. PIXMIX controls the switching between primary and secondary pixel modes when the extended pixel modes are selected (PIXMIX = 0 selects primary mode). BLANK 11 I Blank in. A low value sampled on BLANK, after the pipeline delay, turns the DAC outputs off.
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NAME NO. I/O DESCRIPTION RED, GREEN, BLUE 38–40 O DAC video outputs. These signals are designed to drive a doubly terminated 75-Ω load. REF 51 I External 1.235-V reference voltage. An external bypass capacitor should be connected from REF to GND. RSET 48 I A precision resistor placed between RSET and GND sets the full-scale DAC current. The required resistor value can be calculated from: where Vref is the external or internal reference voltage and IO is the required DAC full-scale output current. Rset is typically 147 Ω for VGA (see application information section). COMP 49 I External compensation capacitor connection for DACs. SENSE 68 O Sense out. SENSE is a logical 0 if one or more of the DAC outputs exceeds the internal DAC comparator trip voltage (which is midway between the DAC full scale and GND potentials). frequency synthesizer interface TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION XOUT 6 O Crystal output and input connections. A series-resonant crystal must be connected between XOUT and XIN XIN 7 I to provide the reference clock for the PLLs. VCLK 9 O Video clock PLL out MCLK 61 O Memory clock PLL out power supply TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION VDD 8, 27, 35, Digital power AV DD 3, 42 Analog power for the DACs and PLL. GND 2, 10, 36, 37, 41, 60 Common ground rail for all circuitry. NC 26, 28–34 No internal connection. For future upgrade to a 24-bit pixel port the controller. Outputs P16–P23 can be routed to terminals 26, 28–34 respectively. detailed description micro port The TVP3703 micro port (see Table 1) is an extension of the standard VGA micro port and powers up with a register configuration compatible with standard and high-color VGA. There are two methods for accessing the register set of the TVP3703 – direct register space (RS) access and indirect access. direct RS access This feature supports direct RS mapping to eight address locations that access the VGA color palette, pixel command register, and an indexed register. The index low/high registers increment after every access to the indexed register. R set(/C0087) /C0043 /C04662.1 /C0032V ref/C0467 IO
Table 1. Direct RS Micro Port Accesses
000 Address register (palette write)
001 Palette color value
010 Pixel mask/indirect access
011 Address register (palette read)
100 Index low byte
101 Indexed register
110 Pixel command register
111 Index high byte
If the indexed register space is not enabled, the next access is directed to the pixel mask (state 1 in Table 2). indexed register space can be moved as a block without the need to keep writing to the index register. Table 2. Indirect Access Sequence
1 Pixel mask 2 2 1 1
2 Pixel mask 3 3 1 1
3 Pixel mask 4 4 1 1
4 Pixel mask 5 5 1 1
5 Pixel command 6 1 1 1
6 Index low byte 7 7 1
7 Index high byte 8 8 1
8 Indexed register 8‡ 8‡ 1
† Power-up state is state 1.
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The TVP3703 indexed register space including the indexes, register contents, and values is shown in Table 3. Table 3. Indexed Register Space † Register power-up values for given synthesizer frequencies are shown in parentheses.
SLAS100 – MARCH 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 register content descriptions A write to any register containing reserved bits should always write 0s to the reserved bits (the exception being bit 7 of power management register A). On reads, all reserved bits should be masked out. The values of register bits that are reset on power-up are listed in the reset value columns below. PIXEL COMMAND REGISTER (RS0–RS2 = 110) BIT VALUE FUNCTION RESET VALUE 000 8-bit color
001 Reserved
010 Reserved
011 Reserved
0007–5
100 Reserved
4 1 = Enable extended register space 0 3 1 = Enable extended pixel modes 0 2 1 = Add 7.5 IRE† blanking pedestal 0 1 1 = Micro port interface to RAM is 8-bit not 6-bit 0 1 = Sleep mode (micro port and palette RAM still enabled, see power management features section) † Institute of Radio Engineers INDEX LOW AND HIGH BYTE REGISTERS (RS0–RS2 = 100, RS0–RS2 = 111) BIT FUNCTION RESET VALUE 7–0 Low/high byte of 16-bit index 0 COMPANY ID REGISTER (Index 0000h) BIT VALUE FUNCTION RESET VALUE 7–0 97h Texas Instruments Read only DEVICE ID REGISTER (Index 0001h) BIT VALUE FUNCTION RESET VALUE 7–0 03h TVP3703 Read only PIXEL MODE SELECT REGISTERS (Primary and Secondary) (Indexes 0003h, 0004h) BIT VALUE FUNCTION MAX PCLK (MHz) MAX VIDEO RATE (MHz) RESET VALUE 00h 8-bit indexed color 110 110 01h 15-bit direct color or 8-bit indexed color 110 110 02h 15-bit direct color 110 110 03h 16-bit 5–6–5 direct color 110 110 04h 24-bit direct color 110 55 05h Double 8-bit indexed color 67.5 135 Not7–0 06h 16-bit 5–6–5 direct color (2 × 8-bit input) 110 55 Not Reset 07h 8-bit indexed color (2 × 4-bit input) 110 55 08h 15-bit direct color (2 × 4-bit input) 110 55 09h Double 24-bit direct color 85 56.5 0Ah– FFh Reserved PIPELINE TIMING CONTROL REGISTER (Double 8-bit and 24-bit modes only) (Index 0005h) The TVP3703 uses an internal PLL and timing control circuitry to automatically adjust pipeline. There are no register bits to program, since the device accounts for all desired frequency ranges. SOFT RESET REGISTER (Index 0006h) BIT FUNCTION RESET VALUE 7–1 Reserved 0 0 1 = Reset all registers to power-on default state0
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7 Reserved (write 1) 1 1
6 Reserved (write 0) 0 1
4 Reserved (write 0) 0 1
3 Reserved 1 1
7 VCLK/MCLK source select 0 (see Table 4)
7 VCLK/MCLK source select 1 (see Table 4)
Table 4. VCLK/MCLK Source Select ‡ See power management features section.
7 Reserved 0
1 Use self-test-generated patterns
SLAS100 – MARCH 1996 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 programming the PLL clock generators The conditions shown in the following equations must be followed when programming the PLL clock generators. /C0551 /C0545 /C0546 fI/C0466XIN/C0467/C003210/C00426 2 /C00422/C0551 /C0547 /C0548 /C0118N1 /C0118/C0466fI/C0466XIN/C0467/C003210/C00426 /C00422/C0467 (1) (2) (3) Where: 0 /C0118N1 /C011831 and N1 must be an integer /C0551/C0545 /C0546 64 /C0032106 fI/C0466XIN/C0467 (N1 /C00412)/C00422/C0551/C0547 /C0548 /C0118M /C0118/C0551/C0545 /C0546 135 /C0032106 fI/C0466XIN/C0467 (N1 /C00412)/C00422/C0551/C0547 /C0548 Where: 0 /C0118M /C0118127 and M must be an integer 2N2 /C0043 fI/C0466XIN/C0467(M /C00412) fO (N1 /C00412) Where: 0 /C0118N2 /C01183 and N2 must be integer power management features Two power reduction options are available on the TVP3703. 1. Bit 0 of the pixel command register (sleep mode) provides a default power-down mode in which the following sections of the device are powered down:
- All pixel multiplexor modes
- All post-RAM logic
- The triple DAC
- The mask logic Micro port and palette-RAM power is maintained to allow read and write access to the internal registers or palette locations. A typical value of IDD in sleep mode is listed in the electrical characteristics section. 2. The power management register, located in the indexed register space (index 0007h), allows selective power down of the device. use of the hardware CRC feature The TVP3703 hardware CRC feature supports testing of the entire pixel data path from the pixel port through to the DAC inputs at full video rates up to 170 MHz on the TVP3703. Each of the three colors (red, green and blue) are tested independently. CRCs are accumulated during active display, with accumulation being gated by the BLANK signal. A TVP3703 CRC can be accumulated in either active screen or self-test-pattern generation mode and is controlled by bit 1 of the CRC test register (index FFD6h). To use the pattern generated CRC feature, perform the following test procedure: 1. Set the mode and verify the PIXMIX signal is low. 2. Set the proper values in the CRC test register for the desired CRC mode. Set BLANK low. Wait for ten PCLKS cycles. 3. Set bit 2 of the CRC test register to 1 and bit 1 to 0.
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use of the hardware CRC feature (continued) 4. Set BLANK high. 5. Run for ten PCLK cycles. 6. Set BLANK low. 7. Run for 1200 dot clock cycles. 8. Set 0x5555 on pixel bus input. 9. Run for 20 PCLK cycles. 10. Set 0x0000 on the pixel bus input. 11. Run for three PCLK cycles. 12. Set bit 2 of the CRC test register to 0 and bit 1 to 1. 13. Wait for > 240 PCLK cycles. 14. Wait 1200 dot clock cycles. 15. Read the CRC low and high byte registers for the CRC result. The CRC technique allows an authoritative check to be performed between the intended display and the actual display at full video rates. For a given image (which can be an application’s image or a specially prepared test screen), theoretically derived CRC values are calculated for each RGB color, which are then compared with the TVP3703 hardware CRC values. Alternatively, the CRC value from a known good screen can be used as the reference. The CRC facility on the TVP3703 can be used to validate correct operation of:
- The TVP3703 device in isolation
- The TVP3703 device designed into, and working in, a VGA board
- The DRAM, controller, and data path on the VGA board
- The disk and bus operation of the host PC
- MS-Windows (and device drivers) on the PC The horizontal and vertical synchronization waveforms or timings do not affect hardware CRC accumulation. Any discrepancy between the calculated and TVP3703 hardware accumulated CRC values indicates a problem in the device or system being used. The CRC logic on the TVP3703 is normally powered down. To perform a CRC test, bit 2 of the CRC test register (index FFD6h) should be reset to 0 and returned to 1 afterwards to return to the default condition. The CRC mechanism does not check the DAC outputs (i.e., what is physically being displayed on the monitor); these can be tested using the TVP3703 SENSE output (generally readable as a register bit on the VGA controller). MS-Windows is a registered trademark of Microsoft Corporation.
indexed registers. This also resets the indirect procedure. VGA, SVGA, and extended pixel modes are listed in Tables 5 and 6. Table 5. VGA and SVGA Modes
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Table 6. Extended Pixel Modes § Modes 5 (05h) and 9 (09h) use PLL, DAC CLK = 2 × PCLK or 2/3 PCLK respectively. control of the PIXMIX terminal. has gone high at the start of a line. The primary and secondary pixel mode combinations are listed in Table 7.
Table 7. Primary and Secondary Pixel Mode Combinations primary and secondary modes are the same. to dot clock ratio based on the multiplexing mode selected. Therefore no further programming is necessary. during active display must be a multiple of 3. The total horizontal duration must be an integral multiple of 3 PCLKs. /C0043integer, where HTOT/C0043total horizontal duration in standard VGA registers. The total vertical duration must be an integral multiple of 3 PCLKs. 3 /C0043integer, where VTOT/C0043total vertical duration in standard VGA registers. In all standard VGA systems, if the horizontal requirement is met, the vertical requirement is also met.
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 3: All voltage values are with respect to GND. recommended operating conditions MIN NOM MAX UNIT Supply voltages, AVDD , DVDD 4.75 5 5.25 V Reference voltage, Vref 1.15 1.235 1.26 V High-level input voltage, VIH 2.4 VDD +0.5 V Low-level input voltage, VIL 0.8 V Output load resistance, RL 37.5 Ω FS ADJUST resistor, RSET 147 Ω Operating free-air temperature, TA 0 70 °C
electrical characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply current, average power (see Note 4) 270 340 mA IDD Supply current, average power (sleep mode) (see Note 5) 60 150 mA Supply current, average power (palette RAM powered down) (see Note 4) 220 250 mA II Digital input current ± 100 µA IO Off-state-digital output current ± 50 µA VOH High-level output voltage IL = –1 mA 2.4 V VOL Low-level output voltage IL = 4 mA 0.4 V NOTES: 4. Typical and maximum figures are both measured at 135 MHz, with differences due to VDD , pixel mode, and part to part variations. 5. Typical figure measured at 35 MHz, with differences due to VDD , pixel mode, and part to part variations.
SLAS100 – MARCH 1996 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements micro port PARAMETER TVP3703-170 TVP3703-135 UNITPARAMETER MIN MAX MIN MAX UNIT tw(WLWH) Pulse duration, WR low 50 75 ns tw(RLRH) Pulse duration, RD low 50 50 ns trec(WHWL) Recovery time preceding a write (see Notes 6 and 7) 3× tc(CHCH) 3× tc(CHCH) ns trec(RHRL) Recovery time preceding a read (see Notes 6 and 7) 6× tc(CHCH) 6× tc(CHCH) ns tsu(SVL) Setup time, RS0-RS2 10 10 ns th(LSX) Hold time, RS0-RS2 4 4 ns tsu(DVWH) Setup time, write data 10 10 ns th(WHDX) Hold time, write data 10 10 ns NOTES: 6. t c(CHCH) (PCLK period) is specified in the pixel port timing requirements table. 7. Access recovery times are specified as the time before a particular access because the worst case access (reading a red palette color value) can occur after either reading a blue palette color value or after writing to the address register (read mode). PLL frequency select PARAMETER TVP3703-170 TVP3703-135 UNITPARAMETER MIN MAX MIN MAX UNIT tw(SHSL) Pulse duration, STROBE high 50 50 ns tw(SLSH) Pulse duration, STROBE low 50 50 ns tsu(SVSL) Setup time, VS0–VS3 (see Note 8) 20 30 ns th(SLSX) Hold time, VS0–VS3 (see Note 8) 20 30 ns NOTE 8: The VS0–VS3 latches are transparent when STROBE is at logic 1. pixel port PARAMETER TVP3703-170 TVP3703-135 UNITPARAMETER MIN MAX MIN MAX UNIT PCLK cycle time (pixel mode 05h – double 8-bit, indexed) 11.7 14.8 ns tc(CHCH) PCLK cycle time (pixel mode 09h – double 24-bit, direct) 9.08 9.08 ns() PCLK cycle time (all other pixel modes) 9.08 9.08 ns tw(CLCH) Pulse duration, PCLK low 2.9 4 ns tw(CHCL) Pulse duration, PCLK high 2.9 3 ns tsu(PVCH) Setup time, pixel data (see Note 9) 2 2 ns th(CHPX) Hold time, pixel data (see Note 9) 2 2 ns NOTE 9: The pixel address input to the color palette should be set up as a valid logic level with the appropriate setup and hold times to each rising edge of PCLK (this requirement must also be met during the blanking period).
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td(RLQX) Delay time, output turn on 5 5 ns ta(RLQV) Access time, read enable 40 40 ns th(RHQX) Hold time, output 5 5 ns td(RHQZ) Delay time, output turn off 20 20 ns pixel port PARAMETER TVP3703-170 TVP3703-135 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT Analog output skew 1 1 ns frequency synthesis PARAMETER TVP3703-170 TVP3703-135 UNITPARAMETER MIN TYP MAX MIN TYP MAX UNIT fI(XIN) XIN crystal frequency range 14.3 14.3 MHz Internal VCO frequency 64 170 64 135 MHz fO VCLK output frequency (CL = 15 pF) 110 110 MHz fO MCLK output frequency (CL = 15 pF) 80 80 MHz Synthesizer lock time 5 5 ms
- About the midpoint of the distribution of the three DACs
- Measured between 10% and 90% of full scale transition.
- Settling to within 2% of frame sync delay (fsd)
Figure 1. Micro Port Read/Write Cycle Timing
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Figure 2. PLL Frequency Select Write Cycle Timing Figure 3. Pixel Port Timing
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APPLICATION INFORMATION
RED, GREEN, BLUE GND 75 Ω Monitor 75 Ω D2–D4 R2 R3–R5D1C3C2 Local AVDD Plane VDD POWER SUPPLY D5–D7 TVP3703 Figure 4. Analog Interface – Recommended Circuit in Internal Voltage Reference Mode † Place these components as close to the palette DAC as possible.
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FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B–10/94
20 PIN SHOWN
0.180 (4,57) 0.020 (0,51) MIN 0.120 (3,05) 0.090 (2,29) D 2/E2 0.013 (0,33) 0.021 (0,53) MAX 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 1.158 (29,41) 0.956 (24,28) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D D 1 E1E MINMAXMIN 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.026 (0,66) 0.032 (0,81) 0.008 (0,20) NOM M0.007 (0,18) 0.050 (1,27) Seating Plane 0.004 (0,10) D 2/E2 D 2/E2D 1/E1D/E NO. OF PINS** NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TVP3703-135CFN OBSOLETE PLCC FN 68 TBD Call TI Call TI TVP3703-170CFN OBSOLETE PLCC FN 68 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1
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