TSX9291 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 31
Technical content
Datasheet sections
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Application information
- 4.1 Operating voltages
- 4.2 Rail-to-rail input
- 4.3 Input pin voltage range
- 4.4 Stability for gain = -1
- 4.5 Input offset voltage drift over temperature
- 4.6 Long-term input offset voltage drift
- 4.7 Capacitive load
- 4.8 High side current sensing
- 4.9 High speed photodiode
- 5 Package information
- 5.1 SOT23-5 package mechanical data
- 5.2 DFN8 2x2 package information
- 5.3 MiniSO8 package information
- 5.4 SO8 package information
- 6 Ordering information
- 7 Revision history
Features
- Rail-to-rail input and output
- Wide supply voltage: 4 V - 16 V
- Gain bandwidth product: 16 MHz typ at 16 V
- Low power consumption: 2.8 mA typ at 16 V
- Slew rate: 27 V/μs
- Stable when used in gain configuration
- Low input bias current: 10 pA typ
- High tolerance to ESD: 4 kV HBM
- Extended temperature range: -40° C to +125° C
- Automotive qualification
Related products
- See the TSX5 series for low power features
- See the TSX6 series for micro power features
- See the TSX92 series for unity gain stability
- See the TSV9 series for lower voltage
Applications
- Communications
- Process control
- Active filtering
- Test equipment
Description
The TSX9291 and TSX9292 operational amplifiers (op-amps) offer excellent AC characteristics such as 16 MHz gain bandwidth, 27 V/μs slew rate, and 0.0003 % THD+N. They are decompensated amplifiers which are stable when used with a gain higher than 2 or lower than -1. The rail-to-rail input and output capability of these devices operates on a wide supply voltage range of 4 V to 16 V. These last two features make the TSX929x series particularly well- adapted for a wide range of applications such as communications, I/V amplifiers for ADCs, and active filtering applications. 627 76; ')1[ 76; 76; 0LQL62 76; Table 1. Device summary
1 Package pin connections
Figure 1. Pin connections (top view)
2 Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings (AMR)
- All voltage values, except the differential volt age are with respect to network ground terminal.
- The differential voltage is the non-inverting input term inal with respect to the inverting input terminal.
- Input current must be limited by a resistor in series with the inputs.
- Short-circuits can c ause excessive heating and destructive dissipation.
- According to JEDEC standard JESD22-A114F
- According to JEDEC standard JESD22-A115A
- According to ANSI/ESD STM5.3.1
Table 3. Operating conditions
3 Electrical characteristics
Table 4. Electrical characteristics at VCC+ = +4.5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and
- Typical value is based on the Vio drift observed after 100 0h at 125°C extrapolated to 25°C using the Arrhenius law and
Long-term input offset voltage drift.
- When used in comparator mode, with high differentia l input voltage, during a long period of time with VCC close to 16V and
Table 5. Electrical characteristics at VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and
- Typical value is based on the Vio drift observed after 100 0h at 125°C extrapolated to 25°C using the Arrhenius law and
Long-term input offset voltage drift.
- When used in comparator mode, with high differentia l input voltage, during a long period of time with VCC close to 16V and
Table 6. Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and
- Typical value is based on the Vio drift observed after 100 0h at 125°C extrapolated to 25°C using the Arrhenius law and
Long-term input offset voltage drift.
- When used in comparator mode, with high differentia l input voltage, during a long period of time with VCC close to 16V and
4 Application information
4.1 Operating voltages
temperature range of -40 to +125 °C.
4.2 Rail-to-rail input
applications requiring the rail-to-rail input feature. TSX9291 and TSX9292 are designed to prevent phase reversal.
4.3 Input pin voltage range
current limitation on the input pins. Figure 35. Limiting input current with a series resistor
4.4 Stability for gain = -1
has a direct impact on the stability. Figure 36. Configuration for gain = -1 Figure 37. Close loop gain vs. frequency
compensate the input capacitance and to increase stability. Figure 38 shows how Cf reduces the gain peaking. Figure 38. Close loop gain vs. frequency with capacitive compensation
4.5 Input offset voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. sample size ensuring a Cpk (process capability index) greater than 2.
4.6 Long-term input of fset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
- Voltage acceleration, by changing the applied voltage
- Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. AFV e β VS VU–()⋅ AFT e Ea TU TS ⎛⎞⋅ AF AFT AFV×=
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 The long-term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
4.7 Capacitive load
Driving a large capacitive load can cause stability issues. Increasing the load capacitance produces gain peaking in the frequency response, with overshooting and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB the op-amp might become unstable. Generally, the unity gain configuration is the worst configuration for stability and the ability to drive large capacitive loads. Figure 39 shows the serial resistor (Riso) that must be added to the output, to make the system stable. Figure 40 shows the test configuration for Riso. Months A F 1000 h× 12 months 24 h 365.25 days×()⁄×= VCC maxVop with Vicm VCC 2⁄== ΔVio Vio drift months()
4.8 High side current sensing
voltage on a high side shunt resistor and translate it into a ground referenced output voltage. The gain is fixed by external resistance. Figure 41. High side current sensing configuration VOUT can be expressed as shown in Equation 8. requires a higher common voltage, please refer to the TSC high side current sensing family.
4.9 High speed photodiode
high-speed photodiode preamplifier applications. and to obtain good noise performance, CF can be set as shown in Equation 10.
- CIN = CCM + CDIFF = 11 pF
- CDIFF is the differential input capacitance: 8 pF typical
- CCM is the Common mode input capacitance: 3 pF typical
- CD is the intrinsic capacitance of the photodiode
- CSMR is the parasitic capacitance of the surface mount RF resistor: 0.2 pF typical
- FGBP is the gain bandwidth product: 10 MHz at 16 V RF fixes the gain as shown in Equation 11. Equation 11
Figure 42. High speed photodiode
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
5.1 SOT23-5 package mechanical data
Figure 43. SOT23-5 package mechanical drawing Table 7. SOT23-5 package mechanical data
5.2 DFN8 2x2 pack age information
Figure 44. DFN8 2x2 package mechanical drawing Table 8. DFN8 2x2 package mechanical data
5.3 MiniSO8 package information
Figure 45. MiniSO8 package mechanical drawing Table 9. MiniSO8 package mechanical data
5.4 SO8 package information
Figure 46. SO8 package mechanical drawing Table 10. SO8 package mechanical data
6 Ordering information
7 Revision history
Table 11. Order codes
- Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 & Q 002 or equivalent. Table 12. Document revision history Table 4, Table 5, and Table 6. temperature in Section 4: Application information. in Section 4: Application information. condition for the gain parameter. concerning an Rs resistor; updated Figure 35. TSX9291IYLT and TSX9291IQ2T.