TSX920 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Package pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Electrical characteristic curves
- 5 Application information
- 5.1 Operating voltages
- 5.2 Rail-to-rail input
- 5.3 Input pin voltage range
- 5.4 Input offset voltage drift over temperature
- 5.5 Long term input offset voltage drift
- 5.6 Capacitive load
- 5.7 High-side current sensing
- 5.8 High-speed photodiode
- 6 Package information
- 6.1 SOT23-5 package information
- 6.2 SOT23-6 package information
- 6.3 MiniSO8 package information
- 6.4 SO8 package information
- 6.5 DFN8 2x2 package information
- 6.6 MiniSO10 package information
- 7 Ordering information
- 8 Revision history
Features
Rail-to-rail input and output Wide supply voltage: 4 V - 16 V Gain bandwidth product: 10 MHz typ at 16 V Low power consumption: 2.8 mA typ per amplifier at 16 V Unity gain stable Low input bias current: 10 pA typ High tolerance to ESD: 4 kV HBM Extended temperature range: -40 °C to 125 °C Automotive qualification
Related products
See the TSX5 series for low-power features See the TSX6 series for micro-power See the TSX929 series for higher speeds See the TSV9 series for lower voltages
Applications
Description
The TSX92x single and dual operational amplifiers (op amps) offer excellent AC characteristics such as 10 MHz gain bandwidth, 17 V/ms slew rate, and 0.0003 % THD+N. These features make the TSX92x family particularly well-adapted for communications, I/V amplifiers for ADCs, and active filtering applications. Their rail-to-rail input and output capability, while operating on a wide supply voltage range of 4 V to 16 V, allows these devices to be used in a wide range of applications. Automotive qualification is available as these devices can be used in this market segment. Shutdown mode is available on the single (TSX920) and dual (TSX923) versions enabling an important current consumption reduction while this function is active. The TSX92x family is available in SMD packages featuring a high level of integration. The DFN8 package, used in the TSX922, with a typical size of 2x2 mm and a maximum height of 0.8 mm offers even greater package size reduction. Table 1: Device summary Op-amp version With shutdown mode Without shutdown mode Single TSX920 TSX921 Dual TSX923 TSX922
1 Package pin connections
Figure 1: Pin connections (top view)
Absolute maximum ratings and operating conditions TSX920, TSX921, TSX922, TSX923
2 Absolute maximum ratings and operating conditions
Table 2: Absolute maximum ratings (AMR) Symbol Parameter Value Unit VCC Supply voltage (1) 18 V Vid Differential input voltage (2) ±VCC mV Vin Input voltage (VCC-)- 0.2 to (VCC+) + 0.2 V Iin Input current (3) 10 mA Tstg Storage temperature -65 to 150 Tj Maximum junction temperature 150 Rthja Thermal resistance junction to ambient (4)(5) SOT23-5 250 °C/W SOT23-6 240 MiniSO8 190 SO8 125 DFN8 2x2 57 MiniSO10 113 ESD HBM: human body model (6) 4000 V MM: machine model (7) 100 CDM: charged device model (8) 1500 Latch-up immunity 200 mA Notes: (1)All voltage values, except the differential voltage are with respect to network ground terminal. (2)The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. (3)Input current must be limited by a resistor in series with the inputs. (4)Rth are typical values. (5)Short-circuits can cause excessive heating and destructive dissipation. (6)According to JEDEC standard JESD22-A114F (7)According to JEDEC standard JESD22-A115A (8)According to ANSI/ESD STM5.3.1 Table 3: Operating conditions Symbol Parameter Value Unit VCC Supply voltage 4 to 16 V Vicm Common mode input voltage range (VCC-) - 0.1 to (VCC+) + 0.1 Toper Operating free air temperature range -40 to 125 °C
3 Electrical characteristics
Table 4: Electrical characteristics at VCC+ = 4.5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit Vio Input offset voltage Vicm = 2 V (all order codes except TSX922IYST and TSX922IYDT) mV Tmin < Top < Tmax Vicm = 2 V (TSX922IYST, TSX922IYDT order codes only) Tmin < Top < Tmax 6.5 ∆Vio/∆T Input offset voltage drift All order codes except TSX922IYST and TSX922IYDT 2 10 μV/°C TSX922IYST and TSX922IYDT order codes only 2 15 ∆Vio Long-term input offset voltage drift (1)(2) TSX920/TSX921 nV/√month TSX922/TSX923 Iib Input bias current Vout = VCC/2 10 100 pA Tmin < Top < Tmax 200 Iio Input offset current Vout = VCC/2 10 100 Tmin < Top < Tmax 200 RIN Input resistance TΩ CIN Input capacitance pF CMRR Common mode rejection ratio 20 log (ΔVic/ΔVio) Vicm = -0.1 V to 2 V, VOUT = VCC/2 61 82 dB Tmin < Top < Tmax 59 Vicm = -0.1 V to 4.6 V, VOUT = VCC/2 59 72 Tmin < Top < Tmax 57 Avd Large signal voltage gain RL= 2 kΩ, Vout = 0.3 V to 4.2 V 100 108 Tmin < Top < Tmax 90 RL= 10 kΩ, Vout = 0.2 V to 4.3 V 100 112 Tmin < Top < Tmax 90 VOH High level output voltage RL= 2 kΩ tο VCC/2 50 80 mV from VCC+ Tmin < Top < Tmax 100 RL= 10 kΩ tο VCC/2 10 16 Tmin < Top < Tmax VOL Low level output voltage RL= 2 kΩ tο VCC/2 42 80 mV Tmin < Top < Tmax 100 RL= 10 kΩ tο VCC/2 9 16 Tmin < Top < Tmax
Symbol Parameter Conditions Min. Typ. Max. Unit Iout Isink Vout = 4.5 V 16 21 mA Tmin < Top < Tmax 13 Isource Vout = 0 V 16 21 Tmin < Top < Tmax 13 ICC Supply current (per amplifier) No load, Vout = VCC/2 2.9 3.4 Tmin < Top < Tmax 3.5 GBP Gain bandwidth product RL = 10 kΩ, CL = 20 pF, G = 20 dB MHz FU Unity gain frequency RL = 10 kΩ, CL = 20 pF 9.3 ɸm Phase margin Degrees Gm Gain margin 6.7 dB SR+ Positive slew rate Av = 1, Vout = 0.5 to 4.0 V, measured between 10 % to 90 % 14.7 V/μs SR- Negative slew rate Av = 1, Vout = 4.0 to 0.5 V, measured between 90 % to 10 % 17.2 en Equivalent input noise voltage f = 10 kHz 17.9 nV√Hz f = 100 kHz 12.9 ∫en Low-frequency peak-to- peak input noise Bandwidth: f = 0.1 to 10 Hz 8.1 µVpp THD+N Total harmonic distortion + noise f = 1 kHz, Av = 1, RL = 10 kΩ, Vout = 2 Vrms 0.002 Shutdown characteristics (TSX920 and TSX923 only) ICC_shdn Supply current in shutdown mode (per amplifier) SHDN = VCC- 7 15 µΑ Tmin < Top < Tmax ton Amplifier turn-on time µs toff Amplifier turn-off time 0.7 Notes: (1)Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 5.5: "Long term input offset voltage drift"). (2)When used in comparator mode, with high differential input voltage, during a long period of time with VCC close to 16 V and Vicm>VCC/2, Vio can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
Table 5: Electrical characteristics at VCC+ = 10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit Vio Input offset voltage Vicm = 2 V (all order codes except TSX922IYST and TSX922IYDT) mV Tmin < Top < Tmax Vicm = 2 V (TSX922IYST and TSX922IYDT order codes only) Tmin < Top < Tmax 6.5 ∆Vio/∆T Input offset voltage drift All order codes except TSX922IYST and TSX922IYDT 2 10 μV/°C TSX922IYST and TSX922IYDT order codes only 2 15 ∆Vio Long-term input offset voltage drift (1)(2) TSX920/TSX921 nV/√month TSX922/TSX923 128 Iib Input bias current Vout = VCC/2 10 100 pA Tmin < Top < Tmax 200 Iio Input offset current Vout = VCC/2 10 100 Tmin < Top < Tmax 200 RIN Input resistance TΩ CIN Input capacitance pF CMRR Common mode rejection ratio 20 log (ΔVic/ΔVio) Vicm = -0.1 V to 7 V, VOUT = VCC/2 72 85 dB Tmin < Top < Tmax 70 Vicm = -0.1 V to 10.1 V, VOUT = VCC/2 64 75 Tmin < Top < Tmax 62 Avd Large signal voltage gain RL= 2 kΩ, Vout = 0.3 V to 9.7 V 100 107 Tmin < Top < Tmax 90 RL= 10 kΩ, Vout = 0.2 V to 9.8 V 100 117 Tmin < Top < Tmax 90 VOH High-level output voltage RL= 2 kΩ tο VCC/2 94 110 mV from VCC+ Tmin < Top < Tmax 130 RL= 10 kΩ tο VCC/2 31 40 Tmin < Top < Tmax VOL Low-level output voltage RL= 2 kΩ tο VCC/2 80 110 mV Tmin < Top < Tmax 130 RL= 10 kΩ tο VCC/2 14 40 Tmin < Top < Tmax Iout Isink Vout = 10 V 50 55 mA Tmin < Top < Tmax 42 Isource Vout = 0 V 75 82 Tmin < Top < Tmax 70
Symbol Parameter Conditions Min. Typ. Max. Unit ICC Supply current (per amplifier) No load, Vout = VCC/2 3.1 3.6 mA Tmin < Top < Tmax 3.6 GBP Gain bandwidth product RL = 10 kΩ, CL = 20 pF, G = 20 dB MHz FU Unity gain frequency RL = 10 kΩ, CL = 20 pF 11.2 ɸm Phase margin Degrees Gm Gain margin dB SR+ Positive slew rate Av = 1, Vout = 0.5 to 9.5 V, measured between 10 % to 90 % 17.7 V/μs SR- Negative slew rate Av = 1, Vout = 9.5 to 0.5 V, measured between 90 % to 10 % 19.6 en Equivalent input noise voltage f = 10 kHz 16.8 nV√Hz f = 100 kHz ∫en Low-frequency peak-to- peak input noise Bandwidth: f = 0.1 to 10 Hz 8.64 µVpp THD+N Total harmonic distortion + noise f = 1 kHz, Av = 1, RL = 10 kΩ, Vout = 2 Vrms 0.0006 Shutdown characteristics (TSX920 and TSX923 only) ICC_shdn Supply current in shutdown mode (per amplifier) SHDN = VCC- 7 15 µΑ Tmin < Top < Tmax ton Amplifier turn-on time 2.4 µs toff Amplifier turn-off time 0.35 Notes: (1)Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 5.5: "Long term input offset voltage drift"). (2)When used in comparator mode, with high differential input voltage, during a long period of time with VCC close to 16 V and Vicm>VCC/2, Vio can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
Table 6: Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit Vio Input offset voltage Vicm = 2 V (all order codes except TSX922IYST and TSX922IYDT) mV Tmin < Top < Tmax Vicm = 2 V (TSX922IYST and TSX922IYDT order codes only) Tmin < Top < Tmax 6.5 ∆Vio/∆T Input offset voltage drift All order codes except TSX922IYST and TSX922IYDT 2 10 μV/°C TSX922IYST and TSX922IYDT order codes only 2 15 ∆Vio Long-term input offset voltage drift (1)(2) TSX920/TSX921 1.73 nV/√month TSX922/TSX923 2.26 Iib Input bias current Vout = VCC/2 10 100 pA Tmin < Top < Tmax 200 Iio Input offset current Vout = VCC/2 10 100 Tmin < Top < Tmax 200 RIN Input resistance TΩ CIN Input capacitance pF CMRR Common mode rejection ratio 20 log (ΔVic/ΔVio) Vicm = -0.1 V to 13 V, VOUT = VCC/2 73 85 dB Tmin < Top < Tmax 71 Vicm = -0.1 V to 16.1 V, VOUT = VCC/2 67 76 Tmin < Top < Tmax 65 SVRR Supply voltage rejection ratio VCC = 4.5 V tο 16 V 73 85 Tmin < Top < Tmax 71 Avd Large signal voltage gain RL= 2 kΩ, Vout = 0.3 V to 15.7 V 100 105 Tmin < Top < Tmax 90 RL= 10 kΩ, Vout = 0.2 V to 15.8 V 100 113 Tmin < Top < Tmax 90 VOH High-level output voltage RL= 2 kΩ tο VCC/2 150 200 mV from VCC+ Tmin < Top < Tmax 230 RL= 10 kΩ tο VCC/2 43 50 Tmin < Top < Tmax VOL Low-level output voltage RL= 2 kΩ tο VCC/2 140 200 mV Tmin < Top < Tmax 230 RL= 10 kΩ tο VCC/2 30 50 Tmin < Top < Tmax
Symbol Parameter Conditions Min. Typ. Max. Unit Iout Isink Vout = 16 V 45 50 mA Tmin < Top < Tmax 40 Isource Vout = 0 V 65 74 Tmin < Top < Tmax 60 ICC Supply current (per amplifier) No load, Vout = VCC/2 2.8 3.4 Tmin < Top < Tmax 3.4 GBP Gain bandwidth product RL = 10 kΩ, CL = 20 pF, G = 20 dB MHz FU Unity gain frequency RL = 10 kΩ, CL = 20 pF ɸm Phase margin Degrees Gm Gain margin 5.9 dB SR+ Positive slew rate Av = 1, Vout = 0.5 to 15.5 V, measured between 10 % to 90 % 16.2 V/μs SR- Negative slew rate Av = 1, Vout = 15.5 to 0.5 V, measured between 90 % to 10 % 17.2 en Equivalent input noise voltage f = 10 kHz 16.5 nV√Hz f = 100 kHz 11.8 ∫en Low-frequency peak-to- peak input noise Bandwidth: f = 0.1 to 10 Hz 8.58 µVpp THD+N Total harmonic distortion + noise f = 1 kHz, Av = 1, RL = 10 kΩ, Vout = 4 Vrms 0.0003 tS Setting time Gain = 1, 100 mV input voltage, 0.1 % of final value 245 ns Gain = 1, 100 mV input voltage, 1 % of final value 178 Shutdown characteristics (TSX920 and TSX923 only) ICC_shdn Supply current in shutdown mode (per amplifier) SHDN = VCC- 7 15 µΑ Tmin < Top < Tmax ton Amplifier turn-on time 1.5 µs toff Amplifier turn-off time 0.2 Notes: (1)Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 5.5: "Long term input offset voltage drift"). (2)When used in comparator mode, with high differential input voltage, during a long period of time with VCC close to 16 V and Vicm>VCC/2, Vio can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
4 Electrical characteristic curves
Figure 2: Supply current vs.supply voltage Figure 3: Distribution of input offset voltage at VCC = 4.5 V Figure 4: Distribution of input offset voltage at VCC = 10 V Figure 5: Distribution of input offset voltage at VCC = 16 V Figure 6: Input offset voltage vs. temperature at VCC = 16 V Figure 7: Distribution of input offset voltage drift over temperature
5 Application information
5.1 Operating voltages
The TSX92x operational amplifiers can operate from 4 V to 16 V. The parameters are fully specified at 4.5 V, 10 V, and 16 V power supplies. However, parameters are very stable in the full VCC range. Additionally, main specifications are guaranteed in the extended temperature range from -40 to 125 °C.
5.2 Rail-to-rail input
The TSX92x series is designed with two complementary PMOS and NMOS input differential pairs. The device has a rail-to-rail input and the input common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V. However, the performance of this device is clearly optimized for the PMOS differential pairs (which means from (VCC-) - 0.1 V to (VCC+) - 2 V). Beyond (VCC+) - 2 V, the operational amplifier is still functional but with downgraded performances (see Figure 19). Performances are still suitable for a large number of applications requiring the rail-to-rail input feature. The TSX92x operational amplifiers are designed to prevent phase reversal.
5.3 Input pin voltage range
The TSX92x operational amplifiers have internal ESD diode protections on the i nputs. These diodes are connected between the input and each supply rail to protect MOSFETs inputs from electrostatic discharges. Thus, if the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current could flow through them. To prevent any permanent damage, this current must be limited to 10 mA. This can be done by adding a resistor in series with the input pin (Figure 38: "Limiting input current with a series resistor"). The resistor value has to be calculated for a 10 mA current limitation on the input pins. Figure 38: Limiting input current with a series resistor
5.4 Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 with T = -40 °C and 125 °C. The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk (process capability index) greater than 2.
5.5 Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used: Voltage acceleration, by changing the applied voltage Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate ∆Vio ∆T max Vio T Vio 25 T 25 °C– = °C AFV e β VS VU– AFT e Ea TU TS
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. Equation 5 To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration. AF AFT AFV×= Months AF 1000 h× 12 months 24 h 365.25 days× ×= / VCC maxVop with Vicm VCC 2= = ∆Vio Viodrift month s
5.6 Capacitive load
Driving a large capacitive load can cause stability issues. Increasing the load capacitance produces gain peaking in the frequency response, with overshooting and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB the op -amp might become unstable. Generally, the unity gain configuration is the worst configuration for stability and the ability to drive large capacitive loads. Figure 39: "Stability criteria with a serial resistor" shows the serial resistor (Riso) that must be added to the output, to make the system stable. Figure 39: Stability criteria with a serial resistor Figure 40: Test configuration for Riso
5.7 High-side current sensing
TSX92x rail to rail input devices can be used to measure a small differential voltage on a high side shunt resistor and translate it into a ground referenced output voltage. The gain is fixed by external resistance. Figure 41: High-side current sensing configuration Vout can be expressed as follows: Equation 8 Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 8 can be simplified as follows: Equation 9 With the TSX92x operational amplifiers, the high side current measurement must be made by respecting the common mode voltage of the amplifier: (VCC-) - 0.1 V to (VCC+) + 0.1 V. If the application requires a higher common voltage please refer to the TSC high side current sensing family. Vout Rshun t I 1 Rg2 Rg2 Rf2+ 1 Rf1 Rg1 –× Ip Rg2 Rf2 Rg2 Rf2 Rf1 Rg1 ln Rf1 Vio 1 Rf1 Rg1 +––+= + + ×× + × Vout Rshunt I Rf Rg × Vio 1 Rf Rg – Rf Iio×+= +
5.8 High-speed photodiode
The TSX92x series is an excellent choice for current to voltage (I-V) conversions. Due to the CMOS technology, the input bias currents are extremely low. Moreover, the low noise and high unity-gain bandwidth of the TSX92x operational amplifiers make them particularly suitable for high-speed photodiode preamplifier applications. The photodiode is considered as a capacitive current source. The input capacitance, C IN, includes the parasitic input Common mode capacitance, CCM (3pF), and the input differential mode capacitance, CDIFF (8pF). CIN acts in parallel with the intrinsic capacitance of the photodiode, CD. At higher frequencies, the capacitors affect the circuit response. The output capacitance of a current sensor has a strong effect on the stability of the op -amp feedback loop. CF stabilizes the gain and limits the transimpedance bandwidth. To ensure good stability and to obtain good noise performance, CF can be set as shown in Equation 10. Equation 10 where, CIN = CCM + CDIFF = 11 pF CDIFF is the differential input capacitance: 8 pF typical CCM is the Common mode input capacitance: 3 pF typical CD is the intrinsic capacitance of the photodiode CSMR is the parasitic capacitance of the surface mount RF resistor: 0.2 pF typical FGBP is the gain bandwidth product: 10 MHz at 16 V RF fixes the gain as shown in Equation 11. Equation 11 VOUT = RF x ID Figure 42: High-speed photodiode
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
6.1 SOT23-5 package information
Figure 43: SOT23-5 package outline Table 7: SOT23-5 mechanical data Ref. Dimensions Millimeters Inches 0.15 0.006 1.90 0.075 e 0.95 0.037 K 0 degrees 10 degrees 0 degrees 10 degrees
6.2 SOT23-6 package information
Figure 44: SOT23-6 package outline Table 8: SOT23-6 mechanical data Ref. Dimensions Millimeters Inches A 0.90 1.45 0.035 0.057 0.10 0.004 A2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.013 0.019 c 0.09 0.20 0.003 0.008 D 2.80 3.05 0.110 0.120 E 1.50 1.75 0.060 0.069 e 0.95 0.037 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ 0 ° 10 ° 0 ° 10 °
6.3 MiniSO8 package information
Figure 45: MiniSO8 package outline Table 9: MiniSO8 mechanical data Ref. Dimensions Millimeters Inches A 1.1 0.043 A1 0 0.15 0 0.006 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 e 0.65 0.026 0.95 0.037 0.25 0.010 k 0° 8° 0° ccc 0.10 0.004
6.4 SO8 package information
Figure 46: SO8 package outline Table 10: SO8 mechanical data Ref. Dimensions Millimeters Inches A 1.75 0.069 A1 0.10 0.25 0.004 0.010 A2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 e 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 1.04 0.040 k 1° 8° 1° ccc 0.10 0.004
6.5 DFN8 2x2 package information
Figure 47: DFN8 2x2 package outline Table 11: DFN8 2x2 mechanical data Ref. Dimensions Millimeters Inches D 2.00 0.079 E 2.00 0.079 e 0.50 0.020 N 8
6.6 MiniSO10 package information
Figure 48: MiniSO10 package outline Table 12: MiniSO-10 package mechanical data Ref. Dimensions Millimeters Inches A 1.10 0.043 e 0.50 0.020 0.95 0.037 aaa 0.10 0.004
7 Ordering information
Table 13: Order codes Order code Temperature range Package Packing Marking TSX920ILT -40 °C to 125 °C SOT23-6 Tape and reel K304 TSX921ILT SΟΤ23-5 TSX921IYLT (1) K305 TSX922IDT SO8 TSX922I TSX922IYDT (1) SX922IY TSX922IST MiniSO8 K305 TSX922IQ2T DFN8 2x2 K26 TSX922IYST (1) MiniSO8 (automotive grade) K312 TSX922IYDT (1) SO8 (automotive grade) SX922IY TSX923IST MiniSO10 K305 Notes: (1)Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent.
8 Revision history
Table 14: Document revision history Date Revision Changes 12-Apr-2013 1 Initial release 27-Jun-2013 2 Added TSX920,TSX922, TSX923 devices. Added packages for TSX920,TSX922, and TSX923. Added shutdown characteristics in Table 4, Table 5, and Table 6. Added Figure 35, Figure 36, and Figure 37. Updated Table 13 for new order codes. 10-Dec-2013 3 Added long-term input offset voltage drift parameter in Table 4, Table 5, and Table 6. Added Section 5.4: Input offset voltage drift over temperature in Section 5: Application information. Added Section 5.5: Long-term input offset voltage drift section in Section 5: Application information. 14-Jan-2016 4 Updated document layout Table 4, Table 5, and Table 6: updated Vio and DVio/DT parameters Table 7: updated inches dimension "B" (typ) and "L" (typ and max) to align with rounded-off values of POA. Table 10: updated minimum mm dimensions for "k" Table 13: "Order codes": added order codes TSX922IYST and TSX922IYDT.