TSX7191 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Package pin connections
  • 2 Absolute maximum ratings and operating conditions
  • 3 Electrical characteristics
  • 4 Application information
  • 4.1 Operating voltages
  • 4.2 Input pin voltage ranges
  • 4.3 Rail-to-rail input
  • 4.4 Rail-to-rail output
  • 4.5 Input offset voltage drift over temperature
  • 4.6 Long term input offset voltage drift
  • 4.7 High values of input differential voltage
  • 4.8 Capacitive load
  • 4.9 PCB layout recommendations
  • 4.10 Optimized application recommendation
  • 5 Package information
  • 5.1 SOT23-5 package information
  • 6 Ordering information
  • 7 Revision history

Features

Low input offset voltage: 200 µV max. Rail-to-rail input and output Low current consumption: 850 µA max. Gain bandwidth product: 9 MHz Low supply voltage: 2.7 - 16 V Stable when used with Gain ≥ 10 Low input bias current: 50 pA max. High ESD tolerance: 4 kV HBM Extended temp. range: -40 °C to +125 °C Automotive qualification

Related products

See the TSX711 for lower speeds with similar precision See the TSX561 for low-power features See the TSX631 for micro-power features See the TSX921 for higher speeds

Applications

Battery-powered instrumentation Instrumentation amplifier Active filtering High-impedance sensor interface Current sensing (high and low side)

Description

The TSX7191, TSX7191A single, operational amplifier (op amp) offers high precision functioning with low input offset voltage down to a maximum of 200 µV at 25 °C. In addition, its rail- to-rail input and output functionality allows this product to be used on full range input and output without limitation. This is particularly useful for a low-voltage supply such as 2.7 V that the TSX7191, TSX7191A is able to operate with. Thus, the TSX7191, TSX7191A has the great advantage of offering a large span of supply voltages, ranging from 2.7 V to 16 V. It can be used in multiple applications with a unique reference. Low input bias current performance makes the TSX7191, TSX7191A perfect when used for signal conditioning in sensor interface applications. In addition, low-side and high-side current measurements can be easily made thanks to rail-to-rail functionality. The TSX7191, TSX7191A is a decompensated amplifier and must be used with a gain greater than 10 to ensure stability. High ESD tolerance (4 kV HBM) and a wide temperature range are also good arguments to use the TSX7191, TSX7191A in the automotive market segment.

1 Package pin connections

Figure 1: Pin connections (top view)

Absolute maximum ratings and operating conditions TSX7191, TSX7191A

2 Absolute maximum ratings and operating conditions

Table 1: Absolute maximum ratings (AMR) Symbol Parameter Value Unit VCC Supply voltage (1) 18 V Vid Differential input voltage (2) ±VCC mV Vin Input voltage VCC- - 0.2 to VCC++ 0.2 V Iin Input current (3) 10 mA Tstg Storage temperature -65 to +150 °C Rthja Thermal resistance junction to ambient (4) (5) 250 °C/W Tj Maximum junction temperature 150 °C ESD HBM: human body model (6) 4000 V MM: machine model (7) 100 CDM: charged device model (8) 1500 Latch-up immunity 200 mA Notes: (1)All voltage values, except the differential voltage are with respect to the network ground terminal. (2)Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. See Section 4.7 for the precautions to follow when using the TSX711 with a high differential input voltage. (3)Input current must be limited by a resistor in series with the inputs. (4)Rth are typical values. (5)Short-circuits can cause excessive heating and destructive dissipation. (6)According to JEDEC standard JESD22-A114F. (7)According to JEDEC standard JESD22-A115A. (8)According to ANSI/ESD STM5.3.1 Table 2: Operating conditions Symbol Parameter Value Unit VCC Supply voltage 2.7 to 16 V Vicm Common mode input voltage range VCC- - 0.1 to VCC+ + 0.1 Toper Operating free air temperature range -40 to +125 °C

3 Electrical characteristics

Table 3: Electrical characteristics at VCC+ = +4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit Vio Input offset voltage TSX7191, Vicm = VCC/2 200 μV Tmin < Top < +85 °C 365 Tmin < Top < +125 °C 450 TSX7191A, Vicm = VCC/2 100 Tmin < Top < +85 °C 265 Tmin < Top < +125 °C 350 ΔVio/ΔT Input offset voltage drift (1) 2.5 µV/°C ΔVio Long term input offset voltage drift (2) T = 25 °C Iib Input bias current (1) Vout = VCC/2 1 50 pA Tmin < Top < Tmax 200 Iio Input offset current (1) Vout = VCC/2 1 50 Tmin < Top < Tmax 200 RIN Input resistance TΩ CIN Input capacitance 12.5 pF CMRR Common mode rejection ratio 20 log (ΔVic/ΔVio) Vicm = -0.1 to 4.1 V, Vout = VCC/2 84 102 dB Tmin < Top < Tmax 83 Vicm = -0.1 to 2 V, Vout = VCC/2 100 122 Tmin < Top < Tmax 94 Avd Large signal voltage gain RL= 2 kΩ, Vout = 0.3 to 3.7 V 110 136 Tmin < Top < Tmax 96 RL= 10 kΩ, Vout = 0.2 to 3.8 V 110 140 Tmin < Top < Tmax 96 VOH High level output voltage (voltage drop from VCC+) RL= 2 kΩ to VCC/2 28 50 mV Tmin < Top < Tmax RL= 10 kΩ tο VCC/2 6 15 Tmin < Top < Tmax VOL Low level output voltage RL= 2 kΩ tο VCC/2 23 50 Tmin < Top < Tmax RL= 10 kΩ tο VCC/2 5 15 Tmin < Top < Tmax

Symbol Parameter Conditions Min. Typ. Max. Unit Iout Isink Vout = VCC 35 45 mA Tmin < Top < Tmax 20 Isource Vout = 0 V 35 45 Tmin < Top < Tmax 20 ICC Supply current per amplifier No load, Vout = VCC/2 570 800 μA Tmin < Top < Tmax 900 GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 5 7.7 MHz ɸm Phase margin Gain = 10, RL = 10 kΩ, CL = 100 pF Degrees SRn Negative slew rate Av = 10, Vout = 3 VPP, 10 % to 90 % 1.3 2.3 V/μs Tmin < Top < Tmax 1.0 SRp Positive slew rate Av = 10, Vout = 3 VPP, 10 % to 90 % 1.5 2.5 Tmin < Top < Tmax 1.1 en Equivalent input noise voltage f = 1 kHz f = 10 kHz THD+N Total harmonic distortion + noise f =1 kHz, Av = 10, RL= 10 kΩ, BW = 22 kHz, Vout = 3VPP 0.003 Notes: (1)Maximum values are guaranteed by design. (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).

Table 4: Electrical characteristics at VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit Vio Input offset voltage TSX7191, Vicm = VCC/2 200 μV Tmin < Top < +85 °C 365 Tmin < Top < +125 °C 450 TSX7191A, Vicm = VCC/2 100 Tmin < Top < +85 °C 265 Tmin < Top < +125 °C 350 ΔVio/ΔT Input offset voltage drift (1) 2.5 μV/°C ΔVio Long term input offset voltage drift (2) T = 25 °C Iib Input bias current (1) Vout = VCC/2 1 50 pA Tmin < Top < Tmax 200 Iio Input offset current (1) Vout = VCC/2 1 50 Tmin < Top < Tmax 200 RIN Input resistance TΩ CIN Input capacitance 12.5 pF CMRR Common mode rejection ratio 20 log (ΔVic/ΔVio) Vicm = -0.1 to 10.1 V, Vout = VCC/2 90 102 dB Tmin < Top < Tmax 86 Vicm = -0.1 to 8 V, Vout = VCC/2 105 117 Tmin < Top < Tmax 95 Avd Large signal voltage gain RL= 2 kΩ, Vout = 0.3 to 9.7 V 110 140 Tmin < Top < Tmax 100 RL= 10 kΩ, Vout = 0.2 to 9.8 V 110 Tmin < Top < Tmax 100 VOH High level output voltage (voltage drop from VCC+) RL= 2 kΩ tο VCC/2 45 70 mV Tmin < Top < Tmax RL= 10 kΩ tο VCC/2 10 30 Tmin < Top < Tmax VOL Low level output voltage RL= 2 kΩ tο VCC/2 42 70 Tmin < Top < Tmax RL= 10 kΩ tο VCC/2 9 30 Tmin < Top < Tmax Iout Isink Vout = VCC 50 70 mA Tmin < Top < Tmax 40 Isource Vout = 0 V 50 69 Tmin < Top < Tmax 40

Symbol Parameter Conditions Min. Typ. Max. Unit ICC Supply current per amplifier No load, Vout = VCC/2 630 850 μA Tmin < Top < Tmax 1000 GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 5 9 MHz ɸm Phase margin G = 10, RL = 10 kΩ, CL = 100 pF Degrees SRn Negative slew rate Av = 10, Vout = 8 VPP, 10 % to 90 % 1.3 2.3 V/μs Tmin < Top < Tmax 1.0 SRp Positive slew rate Av = 10, Vout = 8 VPP, 10 % to 90 % 1.5 2.5 Tmin < Top < Tmax 1.1 en Equivalent input noise voltage f = 1 kHz f = 10 kHz THD+N Total harmonic distortion + noise f = 1 kHz, Av = 10, RL= 10 kΩ, BW = 22 kHz, Vout = 9 VPP 0.0001 Notes: (1)Maximum values are guaranteed by design. (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).

Table 5: Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit Vio Input offset voltage TSX7191, Vicm = VCC/2 200 μV Tmin < Top < +85 °C 365 Tmin < Top < +125 °C 450 TSX7191A, Vicm = VCC/2 100 Tmin < Top < +85 °C 265 Tmin < Top < +125 °C 350 ΔVio/ΔT Input offset voltage drift (1) 2.5 μV/°C ΔVio Long term input offset voltage drift (2) T = 25 °C 500 Iib Input bias current (1) Vout = VCC/2 1 50 pA Tmin < Top < Tmax 200 Iio Input offset current (1) Vout = VCC/2 1 50 Tmin < Top < Tmax 200 RIN Input resistance TΩ CIN Input capacitance 12.5 pF CMRR Common mode rejection ratio 20 log (ΔVicm/ΔVio) Vicm = -0.1 to 16.1 V, Vout = VCC/2 94 113 dB Tmin < Top < Tmax 90 Vicm = -0.1 to 14 V, Vout = VCC/2 110 116 Tmin < Top < Tmax 96 SVRR Supply voltage rejection ratio 20 log (ΔVcc/ΔVio) Vcc = 4 to 16 V 100 131 Tmin < Top < Tmax 90 Avd Large signal voltage gain RL= 2 kΩ, Vout = 0.3 to 15.7 V 110 146 Tmin < Top < Tmax 100 RL= 10 kΩ, Vout = 0.2 to 15.8 V 110 149 Tmin < Top < Tmax 100 VOH High level output voltage (voltage drop from VCC+) RL= 2 kΩ 100 130 mV Tmin < Top < Tmax 150 RL= 10 kΩ 16 40 Tmin < Top < Tmax VOL Low level output voltage RL= 2 kΩ 70 130 Tmin < Top < Tmax 150 RL= 10 kΩ 15 40 Tmin < Top < Tmax

Symbol Parameter Conditions Min. Typ. Max. Unit Iout Isink Vout = VCC 50 71 mA Tmin < Top < Tmax 45 Isource Vout = 0 V 50 68 Tmin < Top < Tmax 45 ICC Supply current per amplifier No load, Vout = VCC/2 660 900 μA Tmin < Top < Tmax 1000 GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 5 8.5 MHz ɸm Phase margin G = 10, RL = 10 kΩ, CL = 100 pF Degrees SRn Negative slew rate Av = 10, Vout = 10 VPP, 10 % to 90 % 1.5 2.4 V/μs Tmin < Top < Tmax 1.1 SRp Positive slew rate Av = 10, Vout = 10 VPP, 10 % to 90 % 1.5 2.5 Tmin < Top < Tmax 1.1 en Equivalent input noise voltage f = 1 kHz f = 10 kHz THD+N Total harmonic distortion + Noise f = 1 kHz, Av = 10, RL= 10 kΩ, BW = 22 kHz, Vout = 10 VPP 0.0001 Notes: (1)Maximum values are guaranteed by design. (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).

4 Application information

4.1 Operating voltages

The TSX7191, TSX7191A device can operate from 2.7 to 16 V. The parameters are fully specified for 4 V, 10 V, and 16 V power supplies. However, the parameters are very stable in the full VCC range. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to +125 °C.

4.2 Input pin voltage ranges

The TSX7191, TSX7191A device has internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge. If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device. In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in Figure 30. Figure 30: Input current limitation

4.3 Rail-to-rail input

The TSX7191, TSX7191A device has a rail-to-rail input, and the input common mode range is extended from VCC- - 0.1 V to VCC+ + 0.1 V.

4.4 Rail-to-rail output

The operational amplifier output levels can go close to the rails: to a maximum of 30 mV above and below the rail when connected to a 10 kΩ resistive load to VCC/2. 9R2 Vcc Vin

4.5 Input offset voltage drift over temperature

The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 Where T = -40 °C and 125 °C. The TSX7191, TSX7191A datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3.

4.6 Long term input offset voltage drift

To evaluate product reliability, two types of stress acceleration are used: Voltage acceleration, by changing the applied voltage Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate ∆Vio ∆T max Vio T Vio 25 T 25 °C– = °C AFV e β VS VU– AFT e Ea TU TS

k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. Equation 5 To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.

4.7 High values of input differential voltage

In a closed loop configuration, which represents the typical use of an op amp, the input differential voltage is low (close to Vio). However, some specific conditions can lead to higher input differential values, such as: operation in an output saturation state operation at speeds higher than the device bandwidth, with output voltage dynamics limited by slew rate. use of the amplifier in a comparator configuration, hence in open loop Use of the TSX7191, TSX7191A in comparator configuration, especially combined with high temperature and long duration can create a permanent drift of Vio. AF AFT AFV×= Months AF 1000 h× 12 months 24 h 365.25 days× ×= / VCC maxVop with Vicm VCC 2= = ∆Vio Viodrift month s

4.8 Capacitive load

Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable. Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads. Figure 31 shows the serial resistor that must be added to the output, to make a system stable. Figure 32 shows the test configuration using an isolation resistor, Riso. Figure 31: Stability criteria with a serial resistor at different supply voltages Figure 32: Test configuration for Riso 100k 11k Vcc+ Vin Vcc- Riso Cl 10k Vout Ω Ω Ω

4.9 PCB layout recommendations

Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is of ten used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

4.10 Optimized application recommendation

It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help to reduce electromagnetic interference impact.

5 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

5.1 SOT23-5 package information

Figure 33: SOT23-5 package outline Table 6: SOT23-5 mechanical data Ref. Dimensions Millimeters Inches 0.15 0.006 1.90 0.075 e 0.95 0.037 K 0 degrees 10 degrees 0 degrees 10 degrees

6 Ordering information

Table 7: Order codes Order code Temperature range Package Packaging Marking TSX7191ILT -40 to +125 °C SΟΤ23-5 Tape and reel K34 TSX7191AILT K196 TSX7191IYLT (1) K199 TSX7191AIYLT (1) K200 Notes: (1)Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are on-going.

7 Revision history

Table 8: Document revision history Date Revision Changes 29-Sep-2014 1 Initial release 06-Jan-2015 2 Features: updated "stable when used with gain" feature. Applications: removed "DAC buffer" Electrical characteristics: replaced Figure 14 17-Mar-2017 3 Added part number TSX7191A