TSX56X STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Pinout information
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Electrical characteristic curves
- 5 Application information
- 5.1 Operating voltages
- 5.2 Rail-to-rail input
- 5.3 Input offset voltage drift over temperature
- 5.4 Long term input offset voltage drift
- 5.5 PCB layouts
- 5.6 Macromodel
- 6 Package information
- 6.1 SOT23-5 package information
- 6.2 DFN8 2x2 package information
- 6.3 MiniSO8 package information
- 6.4 QFN16 3x3 package information
- 6.5 TSSOP14 package information
- 7 Ordering information
- 8 Revision history
Features
Low power consumption: 235 µA typ. at 5 V Supply voltage: 3 V to 16 V Gain bandwidth product: 900 kHz typ. Low offset voltage “A” version: 600 µV max. Standard version: 1 mV max. Low input bias current: 1 pA typ. High tolerance to ESD: 4 kV Wide temperature range: -40 to 125 °C Automotive qualification Tiny packages available: SOT23-5, DFN8 2 mm x 2 mm, MiniSO8, QFN16 3 mm x 3 mm, and TSSOP14 Benefits Power savings in power-conscious
applications
Easy interfacing with high impedance sensors Related topics See TSX63x series for reduced power consumption (45 mA, 200 kHz) See TSX92x series for higher gain bandwidth products (10 MHz) Industrial and automotive signal conditioning Active filtering Medical instrumentation High impedance sensors
Description
The TSX56x, TSX56xA series of operational amplifiers benefit from STMicroelectronics® 16 V CMOS technology to offer state-of-the-art accuracy and performance in the smallest industrial packages. The TSX56x, TSX56xA have pinouts compatible with industrial standards and offer an outstanding speed/power consumption ratio, 900 kHz gain bandwidth product while consuming only 250 µA at 16 V. Such features make the TSX56x, TSX56xA ideal for sensor interfaces and industrial signal conditioning. The wide temperature range and high ESD tolerance ease use in harsh automotive applications. Table 1: Device summary Version Standard VIO Enhanced VIO Single TSX561 TSX561A Dual TSX562 TSX562A Quad TSX564 TSX564A SOT23-5 (single) MiniSO8 (dual) TSSOP14 (quad) DFN8 2x2 (dual) QFN16 3x3 (quad)
TSX56x, TSX56xA Pinout information
1 Pinout information
Figure 1: Pin connections for each package (top view) Singl e SOT23-5 (TSX561) Dual Quad DFN8 2x2 (TSX562) MiniSO8 (TSX562) QFN16 3x3 (TSX564) TSSOP14 (TSX564)
Absolute maximum ratings and operating conditions TSX56x, TSX56xA
2 Absolute maximum ratings and operating conditions
Table 2: Absolute maximum ratings (AMR) Symbol Parameter Value Unit VCC Supply voltage (1) 18 V Vid Differential input voltage (2) ±VCC Vin Input voltage (3) (VCC-) - 0.2 to (VCC+) + 0.2 Iin Input current (4) 10 mA Tstg Storage temperature -65 to 150 Tj Maximum junction temperature 150 Rthja Thermal resistance junction-to-ambient (5) (6) SOT23-5 250 °C/W DFN8 2x2 120 MiniSO8 190 QFN16 3x3 80 TSSOP14 100 Rthjc Thermal resistance junction-to-case DFN8 2x2 33 QFN16 3x3 30 ESD HBM: human body model (7) 4 kV MM: machine model for TSX561 (8) 200 V MM: machine model for TSX562 and TSX564 (8) 100 CDM: charged device model (9) 1.5 kV Latch-up immunity 200 mA Notes: (1)All voltage values, except the differential voltage are with respect to the network ground terminal. (2)The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. (3)Vcc - Vin must not exceed 18 V, Vin must not exceed 18 V (4)Input current must be limited by a resistor in series with the inputs. (5)Rth are typical values. (6)Short-circuits can cause excessive heating and destructive dissipation. (7)Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. (8)Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating. (9)Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground.
TSX56x, TSX56xA Absolute maximum ratings and operating conditions Table 3: Operating conditions Symbol Parameter Value Unit VCC Supply voltage 3 to 16 V Vicm Common-mode input voltage range (VCC-) - 0.1 to (VCC+) + 0.1 Toper Operating free-air temperature range -40 to 125 °C
3 Electrical characteristics
Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSX56xA, T = 25 °C 600 μV TSX56xA, -40 °C < T < 125 °C 1800 TSX56x, T = 25 °C mV TSX56x, -40 °C < T < 125 °C 2.2 ΔVio/ΔT Input offset voltage drift -40 °C < T < 125 °C (1) 2 12 µV/°C Iib Input bias current, Vout = VCC/2 T = 25 °C 1 100 (2) pA 1 200 (2) Iio Input offset current, Vout = VCC/2 T = 25 °C 1 100 (2) 1 200 (2) CMR1 Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC - 1.5 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 63 80 dB -40 °C < T < 125 °C 59 CMR2 Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC + 0.1 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 47 66 -40 °C < T < 125 °C 45 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V), RL > 1 MΩ T = 25 °C 85 -40 °C < T < 125 °C 83 VOH High-level output voltage, VOH = VCC - Vout T = 25 °C mV 100 VOL Low-level output voltage T = 25 °C 100 Iout Isink, Vout = VCC T = 25 °C 4.3 5.3 mA Isource, Vout = 0 V T = 25 °C 3.3 4.3 ICC Supply current, per channel, Vout = VCC/2, RL > 1 MΩ T = 25 °C 220 300 μA 350 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 600 800 kHz Fu Unity gain frequency 690 ɸm Phase margin Degrees Gm Gain margin dB
TSX56x, TSX56xA Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to VCC - 0.5 V V/μs en Equivalent input noise voltage density f = 1 kHz nV/√Hz f = 10 kHz ∫en Low-frequency peak-to- peak input noise Bandwidth, f = 0.1 to 10 Hz µVpp THD+N Total harmonic distortion + noise Follower configuration, fin = 1 kHz, RL = 100 kΩ, Vicm = (VCC -1.5 V)/2, BW = 22 kHz, Vout = 1 Vpp 0.004 Notes: (1)See Section 5.3: "Input offset voltage drift over temperature" (2)Guaranteed by design
Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSX56xA, T = 25 °C 600 μV TSX56xA, -40 °C < T < 125 °C 1800 TSX56x, T = 25 °C mV TSX56x, -40 °C < T < 125 °C 2.2 ΔVio/ΔT Input offset voltage drift -40 °C < T < 125 °C (1) 2 12 µV/°C ΔVio Long-term input offset voltage drift T = 25 °C (2) nV/ √month Iib Input bias current, Vout = VCC/2 T = 25 °C 1 100 (3) pA 1 200 (3) Iio Input offset current, Vout = VCC/2 T = 25 °C 1 100 (3) 1 200 (3) CMR1 Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC - 1.5 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 66 84 dB -40 °C < T < 125 °C 63 CMR2 Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC + 0.1 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 50 69 -40 °C < T < 125 °C 47 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V), RL > 1 MΩ T = 25 °C 85 -40 °C < T < 125 °C 83 VOH High-level output voltage, VOH = VCC - Vout RL = 10 kΩ, T = 25 °C mV RL = 10 kΩ, -40 °C < T < 125 °C 100 VOL Low-level output voltage RL = 10 kΩ, T = 25 °C RL = 10 kΩ, -40 °C < T < 125 °C 100 Iout Isink Vout = VCC, T = 25 °C 11 14 mA Vout = VCC, -40 °C < T < 125 °C 8 Isource Vout = 0 V, T = 25 °C 9 12 Vout = 0 V, -40 °C < T < 125 °C 7 ICC Supply current, per channel, Vout = VCC/2, RL > 1 MΩ T = 25 °C 235 350 μA 400 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 700 850 kHz Fu Unity gain frequency 730 ɸm Phase margin Degrees Gm Gain margin dB
TSX56x, TSX56xA Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to VCC - 0.5 V 1.1 V/μs en Equivalent input noise voltage density f = 1 kHz nV/√Hz f = 10 kHz ∫en Low-frequency peak-to- peak input noise Bandwidth, f = 0.1 to 10 Hz µVpp THD+N Total harmonic distortion + noise Follower configuration, fin = 1 kHz, RL = 100 kΩ, Vicm = (VCC -1.5 V)/2, BW = 22 kHz, Vout = 2 Vpp 0.002 Notes: (1)See Section 5.3: "Input offset voltage drift over temperature" (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. (3)Guaranteed by design
Table 6: Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance Vio Offset voltage TSX56xA, T = 25 °C 600 μV TSX56xA, -40 °C < T < 125 °C 1800 TSX56x, T = 25 °C mV TSX56x, -40 °C < T < 125 °C 2.2 ΔVio/ΔT Input offset voltage drift -40 °C < T < 125 °C (1) 2 12 µV/°C ΔVio Long-term input offset voltage drift T = 25 °C (2) 1.6 nV/ √month Iib Input bias current, Vout = VCC/2 T = 25 °C 1 100 (3) pA 1 200 (3) Iio Input offset current, Vout = VCC/2 T = 25 °C 1 100 (3) 1 200 (3) CMR1 Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC - 1.5 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 76 95 dB -40 °C < T < 125 °C 72 CMR2 Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC + 0.1 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 60 78 -40 °C < T < 125 °C 56 SVR Common mode rejection ratio, 20 log (ΔVCC/ΔVio), VCC = 3 V to 16 V, Vout = Vicm = VCC/2 T = 25 °C 76 90 -40 °C < T < 125 °C 72 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V), RL > 1 MΩ T = 25 °C 85 -40 °C < T < 125 °C 83 VOH High-level output voltage, VOH = VCC - Vout RL = 10 kΩ, T = 25 °C mV RL = 10 kΩ, -40 °C < T < 125 °C 100 VOL Low-level output voltage RL = 10 kΩ, T = 25 °C RL = 10 kΩ, -40 °C < T < 125 °C 100 Iout Isink Vout = VCC, T = 25 °C 40 92 mA Vout = VCC, -40 °C < T < 125 °C 35 Isource Vout = 0 V, T = 25 °C 30 90 Vout = 0 V, -40 °C < T < 125 °C 25 ICC Supply current, per channel, Vout = VCC/2, RL > 1 MΩ T = 25 °C 250 360 μA 400
TSX56x, TSX56xA Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 750 900 kHz Fu Unity gain frequency 750 ɸm Phase margin Degrees Gm Gain margin dB SR Slew rate RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to VCC - 0.5 V 1.1 V/μs en Equivalent input noise voltage density f = 1 kHz nV/√Hz f = 10 kHz ∫en Low-frequency peak-to- peak input noise Bandwidth, f = 0.1 to 10 Hz µVpp THD+N Total harmonic distortion + noise Follower configuration, fin = 1 kHz, RL = 100 kΩ, Vicm = (VCC -1.5 V)/2, BW = 22 kHz, Vout = 5 Vpp 0.000 Notes: (1)See Section 5.3: "Input offset voltage drift over temperature" (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. (3)Guaranteed by design
4 Electrical characteristic curves
Figure 2: Supply current vs. supply voltage at Vicm = VCC/2 Figure 3: Input offset voltage distribution at VCC = 16 V and Vicm = 8 V Figure 4: Input offset voltage temperature coefficient distribution at VCC = 16 V, Vicm = 8 V Figure 5: Input offset voltage vs. input common-mode voltage at VCC = 12 V Figure 6: Input offset voltage vs. temperature at VCC = 16 V -40-40 -20-20 00 2020 4040 6060 8080 100100 120120 -2500 -2000-2000 -1500 -1000-1000 -500 500 10001000 1500 20002000 2500 Limit for TSX56x VCC = 16 V, Vicm = 8 V Limit for TSX56xA
5 Application information
5.1 Operating voltages
The amplifiers of the TSX56x and TSX56xA series can operate from 3 V to 16 V. Their parameters are fully specified at 3.3 V, 5 V, and 16 V power supplies. However, the parameters are very stable in the full VCC range. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 ° C.
5.2 Rail-to-rail input
The TSX56x and TSX56xA devices are built with two complementary PMOS and NMOS input differential pairs. The devices have a rail-to-rail input, and the input common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V. However, the performance of these devices is clearly optimized for the PMOS differential pairs (which means from (VCC-) - 0.1 V to (VCC+) - 1.5 V). Beyond (VCC+) - 1.5 V, the operational amplifiers are still functional but with degraded performance, as can be observed in the electrical characteristics section of this datasheet (mainly Vio and GBP). These performances are suitable for a number of applications that need to be rail-to-rail. The devices are designed to prevent phase reversal.
5.3 Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effects of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 Where T = -40 °C and 125 °C. The datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 2. ∆Vio ∆T max Vio T Vio 25 T 25 °C– = °C
TSX56x, TSX56xA Application information
5.4 Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used: Voltage acceleration, by changing the applied voltage Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. Equation 5 AFV e β VS VU– AFT e Ea TU TS AF AFT AFV×= Months AF 1000 h× 12 months 24 h 365.25 days× ×= /
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
5.5 PCB layouts
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.
5.6 Macromodel
Accurate macromodels of the TSX56x, TSX56xA devices are available on the STMicroelectronics’ website at: www.st.com. These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSX56x and TSX56xA operational amplifiers. They emulate the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the right operational amplifier, but they do not replace on-board measurements. VCC maxVop with Vicm VCC 2= = ∆Vio Viodrift month s
TSX56x, TSX56xA Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
6.1 SOT23-5 package information
Figure 23: SOT23-5 package outline Table 7: SOT23-5 mechanical data Ref. Dimensions Millimeters Inches 0.15 0.006 1.90 0.075 e 0.95 0.037 K 0 degrees 10 degrees 0 degrees 10 degrees
TSX56x, TSX56xA Package information
6.2 DFN8 2x2 package information
Figure 24: DFN8 2x2 package outline Table 8: DFN8 2x2 mechanical data Ref. Dimensions Millimeters Inches D 2.00 0.079 E 2.00 0.079 e 0.50 0.020
6.3 MiniSO8 package information
Figure 25: MiniSO8 package outline Table 9: MiniSO8 mechanical data Ref. Dimensions Millimeters Inches A 1.1 0.043 A1 0 0.15 0 0.006 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 e 0.65 0.026 0.95 0.037 0.25 0.010 k 0° 8° 0° ccc 0.10 0.004
TSX56x, TSX56xA Package information
6.4 QFN16 3x3 package information
Figure 26: QFN16 3x3 package outline e BOTTOM VIEW Pin#1 ID E CA PLANE SEATING C C 2x D b C C A B B A C SI DEVIEW INDEX AREA (D/ 2xE/ 2) aaa aaa TOP VI EW ccc eee L 5 8 bbb bbb C 1316 R0.11
Table 10: QFN16 3x3 mechanical data Ref. Dimensions Millimeters Inches A 0.50 0.65 0.020 0.026 A1 0 0.05 0 0.002 D 3.00 0.118 E 3.00 0.118 e 0.50 0.020 L 0.30 0.50 0.012 0.020 aaa 0.15 0.006 bbb 0.10 0.004 ccc 0.10 0.004 ddd 0.05 0.002 eee 0.08 0.003
TSX56x, TSX56xA Package information
6.5 TSSOP14 package information
Figure 27: TSSOP14 package outline Table 11: TSSOP14 mechanical data Ref. Dimensions Millimeters Inches A 1.20 0.047 A1 0.05 0.15 0.002 0.004 0.006 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 e 0.65 0.0256 1.00 0.039 k 0° 8° 0° aaa 0.10 0.004 aaa
7 Ordering information
Table 12: Order codes Order code Temperature range Channel number Package Packaging Marking TSX561ILT -40 to 125 °C
1 SΟΤ23-5
TSX561IYLT (1) -40 to 125 °C automotive grade TSX562IYST (1) 2 MiniSO8 TSX564IYPT (1) 4 TSSOP14 TSX5641Y TSX561AILT -40 to 125 °C TSX564AIPT 4 TSSOP14 TSX564AI TSX561AIYLT (1) -40 to 125 °C automotive grade TSX562AIYST (1) 2 MiniSO8 TSX564AIYPT (1) 4 TSSOP14 TSX564AIY Notes: (1)Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent
TSX56x, TSX56xA Revision history
8 Revision history
Table 13: Document revision history Date Revision Changes 06-Aug-2012 1 Initial release. 18-Sep-2012 2 Added TSX562, TSX564, TSX562A, and TSX564A devices. Updated Features, Description, Figure 1, Table 1 (added DFN8, MiniSO8, QFN16, and TSSOP14 package). Updated Table 1 (updated ESD MM values). Updated Table 4 and Table 5 (added footnotes), Section 5 (added Figure 24 to Figure 28 and Table 8 to Table 12), Table 13 (added dual and quad devices). Minor corrections throughout document. 23-May-2013 3 Replaced the silhouette, pinout, package diagram, and mechanical data of the DFN8 2x2 and QFN16 3x3 packages. Added Benefits and Related products. Table 1: updated Rthja values and added Rthjc values for DFN8 2x2 and QFN16 3x3. Updated Section 4.3, Section 4.4, and Section 4.6 Replaced Figure 23: SOT23-5 package mechanical drawing and Table 7: SOT23-5 package mechanical data. 09-Aug-2013 4 Added SO8 package for dual version TSX562 and TSX562A. Table 2: updated for SO8 package Table 13: added order codes TSX562IDT, TSX562IYDT, TSX562AIDT, TSX562AIYDT; updated automotive grade status. 07-Feb-2017 5 Removed SO8 package Table 8: "DFN8 2x2 mechanical data": removed "N" Table 11: "TSSOP14 mechanical data": added "L" and " L1" in inches; updated "aaa" in inches. Table 12: "Order codes": removed TSX562IDT, TSX562IYDT, TSX562AIDT, TSX562AIYDT. Updated terminology