TSV914AIDR

TSV911_17 TI1 | Alldatasheet

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0.1 VBUS 5 V R F 165 k R G 3.4 k VOUT ILOAD TSV91x VSHUNT Copyright © 2017, Texas Instruments Incorporated 0 50 100 150 200 250 300 Overshoot (%) Capacitive Load (pF) Overshoot+ Overshoot- C025 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 TSV91xRail-to-RailInput/Output,8-MHzOperationalAmplifiers

1 Features

1• Rail-to-Rail Input and Output

• Low Noise: 18 nV/√Hz at 1 kHz
• Low Power Consumption: 550 µA (Typical)
• High-Gain Bandwidth: 8 MHz
• Operating Supply Voltage From 2.5 V to 5.5 V
• Low Input Bias Current: 1 pA (Typical)
• Low Input Offset Voltage: 1.9 mV (Maximum)
• Low Offset Voltage Drift: ±0.5 µV/°C (Typical)
• ESD Internal Protection: ±4 kV Human-Body Model (HBM)
• Extended Temperature Range: –40°C to +125°C

2 Applications

• Battery-Powered Applications
• Motor Control
• Power Modules
• HVAC: Heating, Ventilating, and Air Conditioning
• Washing Machines
• Refrigerators
• Medical Instrumentation
• Active Filters
• Sensor Signal Conditioning
• Audio Receiver
• Automotive Infotainment

3 Description

The TSV91x family, which includes single-, dual-, and quad-channel operational amplifiers (op amps), is specifically designed for general-purpose applications. Featuring rail-to-rail input and output (RRIO) swings, wide bandwidth (8 MHz), and low offset voltage (0.3 mV, typical), this family is attractive for a variety of applications that require a good balance between speed and power consumption. The op amps are unity-gain stable and feature an ultra- low input bias current, which enables the family to be used in applications with high-source impedances. The low input bias current allows the devices to be used for sensor interfaces, battery-supplied and portable applications, and active filtering. The robust design of the TSV91x provides ease-of- use to the circuit designer. Features include a unity- gain stable, integrated RFI-EMI rejection filter, no phase reversal in overdrive condition, and high electrostatic discharge (ESD) protection (4-kV HBV). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TSV911 SOT-23 (5) (2) 1.60 mm × 2.90 mm TSV912 SOIC (8) 3.91 mm × 4.90 mm WSON (8) (2) 2.00 mm x 2.00 mm TSV914 SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) (2) 4.40 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package is preview only. Low-Side Motor Control Small-Signal Overshoot vs Load Capacitance

TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents

7.6 Electrical Characteristics: VS (Total Supply Voltage) =

12.3 Receiving Notification of Documentation Updates 23

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (July 2017) to Revision A Page

TSV911,TSV912,TSV914 www.ti.com SBOS878A –JULY 2017–REVISED OCTOBER 2017 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Package preview (2) Device preview

5 Device Comparison Table

DEVICE NO. OF CHANNELS PACKAGE LEADS DBV(1) D DSG(1) PW(1) TSV911 (2) 1 5 — — — TSV912 2 — 8 8 — TSV914 4 — 14 — 14

/c45IN OUT V/c45 +IN TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

6 Pin Configuration and Functions

(1) Package preview Pin Functions: TSV911 PIN I/O DESCRIPTION NAME NO. –IN 4 I Inverting input +IN 3 I Noninverting input OUT 1 O Output V– 2 — Negative (lowest) supply or ground (for single-supply operation) V+ 5 — Positive (highest) supply

OUT□A /c45IN□A +IN□A V/c45 OUT□B /c45IN□B +IN□B Exposed Thermal Die□Pad on Underside(2) OUT□B /c45IN□B +IN□B OUT□A /c45IN□A +IN□A V/c45 TSV911,TSV912,TSV914 www.ti.com SBOS878A –JULY 2017–REVISED OCTOBER 2017 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated 8-Pin SOIC, VSSOP Top View 8-Pin WSON With Exposed Thermal Pad Top View (1) Package preview Pin Functions: TSV912 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply

OUT□D /c45IN□D +IN□D V/c45 OUT□A /c45IN□A +IN□A +IN□C /c45IN□C OUT□C +IN□B /c45IN□B OUT□B A B D C TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated TSV914 D, PW Packages 14-Pin SOIC, TSSOP Top View Pin Functions: TSV914 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B –IN C 9 I Inverting input, channel C +IN C 10 I Noninverting input, channel C –IN D 13 I Inverting input, channel D +IN D 12 I Noninverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) supply or ground (for single-supply operation) V+ 4 — Positive (highest) supply

TSV911,TSV912,TSV914 www.ti.com SBOS878A –JULY 2017–REVISED OCTOBER 2017 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply rails to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1) MIN MAX UNIT Supply voltage 6 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 Current(2) –10 10 mA Output short-circuit(3) Continuous mA Specified, TA –40 125 °CJunction, TJ 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted) VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 2.5 5.5 V Specified temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information: TSV912

THERMAL METRIC(1) TSV912 UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 157.6 °C/W RθJC(top) Junction-to-case(top) thermal resistance 104.6 °C/W RθJB Junction-to-board thermal resistance 99.7 °C/W ψJT Junction-to-top characterization parameter 55.6 °C/W ψJB Junction-to-board characterization parameter 99.2 °C/W

TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: TSV914

THERMAL METRIC(1) TSV914 UNITD (SOIC)

14 PINS

RθJA Junction-to-ambient thermal resistance 106.9 °C/W RθJC(top) Junction-to-case(top) thermal resistance 69 °C/W RθJB Junction-to-board thermal resistance 63 °C/W ψJT Junction-to-top characterization parameter 25.9 °C/W ψJB Junction-to-board characterization parameter 62.7 °C/W

TSV911,TSV912,TSV914 www.ti.com SBOS878A –JULY 2017–REVISED OCTOBER 2017 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Third-order filter; bandwidth = 80 kHz at –3 dB. 7.6 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V ±0.3 ±1.5 mVVS = 5 V TA = –40°C to 125°C ±3 dVOS/dT Drift VS = 5 V TA = –40°C to 125°C ±0.5 µV/°C PSRR Power-supply rejection ratio VS = 2.5 V – 5.5 V, VCM = (V–) ±7 µV/V Channel separation, DC At DC 100 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range VS = 2.5 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V CMRR Common-mode rejection ratio VS = 5.5 V TA = –40°C to 125°C 80 103 dB VS = 5.5 V, VCM = –0.1 V to 5.6 V TA = –40°C to 125°C 57 87 TA = –40°C to 125°C 88 VS = 2.5 V, VCM = –0.1 V to 1.9 V TA = –40°C to 125°C 81 INPUT BIAS CURRENT IB Input bias current ±1 pA IOS Input offset current ±0.05 pA NOISE En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP en Input voltage noise density VS = 5 V, f = 10 kHz 12 nV/√Hz VS = 5 V, f = 1 kHz 18 nV/√Hz in Input current noise density f = 1 kHz 10 fA/√Hz INPUT CAPACITANCE CID Differential 2 pF CIC Common-mode 4 pF OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10 kΩ 100 dB RL = 10 kΩ 104 130 RL = 2 kΩ 100 RL = 2 kΩ 130 FREQUENCY RESPONSE GBP Gain bandwidth product VS = 5 V, G = 1 8 MHz φm Phase margin VS = 5 V, G = 1 55 Degrees SR Slew rate VS = 5 V, G = 1 RL = 2 kΩ CL = 100 pF

4.5 V/µs

To 0.1%, VS = 5 V, 2-V step , G = 1 CL = 100 pF 0.5 µs To 0.01%, VS = 5 V, 2-V step , G = 1 CL = 100 pF 1 tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.2 µs THD + N Total harmonic distortion + noise(1) VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz 0.0008% OUTPUT VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 15 mV VS = 5.5 V, RL = 2 kΩ 50

TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V (continued) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISC Short-circuit current VS = 5 V ±50 mA ZO Open-loop output impedance VS = 5 V, f = 10 MHz 100 Ω POWER SUPPLY IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 mA 550 750 µA VS = 5.5 V, IO = 0 mATA = –40°C to 125°C 1100

7.7 Typical Characteristics

Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage Figure 5. Offset Voltage vs Power Supply Figure 6. Open-Loop Gain and Phase vs Frequency

VIN+ VIN– (Ground) VBIAS2 VBIAS1 Class AB Control Circuitry VO Copyright © 2017, Texas Instruments Incorporated TSV911,TSV912,TSV914 www.ti.com SBOS878A –JULY 2017–REVISED OCTOBER 2017 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TSV91x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TSV91x series to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications and are designed for driving sampling analog-to-digital converters (ADCs).

8.2 Functional Block Diagram

TSV911,TSV912,TSV914 SBOS878A –JULY 2017–REVISED OCTOBER 2017 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Rail-to-Rail Input

The input common-mode voltage range of the TSV91x family extends 100 mV beyond the supply rails for the full supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a complementary input stage: an N- channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region.

8.3.2 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the TSV91x series delivers a robust output drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails.

8.3.3 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TSV91x series is approximately 200 ns.

8.4 Device Functional Modes

The TSV91x family has a single functional mode. These devices are powered on as long as the power-supply

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

input noise voltage of 18 nV / √Hz at 1 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.

9.2 Typical Application

Figure 35 shows the TSV91x configured in a low-side, motor-control application. Figure 35. TSV91x in a Low-Side, Motor-Control Application

9.2.1 Design Requirements

• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV

9.2.2 Detailed Design Procedure

Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RF and RG. Equation 4 is used to size the resistors, RF and RG, to set the gain of the TSV91x to 49.5 V/V. the measured transfer function of the circuit shown in Figure 35.

9.2.3 Application Curve

Figure 36. Low-Side, Current-Sense, Transfer Function

10 Power Supply Recommendations

variance with regard to operating voltage or temperature. impedance power supplies. For more detailed information on bypass capacitor placement, see the section.

10.1 Input and ESD Protection

must be kept to a minimum in noise-sensitive applications. Figure 37. Input Current Protection

11 Layout

11.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 39, keeping RF and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

Figure 38. Schematic Representation for Figure 39 Figure 39. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

resources, tools and software, and quick access to order now. Table 1. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 2-Nov-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TSV912AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TSV912 TSV914AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPD Level-2-260C-1 YEAR -40 to 125 TSV914AD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 2-Nov-2017 Addendum-Page 2

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