TSV912A-Q1_V02 TI | Alldatasheet
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Technical content
TSV91xA-Q1 Automotive Rail-to-Rail Input/Output, 8-MHz Operational Amplifiers
1 Features
- Rail-to-rail input and output
- Low noise: 18 nV/√Hz at 1 kHz
- Low power consumption: 550 µA (typical)
- High-gain bandwidth: 8 MHz
- Operating supply voltage from 2.5 V to 5.5 V
- Low input bias current: 1 pA (typical)
- Low input offset voltage: 1.5 mV (maximum)
- Low offset voltage drift: ±0.5 µV/°C (typical)
- ESD internal protection: ±4-kV human-body model (HBM)
- Extended temperature range: –40°C to 125°C
2 Applications
- Optimized for AEC-Q100 grade 1 applications
- Infotainment and cluster
- Passive safety
- Body electronics and lighting
- HEV/EV inverter and motor control
- On-board (OBC) and wireless charger
- Powertrain current sensor
- Advanced driver assistance systems (ADAS)
- Single-supply, low-side, unidirectional current- sensing circuit
3 Description
The TSV91xA-Q1 family, which includes single-, dual-, and quad-channel operational amplifiers (op amps), is specifically designed for general-purpose automotive applications. Featuring rail-to-rail input and output (RRIO) swings, wide bandwidth (8 MHz), and low offset voltage (0.3 mV, typical), this family is designed for a variety of applications that require a good balance between speed and power consumption. The op amps are unity-gain stable and feature an ultra-low input bias current, which enables the family to be used in applications with high-source impedances. The low input bias current allows the devices to be used for sensor interfaces, and active filtering. The robust design of the TSV91xA-Q1 provides ease- of-use to the circuit designer. Features include a unity- gain stable, integrated RFI-EMI rejection filter, no phase reversal in overdrive condition, and high electrostatic discharge (ESD) protection (4-kV HBM). Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) TSV911A-Q1 SOT-23 (5)(2) 1.60 mm × 2.90 mm TSV912A-Q1 SOIC (8) 3.91 mm × 4.90 mm VSSOP (8) 3.00 mm × 3.00 mm TSV914A-Q1 SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 4.40 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package is preview only for TSV91xA-Q1. ZLOAD RSHUNT 0.1 VBUS 5 V RF 165 k RG 3.4 k VOUT ILOAD TSV91x VSHUNT Low-Side Motor Control 0 50 100 150 200 250 300 Overshoot (%) Capacitive Load (pF) Overshoot+ Overshoot- C025 Small-Signal Overshoot vs Load Capacitance www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: TSV912A-Q1 TSV914A-Q1 TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
12.2 Receiving Notification of Documentation Updates..22
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2020) to Revision B (February 2021) Page Changes from Revision * (June 2020) to Revision A (December 2020) Page TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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5 Device Comparison Table
DEVICE NO. OF CHANNELS PACKAGE LEADS DBV D DGK PW TSV911A-Q1 1 5 — — — TSV912A-Q1 2 — 8 8 — TSV914A-Q1 4 — 14 — 14 www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TSV912A-Q1 TSV914A-Q1
6 Pin Configuration and Functions
OUT□B /c45IN□B +IN□B OUT□A /c45IN□A +IN□A V/c45 Figure 6-1. TSV912A-Q1 D and DGK Package 8-Pin SOIC and VSSOP Top View Table 6-1. Pin Functions: TSV912A-Q1 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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OUT□D /c45IN□D +IN□D V/c45 OUT□A /c45IN□A +IN□A +IN□C /c45IN□C OUT□C +IN□B /c45IN□B OUT□B A B D C Figure 6-2. TSV914A-Q1 D and PW Package 14-Pin SOIC and TSSOP Top View Table 6-2. Pin Functions: TSV914A-Q1 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B –IN C 9 I Inverting input, channel C +IN C 10 I Noninverting input, channel C –IN D 13 I Inverting input, channel D +IN D 12 I Noninverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) supply or ground (for single-supply operation) V+ 4 — Positive (highest) supply www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TSV912A-Q1 TSV914A-Q1
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1) MIN MAX UNIT Supply voltage 6 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential(4) (V+) – (V–) + 0.2 Current(2) –10 10 mA Output short-circuit(3) Continuous mA Specified, TA –40 125 °C Junction, TJ 150 °C Storage, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply rails to 10 mA or less. (3) Short-circuit to ground, one amplifier per package. (4) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage above the maximum specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V Charged-device model (CDM), per AEC Q100-011 ±1500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 2.5 5.5 V Specified temperature –40 125 °C
7.4 Thermal Information: TSV912A-Q1
THERMAL METRIC(1) TSV912A-Q1 UNITD (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 157.6 198.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 104.6 87.2 °C/W RθJB Junction-to-board thermal resistance 99.7 120.3 °C/W ψJT Junction-to-top characterization parameter 55.6 23.8 °C/W ψJB Junction-to-board characterization parameter 99.2 118.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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7.5 Thermal Information: TSV914A-Q1
THERMAL METRIC(1) TSV914A-Q1 UNITD (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 111.1 133.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 67.6 62.1 °C/W RθJB Junction-to-board thermal resistance 67 76.9 °C/W ψJT Junction-to-top characterization parameter 27.4 13.2 °C/W ψJB Junction-to-board characterization parameter 66.6 76.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TSV912A-Q1 TSV914A-Q1
7.6 Electrical Characteristics
VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V ±0.3 ±1.5 mVVS = 5 V TA = –40°C to 125°C ±3 dVOS/dT Drift VS = 5 V TA = –40°C to 125°C ±0.5 µV/°C PSRR Power-supply rejection ratio VS = 2.5 V – 5.5 V, VCM = (V–) ±7 µV/V Channel separation, DC At DC 100 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range VS = 2.5 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V CMRR Common-mode rejection ratio VS = 5.5 V TA = –40°C to 125°C 80 103 dB VS = 5.5 V, VCM = –0.1 V to 5.6 V TA = –40°C to 125°C 57 75 TA = –40°C to 125°C 88 VS = 2.5 V, VCM = –0.1 V to 1.9 V TA = –40°C to 125°C 70 INPUT BIAS CURRENT IB Input bias current ±5 pA IOS Input offset current ±5 pA NOISE En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP en Input voltage noise density VS = 5 V, f = 10 kHz 12 nV/√ Hz VS = 5 V, f = 1 kHz 18 in Input current noise density f = 1 kHz 23 fA/√ Hz INPUT CAPACITANCE CID Differential 2 pF CIC Common-mode 4 pF OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10 kΩ 100 dB RL = 10 kΩ 104 130 RL = 2 kΩ 100 RL = 2 kΩ 130 FREQUENCY RESPONSE GBP Gain bandwidth product VS = 5 V, G = 1 8 MHz φm Phase margin VS = 5 V, G = 1 55 ° SR Slew rate VS = 5 V, G = 1 RL = 2 kΩ CL = 100 pF
4.5 V/µs
To 0.1%, VS = 5 V, 2-V step , G = 1 CL = 100 pF 0.5 µs To 0.01%, VS = 5 V, 2-V step , G = 1 CL = 100 pF 1 tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.2 µs THD + N Total harmonic distortion + noise(1) VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz 0.0008% TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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7.6 Electrical Characteristics (continued)
VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 20 mV VS = 5.5 V, RL = 2 kΩ 60 ISC Short-circuit current VS = 5 V ±50 mA ZO Open-loop output impedance VS = 5 V, f = 10 MHz 100 Ω POWER SUPPLY IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 mA 550 750 µA VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C 1100 (1) Third-order filter; bandwidth = 80 kHz at –3 dB. www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TSV912A-Q1 TSV914A-Q1
7.7 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) -1500 -1250 -1000 -750 -500 -250 250 500 750 1000 1250 1500 Population (%) Offset Voltage (µV) C001 Figure 7-1. Offset Voltage Production Distribution 0.4 0.8 1.2 1.6 2.4 2.8 Population (%) Offset Voltage Drift (µV/C) C002 TA = –40°C to 125°C Figure 7-2. Offset Voltage Drift Distribution ±500 ±400 ±300 ±200 ±100 100 200 300 400 500 ±50 ±25 0 25 50 75 100 125 150 Offset Voltage (µV) Temperature (C) C003 Figure 7-3. Offset Voltage vs Temperature ±2500 ±2000 ±1500 ±1000 ±500 500 1000 1500 2000 2500 -4 -3 -2 -1 0 1 2 3 4 Offset Voltage (µV) Input Common Mode Voltage (V) C005 Figure 7-4. Offset Voltage vs Common-Mode Voltage ±1000 ±500 500 1000 Offset Voltage (µV) Supply Voltage (V) C004 VS = 2.5 V to 5.5 V Figure 7-5. Offset Voltage vs Power Supply Frequency (Hz) Open Loop Voltage Gain (dB) Phase Margin (q) -20 0 0 30 20 60 40 90 60 120 80 150 100 180 120 210 100 1k 10k 100k 1M 10M C006 Gain Phase CL = 10 pF Figure 7-6. Open-Loop Gain and Phase vs Frequency TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Frequency (Hz) Closed Loop Voltage Gain (dB) -40 -30 -20 -10 1k 10k 100k 1M 10M C007 G = +1 G = +10 G = -1 Figure 7-7. Closed-Loop Gain vs Frequency ±50 100 150 200 250 ±50 ±25 0 25 50 75 100 125 Input Bias Current and offset current (pA) Temperature (C) IBN IBP IOS C008 Figure 7-8. Input Bias Current vs Temperature 10 20 30 40 50 60 Output Voltage (V) Output Current (mA) C009 125C 85C 25C -40C 125C 85C 25C -40C Figure 7-9. Output Voltage Swing vs Output Current Frequency (Hz) PSRR and CMRR (dB) 100 120 1k 10k 100k 1M 10M C011 PSRR- PSRR+ CMRR Figure 7-10. CMRR and PSRR vs Frequency (Referred to Input) ±50 ±25 0 25 50 75 100 125 CMRR (µV/V) Temperature (C) C012 VS = 5.5 V VCM = (V–) – 0.1 V to (V+) + 0.1 V RL= 10 kΩ TA= –40°C to 125°C Figure 7-11. CMRR vs Temperature ±50 ±25 0 25 50 75 100 125 150 CMRR (µV/V) Temperature (C) C016 VS = 5.5 V VCM = (V–) –0.1 V to (V +) –1.4 V RL= 10 kΩ TA= –40°C to 125°C Figure 7-12. CMRR vs Temperature www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TSV912A-Q1 TSV914A-Q1
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) ±50 ±25 0 25 50 75 100 125 PSRR (µV/V) Temperature (C) C013 VS = 2.5 V to 5.5 V Figure 7-13. PSRR vs Temperature Voltage (1µV/div) Time (1s/div) C014 VS = 2.5 V to 5.5 V Figure 7-14. 0.1-Hz to 10-Hz Input Voltage Noise Frequency (Hz) Input Voltage Noise Spectral Density (nV/Hz) 100 120 10 100 1k 10k 100k C015 Figure 7-15. Input Voltage Noise Spectral Density vs Frequency Frequency (Hz) THD + N (dB) -120 -115 -110 -105 -100 -95 -90 100 1k 10k C017 VS = 5.5 V VCM = 2.5 V RL = 2 kΩ G = 1 VOUT = 0.5 VRMS BW = 80 kHz Figure 7-16. THD + N vs Frequency ±120 ±100 ±80 ±60 ±40 0.001 0.01 0.1 1 THD + N (dB) Output Voltage Amplitude (VRMS) C018 VS = 5.5 V VCM = 2.5 V RL = 2 kΩ G = 1 BW = 80 kHz f = 1 kHz Figure 7-17. THD + N vs Amplitude ±120 ±100 ±80 ±60 ±40 0.001 0.01 0.1 1 THD + N (dB) Output Voltage Amplitude (VRMS) C019 VS = 5.5 V VCM = 2.5 V RL = 2 kΩ G = –1 BW = 80 kHz f = 1 kHz Figure 7-18. THD + N vs Amplitude TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 500 520 540 560 580 600 Quiescent current (µA) Supply Voltage (V) C020 Figure 7-19. Quiescent Current vs Supply Voltage 100 200 300 400 500 600 700 800 ±50 ±25 0 25 50 75 100 125 Quiescent Current (µA) Temperature (C) C021 Figure 7-20. Quiescent Current vs Temperature Frequency (Hz) Open Loop Output Impedance (:) 120 160 200 10k 100k 1M 10M C024 Figure 7-21. Open-Loop Output Impedance vs Frequency 0 50 100 150 200 250 300 Overshoot (%) Capacitive Load (pF) Overshoot+ Overshoot- C025 RL = 10 kΩ VOUT step = 100 mVp-p Figure 7-22. Small-Signal Overshoot vs Load Capacitance 0 50 100 150 200 250 300 Overshoot (%) Capacitive Load (pF) Overshoot(+) Overshoot(-) C026 V+ = 2.75 V V– = –2.75 V RL = 10 kΩ G = –1 V/V VOUT step = 100 mVp-p Figure 7-23. Small-Signal Overshoot vs Load Capacitance Voltage (1V/div) Time (200 µs/div) Input Output C036 Figure 7-24. No Phase Reversal www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TSV912A-Q1 TSV914A-Q1
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Voltage (2 V/V) Time (1 µs/div) INPUT OUTPUT C028 Figure 7-25. Overload Recovery Voltage (20 mV/div) Time (0.1µs/div) Input Output C030 Figure 7-26. Small-Signal Step Response Voltage (1 V/div) Time (1 µs/div) Input Output C031 V+ = 2.75 V V– = –2.75 V CL = 100 pF G = 1 V/V Figure 7-27. Large-Signal Step Response ±80 ±60 ±40 ±20 ±50 ±25 0 25 50 75 100 125 Short Circuit Current Limit (mA) Temperature (C) Sinking Sourcing C034 Figure 7-28. Short-Circuit Current vs Temperature 100 120 140 10M 100M 1G EMIRR (dB) Frequency (Hz) C041 PRF = –10 dBm Figure 7-29. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency Frequency (Hz) Channel Seperation (dB) -140 -120 -100 -80 -60 -40 -20 100 1k 10k 100k 1M 10M C038 Figure 7-30. Channel Separation vs Frequency TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 0 10 20 30 40 50 60 70 80 90 100 Phase Margin (degrees) Capacitive Load (pF) C037 VS = 5.5 V Figure 7-31. Phase Margin vs Capacitive Load 120 160 200 Open Loop Voltage Gain (dB) Output Voltage (V) C023 A. VS = 5.5 V Figure 7-32. Open Loop Voltage Gain vs Output Voltage ±100 ±75 ±50 ±25 100 0 0.3 0.6 0.9 Output Voltage (mV) Settling time (µs) C032 Figure 7-33. Large Signal Settling Time (Positive) -150 -125 -100 -75 -50 -25 100 Output voltage (mV) Settling time (µs) C033 Figure 7-34. Large Signal Settling Time (Negative) www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TSV912A-Q1 TSV914A-Q1
8 Detailed Description
8.1 Overview
The TSV91xA-Q1 series is a family of low-power, rail-to-rail input and output op amps. These devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose automotive applications. The input common-mode voltage range includes both rails and allows the TSV91xA-Q1 series to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications and are designed for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TSV91xA-Q1 family extends 100 mV beyond the supply rails for the full supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region.
8.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TSV91xA-Q1 series delivers a robust output drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 k Ω, the output swings to within 15 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails.
8.3.3 Packages With an Exposed Thermal Pad
The TSV91xA-Q1 family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of the device is not assured when doing so.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TSV91xA-Q1 series is approximately 200 ns.
8.4 Device Functional Modes
The TSV91xA-Q1 family has a single functional mode. These devices are powered on as long as the power- www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TSV912A-Q1 TSV914A-Q1
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
The TSV91xA-Q1 series features 8-MHz bandwidth and 4.5-V/µs slew rate with only 550 µA of supply current per channel, providing good AC performance at low power consumption. DC applications are well served with a low input noise voltage of 18 nV / √ Hz at 1 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.
9.2 Typical Application
Figure 9-1 shows the TSV91xA-Q1 configured in a low-side, motor-control application. ZLOAD RSHUNT 0.1 VBUS 5 V RF 165 k RG 3.4 k VOUT ILOAD TSV91x VSHUNT Figure 9-1. TSV91xA-Q1 in a Low-Side, Motor-Control Application
9.2.1 Design Requirements
The design requirements for this design are:
- Load current: 0 A to 1 A
- Output voltage: 4.95 V
- Maximum shunt voltage: 100 mV TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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9.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is shown in Equation 1. OUT LOAD SHUNTV I R Gain u u (1) The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is defined using Equation 2. SHUNT MAX SHUNT LOAD MAX V 100mVR 100m I 1 A : (2) Using Equation 2 , R SHUNT is 100 m Ω. The voltage drop produced by I LOAD and R SHUNT is amplified by the TSV91xA-Q1 to produce an output voltage of approximately 0 V to 4.95 V. The gain required by the TSV91xA- Q1 to produce the necessary output voltage is calculated using Equation 3: _ _ _ _ OUT MAX OUT MIN IN MAX IN MIN V V Gain V V (3) Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors R F and RG. Equation 4 is used to size the resistors, RF and RG, to set the gain of the TSV91xA-Q1 to 49.5 V/V. F G RGain 1 R (4) Selecting R F as 165 k Ω and R G as 3.4 k Ω provides a combination that equals roughly 49.5 V/V. Figure 9-2 shows the measured transfer function of the circuit shown in Figure 9-1.
9.2.3 Application Curve
0 0.2 0.4 0.6 0.8 1 Output (V) ILOAD (A) C219 Figure 9-2. Low-Side, Current-Sense, Transfer Function www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TSV912A-Q1 TSV914A-Q1
10 Power Supply Recommendations
The TSV91xA-Q1 series is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications apply from –40°C to 125°C. Typical Characteristics presents parameters that can exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than 6 V can permanently damage the device; see the Absolute Maximum Ratings table. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, see Layout Example.
10.1 Input and ESD Protection
The TSV91xA-Q1 series incorporates internal ESD protection circuits on all pins. For input and output pins, this protection consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-mA, as stated in the Absolute Maximum Ratings table. Figure 10-1 shows how a series input resistor is added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications. 5 k/c87 10-mA maximum VIN VOUT IOVERLOAD Device Figure 10-1. Input Current Protection TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TSV912A-Q1 TSV914A-Q1
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
- Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
- To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
- Place the external components as close to the device as possible. As shown in Figure 11-2, keeping RF and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
- Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
- Cleaning the PCB following board assembly is recommended for best performance.
- Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
+VIN B VOUT BRG RF +VIN A VOUT ARG RF Figure 11-1. Schematic Representation of Layout Example OUT A -IN A +IN A OUT B -IN B +IN B VS± GND Ground (GND) plane on another layer Keep input traces short and run the input traces as far away from the supply lines as possible. Place components close to device and to each other to reduce parasitic errors. Use low-ESR, ceramic bypass capacitor. Place as close to the device as possible. VIN A GND RF RG VIN B GND RF RG VS+ GND OUT A OUT B Use low-ESR, ceramic bypass capacitor. Place as close to the device as possible. Figure 11-2. Layout Example www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TSV912A-Q1 TSV914A-Q1
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 12-1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TSV912A-Q1 Click here Click here Click here Click here Click here TSV914A-Q1 Click here Click here Click here Click here Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 www.ti.com
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TSV912A-Q1, TSV914A-Q1 SBOSA18B – JUNE 2020 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TSV912A-Q1 TSV914A-Q1
www.ti.com 2-Apr-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TSV912AQDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 29IT TSV912AQDRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TS912Q TSV914AQDRQ1 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TSV914AQD TSV914AQPWRQ1 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 T914AQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
www.ti.com 2-Apr-2021 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2021 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSV912AQDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0 TSV912AQDRQ1 SOIC D 8 2500 853.0 449.0 35.0 TSV914AQDRQ1 SOIC D 14 2500 853.0 449.0 35.0 TSV914AQPWRQ1 TSSOP PW 14 2000 853.0 449.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Apr-2021 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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