TSV912AIDGKT

TSV911 TI | Alldatasheet

Document overview

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Technical content

0.1 VBUS 5 V RF 165 k RG 3.4 k VOUT ILOAD TSV91x VSHUNT 0 50 100 150 200 250 300 Overshoot (%) Capacitive Load (pF) Overshoot+ Overshoot- C025 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 TSV91xRail-to-RailInput/Output,8-MHzOperationalAmplifiers

1 Features

1• Rail-to-rail input and output

• Low noise: 18 nV/√Hz at 1 kHz
• Low power consumption: 550 µA (typical)
• High-gain bandwidth: 8 MHz
• Operating supply voltage from 2.5 V to 5.5 V
• Low input bias current: 1 pA (typical)
• Low input offset voltage: 1.5 mV (maximum)
• Low offset voltage drift: ±0.5 µV/°C (typical)
• ESD internal protection: ±4-kV human-body model (HBM)
• Extended temperature range: –40°C to 125°C

2 Applications

• Battery-powered applications
• Motor control
• Power modules
• HVAC: heating, ventilating, and air conditioning
• Washing machines
• Refrigerators
• Medical instrumentation
• Active filters
• Sensor signal conditioning
• Audio receiver
• Automotive infotainment

3 Description

The TSV91x family, which includes single-, dual-, and quad-channel operational amplifiers (op amps), is specifically designed for general-purpose applications. Featuring rail-to-rail input and output (RRIO) swings, wide bandwidth (8 MHz), and low offset voltage (0.3 mV, typical), this family is designed for a variety of applications that require a good balance between speed and power consumption. The op amps are unity-gain stable and feature an ultra- low input bias current, which enables the family to be used in applications with high-source impedances. The low input bias current allows the devices to be used for sensor interfaces, battery-supplied and portable applications, and active filtering. The robust design of the TSV91x provides ease-of- use to the circuit designer. Features include a unity- gain stable, integrated RFI-EMI rejection filter, no phase reversal in overdrive condition, and high electrostatic discharge (ESD) protection (4-kV HBV). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TSV911 SOT-23 (5) 1.60 mm × 2.90 mm SC70 (5) 1.25 mm × 2.00 mm TSV912 SOIC (8) 3.91 mm × 4.90 mm WSON (8) 2.00 mm × 2.00 mm SOT-23 (8) 1.60 mm × 2.90 mm TSV914 SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 4.40 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Low-Side Motor Control Small-Signal Overshoot vs Load Capacitance

TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Table of Contents

7.7 Electrical Characteristics: VS (Total Supply Voltage) =

12.3 Receiving Notification of Documentation Updates 24

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision C (January 2019) to Revision D Page Changes from Revision B (April 2018) to Revision C Page Changes from Revision A (October 2017) to Revision B Page

• Deleted package preview note from TSV912 DSG package pinout drawing in Pin Configuration and Functions section.... 6

TSV911, TSV912, TSV914 www.ti.com SBOS878D –JULY 2017–REVISED OCTOBER 2019 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated Changes from Original (July 2017) to Revision A Page

TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

5 Device Comparison Table

DEVICE NO. OF CHANNELS PACKAGE LEADS DBV DCK D DSG PW DDF TSV911 1 5 5 — — — — TSV912 2 — — 8 8 — 8 TSV914 4 — — 14 — 14 —

2V± 3IN± 4 OUT 5 V+ Not to scale /c45IN OUT V/c45 +IN TSV911, TSV912, TSV914 www.ti.com SBOS878D –JULY 2017–REVISED OCTOBER 2019 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated

6 Pin Configuration and Functions

Pin Functions: TSV911 PIN I/O DESCRIPTION NAME NO. DBV (SOT-23) DCK (SC70) –IN 4 3 I Inverting input +IN 3 1 I Noninverting input OUT 1 4 O Output V– 2 2 — Negative (lowest) supply or ground (for single-supply operation) V+ 5 5 — Positive (highest) supply

-IN A +IN A OUT B -IN B +IN B Exposed Thermal Die Pad on Underside(1) OUT□B /c45IN□B +IN□B OUT□A /c45IN□A +IN□A V/c45 TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated TSV912 D, DGK, DDF Packages 8-Pin SOIC, VSSOP Top View TSV912 DSG Package (1) 8-Pin WSON With Exposed Thermal Pad Top View (1) Connect exposed thermal pad to V–. See Packages with an Exposed Thermal Pad section for more information. Pin Functions: TSV912 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply

OUT□D /c45IN□D +IN□D V/c45 OUT□A /c45IN□A +IN□A +IN□C /c45IN□C OUT□C +IN□B /c45IN□B OUT□B A B D C TSV911, TSV912, TSV914 www.ti.com SBOS878D –JULY 2017–REVISED OCTOBER 2019 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated TSV914 D, PW Packages 14-Pin SOIC, TSSOP Top View Pin Functions: TSV914 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B –IN C 9 I Inverting input, channel C +IN C 10 I Noninverting input, channel C –IN D 13 I Inverting input, channel D +IN D 12 I Noninverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) supply or ground (for single-supply operation) V+ 4 — Positive (highest) supply

TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply rails to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1) MIN MAX UNIT Supply voltage 6 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 Current(2) –10 10 mA Output short-circuit(3) Continuous mA Specified, TA –40 125 °C Junction, TJ 150 °C Storage, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted) VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 2.5 5.5 V Specified temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information: TSV911

THERMAL METRIC(1) TSV911 UNITDBV (SOT-23) DCK (SC70)

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 221.7 263.3 °C/W RθJC(top) Junction-to-case(top) thermal resistance 144.7 75.5 °C/W RθJB Junction-to-board thermal resistance 49.7 51.0 °C/W ψJT Junction-to-top characterization parameter 26.1 1.0 °C/W ψJB Junction-to-board characterization parameter 49.0 50.3 °C/W

TSV911, TSV912, TSV914 www.ti.com SBOS878D –JULY 2017–REVISED OCTOBER 2019 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: TSV912

THERMAL METRIC(1) TSV912 UNITD (SOIC) DGK (VSSOP) DSG (WSON) DDF (SOT-23)

8 PINS 8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 157.6 201.2 94.4 184.4 °C/W RθJC(top) Junction-to-case(top) thermal resistance 104.6 85.7 116.5 112.8 °C/W RθJB Junction-to-board thermal resistance 99.7 122.9 61.3 99.9 °C/W ψJT Junction-to-top characterization parameter 55.6 21.2 13 18.7 °C/W ψJB Junction-to-board characterization parameter 99.2 121.4 61.7 99.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A 34.4 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Thermal Information: TSV914

THERMAL METRIC(1) TSV914 UNITD (SOIC) PW (TSSOP)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 106.9 205.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69 106.7 °C/W RθJB Junction-to-board thermal resistance 63 133.9 °C/W ψJT Junction-to-top characterization parameter 25.9 34.4 °C/W ψJB Junction-to-board characterization parameter 62.7 132.6 °C/W

TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated (1) Third-order filter; bandwidth = 80 kHz at –3 dB. 7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V ±0.3 ±1.5 mVVS = 5 V TA = –40°C to 125°C ±3 dVOS/dT Drift VS = 5 V TA = –40°C to 125°C ±0.5 µV/°C PSRR Power-supply rejection ratio VS = 2.5 V – 5.5 V, VCM = (V–) ±7 µV/V Channel separation, DC At DC 100 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range VS = 2.5 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V CMRR Common-mode rejection ratio VS = 5.5 V TA = –40°C to 125°C 80 103 dB VS = 5.5 V, VCM = –0.1 V to 5.6 V TA = –40°C to 125°C 57 87 TA = –40°C to 125°C 88 VS = 2.5 V, VCM = –0.1 V to 1.9 V TA = –40°C to 125°C 81 INPUT BIAS CURRENT IB Input bias current ±1 pA IOS Input offset current ±0.05 pA NOISE En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP en Input voltage noise density VS = 5 V, f = 10 kHz 12 nV/√Hz VS = 5 V, f = 1 kHz 18 in Input current noise density f = 1 kHz 10 fA/√Hz INPUT CAPACITANCE CID Differential 2 pF CIC Common-mode 4 pF OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10 kΩ 100 dB RL = 10 kΩ 104 130 RL = 2 kΩ 100 RL = 2 kΩ 130 FREQUENCY RESPONSE GBP Gain bandwidth product VS = 5 V, G = 1 8 MHz φm Phase margin VS = 5 V, G = 1 55 ° SR Slew rate VS = 5 V, G = 1 RL = 2 kΩ CL = 100 pF

4.5 V/µs

To 0.1%, VS = 5 V, 2-V step , G = 1 CL = 100 pF 0.5 µs To 0.01%, VS = 5 V, 2-V step , G = 1 CL = 100 pF 1 tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.2 µs THD + N Total harmonic distortion + noise(1) VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz 0.0008% OUTPUT VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 15 mV VS = 5.5 V, RL = 2 kΩ 50

TSV911, TSV912, TSV914 www.ti.com SBOS878D –JULY 2017–REVISED OCTOBER 2019 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V (continued) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISC Short-circuit current VS = 5 V ±50 mA ZO Open-loop output impedance VS = 5 V, f = 10 MHz 100 Ω POWER SUPPLY IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 mA 550 750 µA VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C 1100

7.8 Typical Characteristics

Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage Figure 5. Offset Voltage vs Power Supply Figure 6. Open-Loop Gain and Phase vs Frequency

VIN+ V INÛ VÛ (Ground) VBIAS2 VBIAS1 Class AB Control Circuitry VO TSV911, TSV912, TSV914 SBOS878D –JULY 2017–REVISED OCTOBER 2019 www.ti.com Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TSV91x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TSV91x series to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications and are designed for driving sampling analog-to-digital converters (ADCs).

8.2 Functional Block Diagram

TSV911, TSV912, TSV914 www.ti.com SBOS878D –JULY 2017–REVISED OCTOBER 2019 Product Folder Links: TSV911 TSV912 TSV914 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Rail-to-Rail Input

The input common-mode voltage range of the TSV91x family extends 100 mV beyond the supply rails for the full supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a complementary input stage: an N- channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region.

8.3.2 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the TSV91x series delivers a robust output drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails.

8.3.3 Packages with an Exposed Thermal Pad

The TSV91x family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of the device is not assured when doing so.

8.3.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TSV91x series is approximately 200 ns.

8.4 Device Functional Modes

The TSV91x family has a single functional mode. These devices are powered on as long as the power-supply

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

input noise voltage of 18 nV / √Hz at 1 kHz, low input bias current, and a typical input offset voltage of 0.3 mV.

9.2 Typical Application

Figure 35 shows the TSV91x configured in a low-side, motor-control application. Figure 35. TSV91x in a Low-Side, Motor-Control Application

9.2.1 Design Requirements

• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV

9.2.2 Detailed Design Procedure

The transfer function of the circuit in Figure 35 is shown in Equation 1. Using Equation 3, the required gain is calculated to be 49.5 V/V, which is set with resistors RF and RG. Equation 4 is used to size the resistors, RF and RG, to set the gain of the TSV91x to 49.5 V/V. the measured transfer function of the circuit shown in Figure 35.

9.2.3 Application Curve

Figure 36. Low-Side, Current-Sense, Transfer Function

10 Power Supply Recommendations

variance with regard to operating voltage or temperature.

10.1 Input and ESD Protection

must be kept to a minimum in noise-sensitive applications. Figure 37. Input Current Protection

11 Layout

11.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 39, keeping RF and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

Figure 38. Schematic Representation for Figure 39 Figure 39. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

resources, tools and software, and quick access to order now. Table 1. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

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www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TSV911AIDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1U2F TSV911AIDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1U2F TSV911AIDBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1U2F TSV911AIDBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1U2F TSV911AIDCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1EK TSV911AIDCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 1EK TSV912AIDDFR Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T12A TSV912AIDDFR.A Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T12A TSV912AIDDFRG4 Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T12A TSV912AIDDFRG4.A Active Production SOT-23-THIN (DDF) | 83000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T12A TSV912AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T912 TSV912AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T912 TSV912AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T912 TSV912AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 T912 TSV912AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TSV912 TSV912AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TSV912 TSV912AIDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TSV912 TSV912AIDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TSV912 TSV912AIDSGR Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T912 TSV912AIDSGR.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T912 TSV912AIDSGT Active Production WSON (DSG) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T912 TSV912AIDSGT.A Active Production WSON (DSG) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 T912 TSV912AIPWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TSV912 TSV912AIPWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 TSV912 TSV914AIDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TSV914AD TSV914AIDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TSV914AD TSV914AIDRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TSV914AD TSV914AIDRG4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TSV914AD Addendum-Page 1

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TSV914AIPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TSV914 TSV914AIPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 TSV914 TSV914AIPWT Active Production TSSOP (PW) | 14 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TSV914 TSV914AIPWT.A Active Production TSSOP (PW) | 14 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 125 TSV914 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TSV912AIDDFR SOT-23- THIN TSV912AIDDFRG4 SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2025 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSV911AIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TSV911AIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TSV911AIDBVRG4 SOT-23 DBV 5 3000 210.0 185.0 35.0 TSV911AIDCKR SC70 DCK 5 3000 210.0 185.0 35.0 TSV912AIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TSV912AIDDFRG4 SOT-23-THIN DDF 8 3000 210.0 185.0 35.0 TSV912AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 TSV912AIDGKT VSSOP DGK 8 250 353.0 353.0 32.0 TSV912AIDR SOIC D 8 2500 353.0 353.0 32.0 TSV912AIDRG4 SOIC D 8 2500 353.0 353.0 32.0 TSV912AIDSGR WSON DSG 8 3000 210.0 185.0 35.0 TSV912AIDSGT WSON DSG 8 250 210.0 185.0 35.0 TSV912AIPWR TSSOP PW 8 2000 353.0 353.0 32.0 TSV914AIDR SOIC D 14 2500 353.0 353.0 32.0 TSV914AIDRG4 SOIC D 14 2500 353.0 353.0 32.0 TSV914AIPWR TSSOP PW 14 2000 353.0 353.0 32.0 TSV914AIPWT TSSOP PW 14 250 353.0 353.0 32.0 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4) 14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C 0.22 0.15 2.4 1.8 2X 0.65 1.3 0.1

0.0 TYP

5X 0.33 0.15 NOTE 5

0.1 C A B

0.46

0.26 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT 5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/G 11/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 4X 0 -15 4X 4 -15 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT (2.6) ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/E 07/2024 SOT-23-THIN - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WSON - 0.8 mm max heightDSG 8 PLASTIC SMALL OUTLINE - NO LEAD2 x 2, 0.5 mm pitch 4224783/A

www.ti.com PACKAGE OUTLINE C 8X 0.32 0.18 1.6 0.1 1.5 0.9 0.1 6X 0.5 8X 0.4 0.2 0.05 0.00 0.8 0.7 A 2.1 1.9 B 2.1 1.9 0.32 0.18 0.4 0.2 (DIM A) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 X 0.25)(45 PIN 1 ID 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500 ALTERNATIVE TERMINAL SHAPE TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT 8X (0.25) (1.6) (1.9) 6X (0.5) (0.9) ( 0.2) VIA TYP (0.55) 8X (0.5) (R0.05) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 SYMM 4 5 LAND PATTERN EXAMPLE SCALE:20X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.25) 8X (0.5) (0.9) (0.7) (1.9) (0.45) 6X (0.5) WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM METAL SYMM

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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