TSV792 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 36
Technical content
Datasheet sections
- 1 Pin description
- 1.1 TSV791 single operational amplifier
- 1.2 TSV792 dual operational amplifier
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Typical performance characteristics
- 5 Application information
- 5.1 Operating voltages
- 5.2 Input offset voltage drift over the temperature
- 5.3 Long term input offset voltage drift
- 5.4 Unused channel
- 5.5 EMI rejection
- 5.6 Maximum power dissipation
- 5.7 Capacitive load and stability
- 5.8 Resistor values for high speed op-amp design
- 5.9 Settling time
- 5.10 PCB layout recommendations
- 5.11 Decoupling capacitor
- 5.12 Macro model
- 6 Typical applications
- 6.1 Low-side current sensing
- 6.2 Photodiode transimpedance amplification
- 7 Package information
- 7.1 DFN8 2x2 mm package information
- 7.2 DFN8 2x2 package information
- 7.3 MiniSO8 package information
- 7.4 SO-8 package information
- 8 Ordering information
Features
- Gain bandwidth product 50 MHz, unity gain stable
- Slew rate 30 V/µs
- Low input offset voltage 50 µV typ., 200 µV max.
- Low input bias current: 2 pA typ.
- Low input voltage noise density 6.5 nV/√Hz @ 10 kHz
- Wide supply voltage range: 2.2 V to 5.5 V
- Rail-to-rail input and output
- Extended temperature range: - 40 °C to +125 °C
- Automotive grade version available
- Benefits: – Accuracy of measurement virtually unaffected by noise or input bias current – Signal conditioning for high frequencies
Applications
- High bandwidth low-side and high-side current sensing
- Photodiode transimpedance amplification
- A/D converters input buffers
- Power management in solar-powered systems
- Power management in automotive applications
Description
The TSV791 and TSV792 are single and dual 50 MHz-bandwidth unity-gain-stable amplifiers. The rail-to-rail input stage and the slew rate of 30 V/µs make the TSV791 and TSV792 ideal for low-side current measurement. The excellent accuracy provided by maximum input voltage of 200 µV allows amplifying accurately small- amplitude input signal. The TSV792 can operate from a 2.2 V to 5.5 V single supply; it can typically handle an output capacitor up to 1 nF and is fully specified on a load of 22 pF, therefore allowing easy usage as A/D converters input buffer. Maturity status link TSV791, TSV792
Related products
Zero drift amplifiers with more power savings (3 MHz) TSB712 36 V high-bandwidth amplifiers (6 MHz) TSB7192 36 V high-bandwidth amplifiers (20 MHz) High bandwidth (50 MHz) low offset (200 µV) rail-to-rail 5 V op-amp TSV791, TSV792 Datasheet DS13480 - Rev 1 - November 2020 For further information contact your local STMicroelectronics sales office.
1 Pin description
1.1 TSV791 single operational amplifier
Figure 1. Pin connections (top view) Table 1. Pin description
1 OUT Output channel
2 VCC- Negative supply voltage
3 IN+ Non-inverting input channel
4 IN- Inverting input channel
5 VCC+ Positive supply voltage
1.2 TSV792 dual operational amplifier
Figure 2. Pin connections (top view)
- The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
Table 2. Pin description
1 OUT1 Output channel 1
2 IN1- Inverting input channel 1
3 IN1+ Non-inverting input channel 1
4 VCC- Negative supply voltage
5 IN2+ Non-inverting input channel 2
6 IN2- Inverting input channel 2
7 OUT2 Output channel 2
8 VCC+ Positive supply voltage
2 Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
- All voltage values are with respect to the VCC- pin, unless otherwise specified.
- The maximum input voltage differential value may be extended to the condition that the input current is limited to ±10 mA.
- R th-ja is a typical value, obtained with PCB according to JEDEC 2s2p without vias.
- R th-jc is a typical value, obtained with PCB according to JEDEC 1s0p without vias.
- Human body model: HBM test according to the standard ESDA-JS-001-2017.
- Human body model: HBM test according to the standard AEC-Q100-002.
- Charged device model: the CDM test is done according to the standard AEC-Q100-011.
Table 4. Operating conditions
3 Electrical characteristics
Table 5. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, T = 25 °C, RL = 10 kΩ connected to VCC / 2 and CL = 22 pF (unless otherwise specified).
Electrical characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit IOUT ISINK OUT connected to VCC+, mA ISOURCE OUT connected to VCC-, T = 25°C 50 60 OUT connected to VCC-, ICC Supply current (by operational amplifier) T = 25 °C 5.5 6 mA -40 °C ≤ T ≤ 125 °C 6 AC performance GBP Gain bandwidth product RL = 10 kΩ, CL = 22 pF 35 50 MHz SR Slew rate RL = 10 kΩ, CL = 22 pF, AV = 1 V/V, 10 % to 90 %
30 V/µs
VOUT = 4 Vpp, RL = 10 kΩ, AV = +101, f = 1 kHz 126 dB Φm Phase margin RL = 10 kΩ 53 degrees en Input voltage noise density f = 10 Hz 140 nV/√Hzf = 100 Hz 43 f = 10 kHz 6.5 en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 9 µVpp Cin Input capacitance Differential 6.3 pF Common mode 1.6 1. See Section 5.2 Input offset voltage drift overtemperature. 2. See Section 5.3 Long term input offset voltage drift. 3. Guaranteed by characterization. TSV791, TSV792
Table 6. Electrical characteristics at VCC = 3.3 V, VICM = VOUT = VCC / 2, T = 25 °C, RL = 10 kΩ connected to VCC / 2 and CL = 22 pF (unless otherwise specified).
Symbol Parameter Conditions Min. Typ. Max. Unit 10 % to 90 % CR Cross talk VOUT = 4 Vpp, RL = 10 kΩ, AV = +101, f = 1 kHz 126 dB Φm Phase margin RL = 10 kΩ 53 degrees en Input voltage noise density f = 10 Hz 140 nV/√Hzf = 100 Hz 43 f = 10 kHz 6.5 Cin Input capacitance Differential 6.3 pF Common mode 1.6 1. See Section 5.2 Input offset voltage drift overtemperature. 2. Guaranteed by characterization. TSV791, TSV792
Table 7. Electrical characteristics at VCC = 2.2 V, VICM = VOUT = VCC / 2, T = 25 °C, RL = 10 kΩ connected to VCC / 2 and CL = 22 pF (unless otherwise specified).
Symbol Parameter Conditions Min. Typ. Max. Unit Φm Phase margin RL = 10 kΩ 69 degrees en Input voltage noise density f = 10 Hz 250 nV/√Hzf = 100 Hz 94 f = 10 kHz 15 Cin Input capacitance Differential 6.3 pF Common mode 1.6 1. See Section 5.2 Input offset voltage drift overtemperature. 2. Guaranteed by characterization. TSV791, TSV792 DS13480 - Rev 1 page 10/36
4 Typical performance characteristics
RL = 10 kΩ connected to VCC / 2 and CL = 22 pF, unless otherwise specified. Figure 3. Supply current vs. supply voltage Figure 4. Input offset voltage distribution at Figure 5. Input offset voltage distribution at Figure 6. Input offset voltage vs. temperature at
Figure 43. PSRR vs. frequency at VCC = 5 V Figure 44. Crosstalk vs. frequency at VCC = 5 V
5 Application information
5.1 Operating voltages
power supplies. However, the parameters are very stable over the full VCC range and several characterization curves show the TSV79x device characteristics over the full operating range. Additionally, the main specifications are guaranteed in extended temperature range from - 40 to 125 °C. The TSV79X devices are rail-to-rail input and output, and feature two input transistor pairs, allowing the op-amp to operate over all the common mode range, from Vcc- - 0.1 V, to Vcc+ + 0.1 V. The input pair transition typically occurs at Vcc+ - 1.4 V, as seen in figures 11 and 12. The precision and dynamic performances are particularly optimized on the low pair, from Vcc- - 0.1 V to Vcc+ - 2 V, and operating in this Vicm range is advised for best performance whenever possible. Also, operating near the pair transition should be avoided when precision is a concern, as CMRR can be lower in these conditions.
5.2 Input offset voltage drift overtemperature
The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset (Vio) is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift overtemperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift overtemperature is computed using Equation 1. ∆ V i o ∆ T = max V i o T − V i o 25 ° C T − 25° C T = − 40 ° C an d T = 125 ° C (1) The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk (process capability index) greater than 1.3.
5.3 Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
- Voltage acceleration, by changing the applied voltage
- Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2 A F V = e β . V S − V U (2) Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. A F T = e E a k . 1 T U − 1 T S (3) Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV . K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) TSV791, TSV792
Application information
DS13480 - Rev 1 page 19/36
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). A F = A F T . A F V (4) AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation x to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. Months = AF × 1000 h × 12 months / (24 h × 365.25 days) To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 5). V C C = m ax V o p wi t ℎ V i c m = V c c 2 (5) The long term drift parameter ΔVio (in µV.month-1/2), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 6). ∆ V i o = V i o d ri f t m on t ℎ s (6) Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration. The Vio final drift, in µV, to be measured on the device in real operation conditions can be computed from Equation 7. V i o f i na l dr i f t t o p , T op , V C C = ∆ V i o . t o p . e β . V C C − V C C n om . e E a k . 1 297 − 1 T op (7) Where: ΔVio is the long term drift parameter in µV.√month top is the operating time seen by the device, in months Top is the operating temperature VCC is the power supply during operating time VCC nom is the nominal VCC at which the ΔVio is computed (5 V for TSV79x) Ea is the activation energy of the technology (here 0.7 eV).
5.4 Unused channel
When one of the two channels of the TSV792 is not used, it must be properly connected in order to avoid internal oscillations that can negatively impact the signal integrity on the other channel, as well as the current consumption. Two different configurations can be used: Gain configuration: the channel can be set in gain, the input can be set to any voltage within the Vicm operating range. Comparator configuration: the channel can be set to a comparator configuration (without negative feedback). In this case, positive and negative inputs can be set to any value provided these values are significantly different (100 mV or more, to avoid oscillation between positive and negative state).
5.5 EMI rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op-amps is a change in the offset voltage as a result of RF signal rectification. EMIRR is defined in Equation 8: E MIR R = 20 . l o g V i n pp ∆ V i o (8) TSV791, TSV792 Unused channel DS13480 - Rev 1 page 20/36
seen in Figure 45, EMI rejection ratio has been measured on both inputs and output, from 400 MHz to 2.4 GHz. Figure 45. EMIRR on IN+ and IN- pins supply and output pins. These capacitances help to minimize the impedance of these nodes at high frequencies.
5.6 Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package. θJA is the junction to ambient thermal resistance of the package. TA is the ambient temperature. P D = V C C × I C C + V C C + − V O U T × I Lo ad when the op-amp is sourcing the current. P D = V C C × I C C + V OU T − V C C − × I Lo ad when the op-amp is sinking the current. can cause degradation in the parametric performance or even destroy the device.
5.7 Capacitive load and stability
values produces gain peaking in the frequency response, with overshoot and ringing in the step response.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads. Figure 46. Test configuration for RISO Please note that RISO = 22 Ω is sufficient to make the TSV79x stable whatever the capacitive load.
5.8 Resistor values for high speed op-amp design
mitigated by lowering the resistive impedances. the feedback. In these cases, it is advised to use a low value feedback resistor (Rf), typically 600 Ω. Figure 47. Inverting amplifier configuration with parasitic input capacitances
currents are very low. Furthermore, this resistor can also interact with the input capacitances to generate a pole. The frequency of this pole should be kept higher than the closed-loop bandwidth frequency. evaluation of the application circuit.
5.9 Settling time
output stays within the given range around the final value. Figure 48. Settling time measurement configuration estimation, but prototyping can be needed for fine circuit optimization.
5.10 PCB layout recommendations
connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
5.11 Decoupling capacitor
In order to ensure op-amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as close as possible to the op-amp supply pins. A good decoupling helps to reduce electromagnetic interference impact.
5.12 Macro model
Accurate macro models of the TSV79x device are available on the STMicroelectronics’ website at: www.st.com. These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSV79x operational amplifier. They emulate the nominal performance of a typical device at 25 °C within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the right operational amplifier, but they do not replace onboard measurements. TSV791, TSV792 Decoupling capacitor DS13480 - Rev 1 page 24/36
6 Typical applications
6.1 Low-side current sensing
circuit ground. The resulting voltage drop is amplified using the TSV79x (see Figure 48). Figure 49. Low-side current sensing schematic
6.2 Photodiode transimpedance amplification
Figure 50. Photodiode transimpedance amplifier circuit The feedback resistance is usually in the MΩ range, in order to get a large enough voltage output range. For more details on tuning this circuit, please read the application note AN4451.
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. TSV791, TSV792
Package information
DS13480 - Rev 1 page 27/36
7.1 SOT23-5 package information
Figure 51. SOT23-5 package outline Table 8. SOT23-5 package mechanical data
7.2 DFN8 2x2 package information
Figure 52. DFN8 2x2 package outline Table 9. DFN8 2x2 package mechanical data
Figure 53. DFN8 2x2 recommended footprint Note: The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
7.3 MiniSO8 package information
Figure 54. MiniSO8 package outline Table 10. MiniSO8 package mechanical data
7.4 SO-8 package information
Figure 55. SO-8 package outline Table 11. SO-8 mechanical data
8 Ordering information
Table 12. Order code
- Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 & Q 002 or equivalent are on-going.
Ordering information
DS13480 - Rev 1 page 33/36
Revision history
Table 13. Document revision history 09-Nov-2020 1 Initial release.