TSV7721 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 40
Technical content
Datasheet sections
- 1 Pin description
- 1.1 TSV7721 single operational amplifier
- 1.2 TSV7722 dual operational amplifier
- 1.3 TSV7723 dual operational amplifier with shutdown option
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Typical performance characteristics
- 5 Application information
- 5.1 Operating voltages
- 5.2 Input offset voltage drift over the temperature
- 5.3 Unused channel
- 5.4 EMI rejection
- 5.5 Maximum power dissipation
- 5.6 Capacitive load and stability
- 5.7 Resistor values for high speed op amp design
- 5.8 Settling time
- 5.9 Shutdown function (TSV7723)
- 5.10 PCB layout recommendations
- 5.11 Decoupling capacitor
- 5.12 Macro model
- 6 Typical applications
- 6.1 Low-side current sensing
- 6.2 Photodiode transimpedance amplification
- 7 Package information
- 7.1 DFN8 2x2 mm package information
- 7.2 DFN8 2x2 package information
- 7.3 MiniSO8 package information
- 7.4 SO-8 package information
- 7.5 MiniSO10 package information
Datasheet sections
- 8 Ordering information
Features
- Gain bandwidth product 22 MHz, unity gain stable
- High accuracy input offset voltage: 50 µV typ., 200 µV max.
- Low input bias current: 2 pA typ.
- Low input voltage noise density: 7 nV/√Hz
- Wide supply voltage range: 1.8 V to 5.5 V
- Output rail-to-rail
- Input common-mode range includes low rail
- Automotive grade and shutdown versions available
- Benefits: – High frequency signal conditioning – Optimized accuracy for low-side current sensing
Applications
- Low-side current measurement
- Photodiode amplifiers
- Automotive current measurement and sensor signal conditioning
- Strain gauges signal conditioning
Description
The TSV7721, TSV7722 and TSV7723 are single and dual 22 MHz-bandwidth unity- gain-stable amplifiers. The input offset voltage of 200 µV max. (50 µV typ.) at room temperature, optimized for common-mode close to ground makes the TSV772x ideal for low-side current measurements. The TSV772x can operate from 1.8 V to 5.5 V single supply and it is fully specified on a load of 47 pF, therefore allowing easy usage as A/D converters input buffer. The TSV772x series offers rail-to-rail output, excellent speed/power consumption ratio, and 22 MHz gain bandwidth product, while consuming just 1.7 mA at 5 V. The devices also feature an ultra-low input bias current that enables connection to photodiodes and other sensors where current is the key value to be measured. These features make the TSV772x series ideal for high-accuracy, high-bandwidth sensor interfaces. Maturity status link Channel Automotive Package TSV7721
1 SOT23-5
1 • SOT23-5 TSV7722
2 DFN8
2 MiniSO8
2 SO8
2 • MiniSO8 2 • SO8 TSV7723 2 MiniSO10
Related products
TSV792 Rail-to-rail amplifier with higher GBW 50 MHz TSB7192 22 MHz amplifier with 36 V supply voltage High bandwidth (22 MHz) low offset (200 μV) 5 V op amp TSV7721, TSV7722, TSV7723 Datasheet DS13614 - Rev 3 - May 2021 For further information contact your local STMicroelectronics sales office.
1 Pin description
1.1 TSV7721 single operational amplifier
Figure 1. Pin connections (top view) Table 1. Pin description
1 OUT Output channel
2 VCC- Negative supply voltage
3 IN+ Non-inverting input channel
4 IN- Inverting input channel
5 VCC+ Positive supply voltage
1.2 TSV7722 dual operational amplifier
Figure 2. Pin connections (top view)
- The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
Table 2. Pin description
1 OUT1 Output channel 1
2 IN1- Inverting input channel 1
3 IN1+ Non-inverting input channel 1
4 VCC- Negative supply voltage
5 IN2+ Non-inverting input channel 2
6 IN2- Inverting input channel 2
7 OUT2 Output channel 2
8 VCC+ Positive supply voltage
1.3 TSV7723 dual operational amplifier with shutdown option
Figure 3. Pin connections (top view) Table 3. Pin description
5 EN1
6 EN2
7 IN2+ Non-inverting input channel 2
8 IN2- Inverting input channel 2
9 OUT2 Output channel 2
10 VCC+ Positive supply voltage
2 Absolute maximum ratings and operating conditions
Table 4. Absolute maximum ratings
- All voltage values, except differential voltage, are with respect to VCC- pin.
- The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
- Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V.
- Input current must be limited by a resistor in series with the inputs.
- Human body model: the test HBM is done in accordance with the standards ESDA-JS-001-2017 and Q100-002
- Charged device model: the test CDM is done in accordance with the standards ESDA-JS-002-2018 and Q100-011
Table 5. Operating conditions
3 Electrical characteristics
Table 6. Electrical characteristics at VCC+ = 5 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to VCC /
Electrical characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit trec Overload recovery time: trec is defined as delay between input voltage edge and VOUT reaching 100 mV from initial value 70 ns ts Settling time To 0.1%, Vin = 1 Vp-p 270 ns en Equivalent input noise voltage f = 1 kHz 13 nV/√Hz f = 10 kHz 7 CS Channel separation (for TSV7722 and TSV7723) f = 1 kHz 120 dB Cin Input capacitance Differential 6 pF Common-mode 4.5 Shutdown feature characteristics (TSV7723 only, op-amp in shutdown mode when EN input is low) ICC Supply current per channel in shutdown mode VOUT = VCC / 2, RL > 1 MΩ, EN = VCC- T = 25°C 2.5 50 nA -40°C < T < 85°C 450 -40°C < T < 125°C 4 µA ton Amplifier turn-on time (other channel already on) VOUT = VCC- to VCC- + 0.2 V 2 µs tinit Initialization time (both channels off) VOUT to 200 mV of final value 7 µs VIH EN logic high 2 V VIL EN logic low 0.8 IIH EN current high EN = VCC+ 1 pA IIL EN current low EN = VCC- 1 IOleak Output leakage in shutdown mode, EN = VCC- T = 25°C 50 pA -40°C < T < 125°C 15 nA 1. Slew rate value is calculated as the average between positive and negative slew rates. TSV7721, TSV7722, TSV7723
Table 7. Electrical characteristics at VCC+ = 3.3 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to
Symbol Parameter Conditions Min. Typ. Max. Unit ICC VOUT = VCC / 2, RL > 1 MΩ, EN = VCC- -40°C < T < 85°C nA450 -40°C < T < 125°C 4 µA ton Amplifier turn-on time (other channel already on) VOUT = VCC- to VCC- + 0.2 V 2 µs tinit Initialization time (both channels off) VOUT to 200 mV of final value 11 µs VIH EN logic high 2 V VIL EN logic low 0.8 IIH EN current high EN = VCC+ 1 pA IIL EN current low EN = VCC- 1 IOleak Output leakage in shutdown mode, EN = VCC- T = 25°C 50 pA -40°C < T < 125°C 15 nA 1. Slew rate value is calculated as the average between positive and negative slew rates. TSV7721, TSV7722, TSV7723
Table 8. Electrical characteristics at VCC+ = 1.8 V, with VCC- = 0 V, Vicm = 0.7 V, T = 25°C, and OUT pin connected to VCC / DS13614 - Rev 3 page 10/40
Symbol Parameter Conditions Min. Typ. Max. Unit ICC EN = VCC- -40°C < T < 125°C 4 µA ton Amplifier turn-on time (other channel already on) VOUT = VCC - to VCC - + 0.2 V 1.5 µs tinit Initialization time (both channels off) VOUT to 200 mV of final value 38 µs VIH EN logic high 1.2 V VIL EN logic low 0.6 IIH EN current high EN = VCC+ 1 pA IIL EN current low EN = VCC- 1 IOleak Output leakage in shutdown mode, EN = VCC- T = 25°C 50 pA -40°C < T < 125°C 15 nA 1. Slew rate value is calculated as the average between positive and negative slew rates. TSV7721, TSV7722, TSV7723 DS13614 - Rev 3 page 11/40
4 Typical performance characteristics
RL = 10 kΩ connected to VCC / 2 and CL = 47 pF, unless otherwise specified. Figure 4. Supply current vs. supply voltage Figure 5. Input offset voltage distribution at VCC = 5 V Figure 6. Input offset voltage distribution at VCC = 1.8 V Figure 7. Input offset voltage vs. temperature at VCC = 5 V Figure 8. Input offset voltage vs. temperature at VCC=1.8 V Figure 9. Input offset voltage thermal coeff. at VCC=5 V
5 Application information
5.1 Operating voltages
and 5 V power supplies. However, the parameters are very stable over the full VCC range and several characterization curves show the TSV7722 device characteristics over the full operating range. Additionally, the main specifications are guaranteed in extended temperature range from - 40 to 125 °C. The TSV7722 device is low rail input, and rail-to-rail output. The common-mode operating range is from Vcc- - 0.1 V, to Vcc+ - 1.1 V. The op amp Vio is trimmed at Vcc = 3.3 V, Vicm = 0 V, and thus the DC precision is optimized for operation with Vicm close to Vcc-.
5.2 Input offset voltage drift over the temperature
The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift overtemperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift overtemperature is computed using the following equation: ∆ V i o ∆ T = max V i o T − V i o 25 ° C T − 25° C (1) Where T = - 40 °C and 125 °C. The TSV7721, TSV7722, TSV7723 datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3.
5.3 Unused channel
When one of the two channels of the TSV7722 is not used, it must be properly connected in order to avoid internal oscillations that can negatively impact the signal integrity on the other channel, as well as the current consumption. Two different configurations can be used: Gain configuration: the channel can be set in gain, the input can be set to any voltage within the Vicm operating range. Comparator configuration: the channel can be set to a comparator configuration (without negative feedback). In this case, positive and negative inputs can be set to any value provided these values are significantly different (100 mV or more, to avoid oscillation between positive and negative state).
5.4 EMI rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. EMIRR is defined in Eq. (2): E MIR R = 20 . l o g V i n pp ∆ V i o (2) The TSV7722 has been specially designed to minimize susceptibility to EMIRR and shows a low sensitivity. As can be seen in Figure 46. EMIRR on In+, In- and Out pins, EMI rejection ratio has been measured on both inputs and output, from 400 MHz to 2.4 GHz. TSV7721, TSV7722, TSV7723
Application information
DS13614 - Rev 3 page 19/40
Figure 46. EMIRR on In+, In- and Out pins These capacitances help to minimize the impedance of these nodes at high frequencies.
5.5 Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package. θJA is the junction to ambient thermal resistance of the package. TA is the ambient temperature. P D = V C C × I C C + V C C + − V O U T × I Lo ad when the op amp is sourcing the current. P D = V C C × I C C + V OU T − V C C − × I Lo ad when the op amp is sinking the current. can cause degradation in the parametric performance or even destroy the device.
5.6 Capacitive load and stability
values produces gain peaking in the frequency response, with overshoot and ringing in the step response. Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
Figure 47. Test configuration for RISO Please note that RISO = 22 Ω is sufficient to make the TSV7722 stable whatever the capacitive load.
5.7 Resistor values for high speed op amp design
Due to its high gain bandwidth product (GBP), this op amp is particularly sensitive to parasitic impedances. value feedback resistor (Rf), typically 1 kΩ. Figure 48. Inverting amplifier configuration with parasitic input capacitances a hardware evaluation of the application circuit.
5.8 Settling time
inverting configuration, using the so-called “false summing node” circuit. Figure 49. Settling time measurement configuration good estimation, but prototyping can be needed for fine circuit optimization.
5.9 Shutdown function (TSV7723)
must never be left floating, but must be tied to VCC+ or VCC-. Figure 50. Test configuration
5.10 PCB layout recommendations
connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
5.11 Decoupling capacitor
5.12 Macro model
Accurate macro models of the TSV7722 device are available on the STMicroelectronics’ website at: www.st.com. right operational amplifier, but they do not replace on-board measurements.
6 Typical applications
6.1 Low-side current sensing
Figure 51. Low-side current sensing schematic chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. degradation due to the CMRR.
6.2 Photodiode transimpedance amplification
Figure 52. Photodiode transimpedance amplifier circuit The feedback resistance is usually in the MΩ range, in order to get a large enough voltage output range. For more details on tuning this circuit, please read the application note AN4451.
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. TSV7721, TSV7722, TSV7723
Package information
DS13614 - Rev 3 page 26/40
7.1 SOT23-5 package information
Figure 53. SOT23-5 package outline Table 9. SOT23-5 package mechanical data
7.2 DFN8 2x2 package information
Figure 54. DFN8 2x2 package outline Table 10. DFN8 2x2 package mechanical data
Figure 55. DFN8 2x2 recommended footprint Note: The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.
7.3 MiniSO8 package information
Figure 56. MiniSO8 package outline Table 11. MiniSO8 package mechanical data
7.4 SO-8 package information
Figure 57. SO-8 package outline Table 12. SO-8 mechanical data
7.5 MiniSO10 package information
Figure 58. MiniSO10 package outlineaaa Table 13. MiniSO10 mechanical data
8 Ordering information
Table 14. Order code
- Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 & Q 002 or equivalent are ongoing.
Ordering information
DS13614 - Rev 3 page 33/40
Revision history
Table 15. Document revision history 20-Jan-2021 1 Initial release. Updated the "Related products" table in cover page. Added: Figure 43, Figure 44, Figure 45 and Section 5.9 .
Table 6. Electrical characteristics at VCC+ = 5 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to VCC / 2 Table 7. Electrical characteristics at VCC+ = 3.3 V, with VCC- = 0 V, Vicm = VCC / 2, T = 25°C, and OUT pin connected to VCC / Table 8. Electrical characteristics at VCC+ = 1.8 V, with VCC- = 0 V, Vicm = 0.7 V, T = 25°C, and OUT pin connected to VCC / 2