High accuracy (200 V) micropower 14 A, 150 kHz 5 V CMOS operational amplifiers
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 29
Technical content
Datasheet sections
- 1 Pin connections
- 2 Absolute maximum ratings and operating conditions
- 3 Electrical characteristics
- 4 Application information
- 4.1 Operating voltages
- 4.2 Rail-to-rail input
- 4.3 Rail-to-rail output
- 4.4 Input offset voltage drift over temperature
- 4.5 Long-term input offset voltage drift
- 4.6 Initialization time
- 4.7 PCB layouts
- 4.8 Macromodel
- 5 Package information
- 5.1 SC70-5 package information
- 5.2 DFN8 2x2 package information
- 5.3 MiniSO-8 package information
- 5.4 QFN16 3x3 package information
- 5.5 TSSOP14 package information
- 6 Ordering information
- 7 Revision history
Features
- Low offset voltage: 200 µV max.
- Low power consumption: 10 µA at 5 V
- Low supply voltage: 1.5 V to 5.5 V
- Gain bandwidth product: 150 kHz typ.
- Low input bias current: 1 pA typ.
- Rail-to-rail input and output
- EMI hardened operational amplifiers
- High tolerance to ESD: 4 kV HBM
- Extended temperature range: -40 to +125 °C Benefits
- Higher accuracy without calibration
- Energy saving
- Guaranteed operation on low-voltage battery
Related products
- See the TSV73 series (900 kHz for 60 μA) for higher gain bandwidth products
Applications
- Battery powered applications
- Portable devices
- Signal conditioning
- Active filtering
- Medical instrumentation
Description
The TSV71x series of single, dual, and quad operational amplifiers offer low-voltage operation, rail-to-rail input and output, and excellent accuracy (V io lower than 200 μV at 25 ° C). These devices benefit from STMicroelectronics®
5 V CMOS technology and offer an excellent
speed/power consumption ratio (150 kHz typical gain bandwidth) while consuming less than 14 μ A at 5 V. The TSV71x series also feature an ultra-low input bias current. The single version (TSV711), the dual version (TSV712), and the quad version (TSV714) are housed in the smallest industrial packages. These characteristics make the TSV71x family ideal for sensor interfaces, battery-powered and portable applications, and active filtering. Single (TSV711) SC70-5 DFN8 2x2 MiniSO-8 Dual (TSV712) Quad (TSV714) QFN16 3x3 TSSOP14
1 Pin connections
Figure 1. Pin connections (top view)
- The exposed pads of the QFN16 3x3 c an be connected to VCC- or left floating.
2 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
- All voltage values, except the differential volt age are with respect to the network ground terminal.
- The differential voltage is a non-inverting input terminal with respect to the inverting input terminal. The
- VCC - Vin must not exceed 6 V, Vin must not exceed 6 V.
- Input current must be limited by a resistor in series with the inputs.
- Short-circuits can c ause excessive heating and destructive dissipation.
- Human body model: 100 pF discharged through a 1.5 k Ω resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
- Machine model: a 200 pF cap is charged to the spec ified voltage, then discharged directly between two
combinations with other pins floating.
- Charged device model: all pins plus package ar e charged together to the specified voltage and then
discharged directly to ground.
Table 2. Operating conditions
3 Electrical characteristics
Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and
- See Section 4.4: Input offset voltage drift over temperature.
- Guaranteed by characterization.
- Slew rate value is calculated as the average between positive and negative slew rates.
- Initialization time is defined as the delay after power-up to guarantee operation within specified performances. Guaranteed
by design. See Section 4.6: Initialization time.
Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and
- See Section 4.4: Input offset voltage drift over temperature.
- Typical value is based on the V io drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
Long-term input offset voltage drift.
- Guaranteed by characterization.
- Slew rate value is calculated as the average between positive and negative slew rates.
- Initialization time is defined as the delay after power -up which guarantees operation within specified performances.
Guaranteed by design. See Section 4.6: Initialization time.
Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C,
- See Section 4.4: Input offset voltage drift over temperature.
- Typical value is based on the V io drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
Long-term input offset voltage drift.
- Guaranteed by characterization.
- Tested on SC70-5 package.
- Slew rate value is calculated as the average between positive and negative slew rates.
- Initialization time is defined as the delay after power-up to guarantee operation within specified performances. Guaranteed
by design. See Section 4.6: Initialization time.
Figure 20. THD+N vs. output voltage Figur e 21. Output impedance vs. frequency
4 Application information
4.1 Operating voltages
The TSV71x series of devices can operate from 1.5 V to 5.5 V. The parameters are fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, they are very stable in the full VCC range and several characterization curves show TSV71x device characteristics at 1.5 V. In addition, the main specifications are guaranteed in the extended temperature range from -40 °C to +125 °C.
4.2 Rail-to-rail input
The TSV711, TSV712, and TSV714 devices have a rail-to-rail input, and the input common mode range is extended from V CC-- 0.1 V to VCC+ + 0.1 V.
4.3 Rail-to-rail output
The output levels of the TSV71x operational amplifiers can go close to the rails: to a maximum of 40 mV below the upper rail and to a maximum of 75 mV above the lower rail when a 10 kΩ resistive load is connected to VCC/2.
4.4 Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 with T = -40 °C and 125 °C. The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk (process capability index) greater than 1.33. ΔVio
4.5 Long-term input of fset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
- Voltage acceleration, by changing the applied voltage
- Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV.K-1) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. AFV e β VS VU–()⋅ AFT e Ea TU TS ⎛⎞⋅ AF AFT AFV×=
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration. Months A F 1000 h× 12 months 24 h 365.25 days×()⁄×= VCC maxVop with Vicm VCC 2⁄== ΔVio Vio drift months()
4.6 Initialization time
(Vio) can be different to the typical ones. Figure 22. Initialization phase
4.7 PCB layouts
possible to the power supply pins. Table 6. Initialization time measurement results
4.8 Macromodel
Accurate macromodels of the TSV71x devices are available on the STMicroelectronics’ website at www.st.com. These model are a trade-off between accuracy and complexity (that is, time simulation) of the TSV71x operational amplifiers. They emulate the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the right operational amplifier, but they do not replace on-board measurements.
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
5.1 SC70-5 package information
Figure 23. SC70-5 package mechanical drawing Table 7. SC70-5 package mechanical data
5.2 DFN8 2x2 pack age information
Figure 24. DFN8 2x2 package mechanical drawing Table 8. DFN8 2x2 package mechanical data
5.3 MiniSO-8 package information
Figure 25. MiniSO-8 package mechanical drawing Table 9. MiniSO-8 package mechanical data
5.4 QFN16 3x3 package information
Figure 26. QFN16 3x3 package mechanical drawing
Figure 27. QFN16 3x3 footprint recommendation Table 10. QFN16 3x3 mm package mechanical data (pitch 0.5 mm)
5.5 TSSOP14 package information
Figure 28. TSSOP14 package mechanical drawing Table 11. TSSOP14 package mechanical data
6 Ordering information
7 Revision history
Table 12. Order codes Table 13. Document revision history Updated Table 3, Table 4, and Table 5.