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- General description The PCAL9554B and PCAL9554C are a low-voltage 8-bit General Purpose Input/Output (GPIO) expanders with interrupt and weak pull-up for I2C-bus/SMBus applications. The only difference between the PCAL9554B and PCAL9554C is their I2C-bus fixed address, allowing a larger number of the same device on the I2C-bus with no chance of address conflicts. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control, etc. In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V allows the PCAL9554B/PCAL9554C to interface with next-generation microprocessors and microcontrollers where supply levels are dropping down to conserve power. The PCAL9554B/PCAL9554C contains the PCA9554A register set of four 8-bit Configuration, Input, Output, and Polarity Inversion registers, and additionally, the PCAL9554B/PCAL9554C has Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. The PCAL9554B is a pin-for-pin replacement for the PCA9554, while the PCAL9554C replaces the PCA9554A, however both versions power-up with all I/O interrupted masked. This mask default allows for a board bring-up free of spurious interrupts at power-up. The PCAL9554B/PCAL9554C open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. Thus, the PCAL9554B or PCAL9554C can remain a simple slave device. The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. Three hardware pins (A0, A1, A2) select the fixed I 2C-bus address and allow up to eight devices to share the same I2C-bus/SMBus. The PCAL9554B and PCAL9554C differ only in their base I2C-bus addresses permitting a total of 16 of the same devices on the I2C-bus, minimizing the chance of address conflict, even in the most complex system. PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O Rev. 2 — 10 December 2012 Product data sheet
Product data sheet Rev. 2 — 10 December 2012 2 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 2. Features and benefits I2C-bus to parallel port expander Operating power supply voltage range of 1.65 V to 5.5 V Low standby current consumption: 1.5 A (typical at 5 V VDD) 1.0 A (typical at 3.3 V VDD) Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs Vhys =0 . 1 0 VDD (typical) 5 V tolerant I/Os Open-drain active LOW interrupt output (INT) 400 kHz Fast-mode I2C-bus Internal power-on reset Power-up with all channels configured as inputs No glitch on power-up Latched outputs with 25 mA drive maximum capability for directly driving LEDs Latch-up performance exceeds 100 mA per JESD78, Class II ESD protection exceeds JESD22 2000 V Human Body Model (A114-A) 1000 V Charged-Device Model (C101) Packages offered: TSSOP16 and HVQFN16
2.1 Agile I/O features
Pin to pin replacement for PCA9554 and PCA9554B, PCA9554A and PCA9554C with interrupts disabled at power-up Software backward compatible with PCA9554 and PCA9554B, PCA9554A and PCA9554C Output port configuration: bank selectable push-pull or open-drain output stages Interrupt status: read-only register identifies the source of an interrupt Bit-wise I/O programming features: Output drive strength: four programmable drive strengths to reduce rise and fall times in low capacitance applications Input latch: Input Port register values changes are kept until the Input Port register is read Pull-up/pull-down enable: floating input or pull-up/down resistor enable Pull-up/pull-down selection: 100 k pull-up/down resistor selection Interrupt mask: mask prevents the generation of the interrupt when input changes state
3.1 Ordering options
Table 1. Ordering information Table 2. Ordering options
6000 Tamb = 40 C to +85 C
2500 Tamb = 40 C to +85 C
Remark: All I/Os are set to inputs at reset.
5.1 Pinning
5.2 Pin description
[1] All I/O are configured as input at power-on. incorporated in the printed-circuit board in the thermal pad region. Table 3. Pin description
Product data sheet Rev. 2 — 10 December 2012 5 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 6. Functional description Refer to Figure 1 “Block diagram of PCAL9554B/PCAL9554C”.
6.1 Device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL9554B/PCAL9554C. Two bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower three bits of the Command byte are used to point to the extended features of the device (Agile I/O). This register is write only. a. PCAL9554B address b. PCAL9554C address Fig 4. Device address R/W 002aah207 0 1 0 0 A2 A1 A0 slave address fixed hardware selectable R/W 002aah208 0 1 1 1 A2 A1 A0 slave address fixed hardware selectable Fig 5. Pointer register bits 002aaf540 B7 B6 B5 B4 B3 B2 B1 B0
6.3 Interface definition
6.4 Register descriptions
6.4.1 Input port register (00h)
performed as described in Section 7.2 “Read commands”.
6.4.2 Output port register (01h)
register, not the actual pin value. Table 4. Command byte Table 5. Interface definition Table 6. Input port register (address 00h)
6.4.3 Polarity inversion register (02h)
‘0’), the corresponding port pin’s original polarity is retained.
6.4.4 Configuration register (03h)
bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
6.4.5 Output drive strength registers (40h, 41h)
Output drive strength control” for more details. Table 7. Output port register (address 01h) Table 8. Polarity inversion register (address 02h) Table 9. Configuration register (address 03h) Table 10. Current control register (address 40h) Table 11. Current control register (address 41h)
6.4.6 Input latch register (42h)
read, then the interrupt is cleared. no additional input(s) that have changed, and bit 4 of the input port register will read ‘1’. The next read of the input port register bit 4 should now read ‘0’. not cleared if the input latch register changes from latched to non-latched configuration. latched input, the read from the input port register reflects the latched logic level.
6.4.7 Pull-up/pull-down enable register (43h)
devices PCA9554B and PCA9554C. Table 12. Input latch register (address 42h) Table 13. Pull-up/pull-down enable register (address 43h)
6.4.8 Pull-up/pull-down selection register (44h)
effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k.
6.4.9 Interrupt mask register (45h)
in the Interrupt mask register is set to 0, the interrupt pin will be asserted. interrupt pin will be de-asserted.
6.4.10 Interrupt status register (46h)
indicates that the input pin is not the source of an interrupt. status bit will return logic 0. Table 14. Pull-up/pull-down selection register (address 44h) Table 15. Interrupt mask register (address 45h) Table 16. Interrupt status register (address 46h)
6.4.11 Output port configuration register (47h)
The output port configuration register selects port-wise push-pull or open-drain I/O stage. configures the I/O as open-drain (Q1 is disabled, Q2 is active).
6.5 I/O port
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. recommended levels for proper operation. Table 17. Output port configuration register (address 47h) On power-up or reset, all registers return to default values.
Product data sheet Rev. 2 — 10 December 2012 11 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.6 Power-on reset
When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCAL9554B/PCAL9554C in a reset condition until VDD has reached VPOR. At that time, the reset condition is released and the PCAL9554B/PCAL9554C registers and I2C-bus/SMBus state machine initialize to their default states. After that, VDD must be lowered to below VPOR and back up to the operating voltage for a power-reset cycle. See Section 8.4 “Power-on reset requirements”.
6.7 Interrupt output (INT )
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt (see Figure 10 ). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input port register. The INT output has an open-drain structure and requires a pull-up resistor to VDD. INT should be connected to the voltage source of the device that requires the interrupt information. When using the input latch feature, the input pin state is latched. The interrupt is reset only when data is read from the port that generated the interrupt. The reset occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Product data sheet Rev. 2 — 10 December 2012 12 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 7. Bus transactions The PCAL9554B/PCAL9554C is an I2C-bus slave device. Data is exchanged between the master and PCAL9554B/PCAL9554C through write and read commands using I2C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Write commands
Data is transmitted to the PCAL9554B/PCAL9554C by sending the device address and setting the Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. Fig 7. Write to Output port register 0 AS slave address(1) START condition R/W acknowledge from slave 002aah124 00000010 command byte A acknowledge from slave 12345678SCL 9 SDA DATA 1 A write to port data out from port tv(Q) acknowledge from slave DATA 1 VALID data to port 1 0 0 A2 A1 A00 P STOP condition (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. Fig 8. Write to Configuration or Polarity inversion registers 0 AS slave address(1) START condition R/W acknowledge from slave 002aah125 0 0 0 0 0 1/0 1/00 command byte A acknowledge from slave 12345678SCL 9 SDA DATA 1 A acknowledge from slave data to register 1 0 0 A2 A1 A00 P STOP condition
Product data sheet Rev. 2 — 10 December 2012 13 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port
7.2 Read commands
To read data from the PCAL9554B/PCAL9554C, the bus master must first send the PCAL9554B/PCAL9554C address with the least significant bit set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart the device address is sent again, but this time the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the PCAL9554B/PCAL9554C (see Figure 9 and Figure 10). Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. Fig 9. Read from register AS START condition R/W acknowledge from slave 002aah126 A acknowledge from slave SDA A P acknowledge from master DATA (first byte) slave address(1) STOP condition S (repeated) START condition (cont.) (cont.) 1 0 0 A2 A1 A0 1 A0 R/W acknowledge from slave slave address(1) at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter NA no acknowledge from master COMMAND BYTE1 0 0 A2 A1 A00 0 data from register DATA (last byte) data from register Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 9). (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. Fig 10. Read Input port register (non-latched) 1 0 0 A2 A1 A0 1 AS0 slave address(1) START condition R/W acknowledge from slave 002aah127 data from port A acknowledge from master SDA 1 no acknowledge from master read from port data into port data from port DATA 1 DATA 4 INT DATA 4 DATA 2 DATA 3 P STOP condition tv(INT) trst(INT) th(D) tsu(D) 12345678SCL 9 DATA 1 DATA 5 INT is cleared by read from port STOP not needed to clear INT
Product data sheet Rev. 2 — 10 December 2012 14 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 9). (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. Fig 11. Read Input port register (latch enabled) 1 0 0 A2 A1 A0 1 AS0 slave address(1) START condition R/W acknowledge from slave 002aah209 data from port A acknowledge from master SDA 1 no acknowledge from master read from port data into port data from port DATA 1 DATA 1 INT DATA 2 DATA 2 P STOP condition tv(INT) trst(INT) th(D) tsu(D) 12345678SCL 9 DATA 1 INT is cleared by read from port STOP not needed to clear INT
Product data sheet Rev. 2 — 10 December 2012 15 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 8. Application design-in information
8.1 Minimizing I DD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 13 shows a high value resistor in parallel with the LED, which is not needed with the PCAL9554B or PCAL9554C that integrate a weak pull-up resistor on all pins. Figure 14 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. Device address is 0100 000x for this example using PCAL9554B (address for PCAL9554C is 0111 000x). P0, P2, P3 configured as outputs. P1, P4, P5 configured as inputs. P6, P7 are not used and need 100 k pull-up resistors to protect them from floating or the internal pull-up or pull-down selected. (1) No resistors are required for inputs (on P port) that may float due to the weak pull-up integrated into the device. Fig 12. Typical application PCAL9554B SCL SDA VDD (3.3 V) MASTER CONTROLLER SCL SDA INT VDDVDD VSS INT 10 kΩ SUB-SYSTEM 1 (e.g., temp sensor) INT SUB-SYSTEM 2 (e.g., counter) RESET controlled switch (e.g., CBT device) A B enable VSS 002aah211 10 kΩ10 kΩ 2 kΩ 100 kΩ (× 3)(1) A0 SUB-SYSTEM 3 (e.g., alarm system) ALARM VDD
Product data sheet Rev. 2 — 10 December 2012 16 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8.2 Output drive strength control
The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure 15 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. Fig 13. High value resistor in parallel with the LED Fig 14. Device supplied by a lower voltage 002aag164 LEDVDD Pn 100 kΩ VDD 002aag165 LEDVDD Pn
3.3 V 5 V
Fig 15. Simplified output stage VDD P0 to P7 Configuration register 002aah108 DECODER PMOS_EN0 PMOS_EN1 PMOS_EN2 PMOS_EN3 NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 Output port register Current Control register PMOS_EN[3:0] NMOS_EN[3:0]
Product data sheet Rev. 2 — 10 December 2012 17 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The output drive strength control through the Current Control registers allows the user to mitigate SSN issues without the need of additional external components. 8.3 12 V tolerant I/Os The PCAL9554B/PCAL9554C device SCR group reference diode can go up to 10 V before latch back to 8 V. The ESD gate oxide will protect the device, but not if used continually. Therefore, to achieve 12 V tolerant I/Os, the external protection circuitry (diode) must be used as shown in Figure 16. Fig 16. External protection circuitry PCAL9554B PCAL9554C A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 002aah210 +5 V +12 V
Product data sheet Rev. 2 — 10 December 2012 18 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8.4 Power-on reset requirements
In the event of a glitch or data corruption, PCAL9554B/PCAL9554C can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 17 and Figure 18. Table 18 specifies the performance of the power-on reset feature for PCAL9554B/PCAL9554C for both types of power-on reset. Fig 17. V DD is lowered below 0.2 V or 0 V and then ramped up to VDD Fig 18. V DD is lowered below the POR threshold, then ramped back up to VDD 002aah329 VDD time ramp-up ramp-down (dV/dt)r (dV/dt)f re-ramp-up (dV/dt)rtime to re-ramp when VDD drops below 0.2 V or to VSS td(rst) 002aah330 VDD time ramp-down (dV/dt)f ramp-up (dV/dt)rtime to re-ramp when VDD drops to VPOR(min) − 50 mV td(rst)VI drops below POR levels
[1] Level that V DD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD <1 s. [2] Glitch width that will not cause a functional disruption when VDD(gl) =0 . 5 VDD. how to measure these specifications. 0V . Figure 20 and Table 18 provide more details on this specification. Table 18. Recommended supply sequencing and ramp rates Tamb =2 5 C (unless otherwise noted). Not tested; specified by design.
Product data sheet Rev. 2 — 10 December 2012 20 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port
8.5 Device current consumption with internal pull-up and pull-down
The PCAL9554B; PCAL9554C integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. Since these pull-up and pull-down resistors are internal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. The pull-up or pull-down function is selected in register 44h, while the resistor is connected by the enable register 43h. The configuration of the resistors is shown in Figure 6 If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from the VDD pin through the resistor to ground when the pin is held LOW. This current will appear as additional IDD upsetting any current consumption measurements. In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH, current will flow from the power supply through the pin to the VSS pin. While this current will not be measured as part of IDD, one must be mindful of the 200 mA limiting value through VSS. The pull-up and pull-down resistors are simple resistors and the current is linear with voltage. The resistance specification for these devices spans from 50 k with a nominal 100 k value. Any current flow through these resistors is additive by the number of pins held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 24 for a graph of supply current versus the number of pull-up resistors.
[1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
- Recommended operating conditions
[1] The package thermal impedance is calc ulated in accordance with JESD 51-7. Table 19. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 20. Operating conditions Table 21. Thermal characteristics
Table 22. Static characteristics Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
typical values are at VDD = 3.3 V and Tamb =2 5 C. [2] The total current sourced by all I/Os must be limited to 160 mA , and total current sunk by all I/Os must be limited to 200 mA. Table 22. Static characteristics …continued Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Product data sheet Rev. 2 — 10 December 2012 24 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port
12.1 Typical characteristics
Fig 21. Supply current versus ambient temperature Fig 22. Standby supply current versus ambient temperature Tamb =2 5 C Fig 23. Supply current versus supply voltage Fig 24. Supply current versus number of I/O held LOW IDD (μA) Tamb (°C) −40 85 6010 35−15 002aah333 VDD = 5.5 V 5.0 V 3.6 V 3.3 V 2.5 V 2.3 V VDD = 1.8 V 1.65 V 600 800 400 1400 IDD(stb) (nA) Tamb (°C) −40 85 6010 35−15 002aah334 VDD = 5.5 V 5.0 V 3.6 V 3.3 V 200 1000 2.5 V 2.3 V 1.8 V 1.65 V IDD (μA) VDD (V) 002aah335 0.6 0.4 0.2 0.8 I DD (mA) number of I/O held LOW 08 624 002aah212 Tamb = −40 °C 25 °C 85 °C
Product data sheet Rev. 2 — 10 December 2012 25 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port a. V DD =1 . 6 5V b . V DD =1 . 8V c. V DD =2 . 5V d . V DD =3 . 3V e. V DD =5 . 0V f . V DD =5 . 5V Fig 25. I/O sink current versus LOW-le vel output voltage with CCX.X = 11b VOL (V) 0 0.3 0.20.1 002aaf578 35I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf579 35I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf580 Isink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf581 I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf582 70I sink (mA) Tamb = −40 °C 25 °C 85 °C VOL (V) 0 0.3 0.20.1 002aaf583 70I sink (mA) Tamb = −40 °C 25 °C 85 °C
Product data sheet Rev. 2 — 10 December 2012 26 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port a. V DD =1 . 6 5V b . V DD =1 . 8V c. V DD =2 . 5V d . V DD =3 . 3V e. V DD =5 . 0V f . V DD =5 . 5V Fig 26. I/O source current versus HIGH-level output voltage with CCX.X = 11b VDD − VOH (V) 0 0.6 0.40.2 002aah110 I source (mA) Tamb = −40 °C 25 °C 85 °C VDD − VOH (V) 0 0.6 0.40.2 002aah111 35I source (mA) Tamb = −40 °C 25 °C 85 °C VDD − VOH (V) 0 0.6 0.40.2 002aah112 I source (mA) Tamb = −40 °C 25 °C 85 °C VDD − VOH (V) 0 0.6 0.40.2 002aah113 70I source (mA) Tamb = −40 °C 25 °C 85 °C VDD − VOH (V) 0 0.6 0.40.2 002aah114 I source (mA) Tamb = −40 °C 25 °C 85 °C VDD − VOH (V) 0 0.6 0.40.2 002aah115 I source (mA) Tamb = −40 °C 25 °C 85 °C
Product data sheet Rev. 2 — 10 December 2012 27 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port (1) V DD = 1.8 V; Isink =1 0m A (2) V DD = 5 V; Isink =1 0m A (3) V DD = 1.8 V; Isink =1m A (4) V DD = 5 V; Isink =1m A Isource = 10 mA Fig 27. LOW-level output voltage versus temperature Fig 28. I/O high voltage versus temperature 100 120VOL (mV) Tamb (°C) −40 85 6010 35−15 002aah056 (1) (3) (4) (2) Tamb (°C) −40 85 6010 35−15 002aah343 160 120 200 VDD − VOH (mV) VDD = 1.8 V 5 V
Table 23. I 2C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Figure 29. Table 24. Switching characteristics Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 29.
Product data sheet Rev. 2 — 10 December 2012 29 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 14. Parameter measurement information a. SDA load configuration b. Transaction format c. Voltage waveforms CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data. (1) See Figure 9. Fig 29. I 2C-bus interface load circuit and voltage waveforms 002aag803 DUT CL = 50 pF RL = 1 kΩ SDA VDD STOP condition (P) Data Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) R/W Bit 0 (LSB) Address Bit 1 Address Bit 7 (MSB) START condition (S) STOP condition (P) two bytes for read Input port register(1) 002aag952 tLOW tHIGH tr tf 0.7 × VDD 0.3 × VDD 0.7 × VDD 0.3 × VDD tSP tBUF tf tHD;STA tr SCL SDA tSU;DAT tHD;DAT tf(o) tVD;ACK tVD;DAT tVD;ACK tSU;STA tSU;STO 002aag804 repeat START condition STOP condition
Product data sheet Rev. 2 — 10 December 2012 30 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port a. Interrupt load configuration b. Voltage waveforms CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. Fig 30. Interrupt load circuit and voltage waveforms 002aah069 DUT CL = 100 pF RL = 4.7 kΩ INT VDD 1 0 0 A2 A1 A0 1 AS0 slave address(1) START condition R/W acknowledge from slave 002aah130 8 bits (one data byte) from port A acknowledge from slaveSDA 1 no acknowledge from master data into port data from port DATA 1 DATA 2 INT DATA 2 DATA 1 P STOP condition tv(INT) trst(INT) tsu(D) 12345678SCL 9 ADDRESS trst(INT) A A View A - A INT Pn tv(INT) 0.5 × VDD 0.5 × VDD View B - B SCL 0.5 × VDDINT R/W A trst(INT) 0.3 × VDD 0.7 × VDD B B
Product data sheet Rev. 2 — 10 December 2012 31 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port a. P port load configuration b. Write mode (R/W =0 ) c. Read mode (R/W =1 ) CL includes probe and jig capacitance. tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo =5 0 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Fig 31. P port load circuit and voltage waveforms 002aag805 DUT CL = 50 pF 500 Ω Pn 2 × VDD 500 Ω 002aag806 SCL SDA P0 A tv(Q) 0.3 × VDD 0.7 × VDD last stable bitunstable data Pn 002aag807 SCL Pn P0 A th(D) 0.3 × VDD 0.7 × VDD tsu(D)
Product data sheet Rev. 2 — 10 December 2012 32 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 15. Package outline Fig 32. Package outline SOT403-1 (TSSOP16) UNIT A1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 16 9 θ AA1 Lp Q detail X L (A )3 HE E c v M A XA y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index
Product data sheet Rev. 2 — 10 December 2012 33 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port Fig 33. Package outline SOT758-1 (HVQFN16) terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.1 2.9 Dh 1.75 1.45 3.1 2.9 1.75 1.45 1.5 1.50.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT758-1 HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm A(1) max. A c detail X yy1 Ce L Eh Dh e b 16 13 X D E C B A 02-03-25 02-10-21 terminal 1 index area 1/2 e 1/2 e A C C Bv M w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1)
Product data sheet Rev. 2 — 10 December 2012 34 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 34) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 25 and 26 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 34.
Table 25. SnPb eutectic process (from J-STD-020C) Table 26. Lead-free process (from J-STD-020C)
Product data sheet Rev. 2 — 10 December 2012 36 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. MSL: Moisture Sensitivity Level Fig 34. Temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature
Product data sheet Rev. 2 — 10 December 2012 37 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 18. Soldering: PCB footprints Fig 35. PCB footprint for SOT403-1 (TSSOP16); reflow soldering DIMENSIONS in mm Ay By D1 D2 Gy HyP1 C Gx sot403-1_fr Hx SOT403-1 solder land occupied area Footprint information for reflow soldering of TSSOP16 package AyByGy C Hy Hx Gx Generic footprint pattern Refer to the package outline drawing for actual layout (0.125) (0.125) D1D2 (4x)
Product data sheet Rev. 2 — 10 December 2012 38 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port Fig 36. PCB footprint for SOT758-1 (HVQFN16); reflow soldering SOT758-1Footprint information for reflow soldering of HVQFN16 package Dimensions in mm Ax Ay Bx By D SLx SLy SPx SPy Gx Gy Hx Hy 4.00 4.00 2.20 2.20 P 0.50 0.24 C 0.90 1.50 1.50 0.30 SPy tot 0.90 SPx tot nSPx nSPy sot758-1_fr occupied area solder land plus solder paste solder land solder paste deposit Issue date 12-03-07 12-03-08 Ay By SLy Ax Bx SLx Gx Hx D GyHy (0.105) SPx C P 0.025 0.025 SPy SPx tot SPy tot nSPx nSPy
Table 27. Abbreviations Table 28. Revision history
- Table 22 “Static characteristics”: Conditions updated for characteristic Cio: added “SDA, SCL” to first condition row; added “P port” to second condition row PCAL9554B_PCAL9554C v.1 20121003 Product data sheet - -
Product data sheet Rev. 2 — 10 December 2012 40 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port 21. Legal information
21.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 2 — 10 December 2012 41 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 December 2012 Document identifier: PCAL9554B_PCAL9554C Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 23. Contents