TSP2100DBV

TPS2101 TI | Alldatasheet

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Technical content

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

/C0068Dual-Input, Single-Output MOSFET Switch With No Reverse Current Flow (No Parasitic Diodes) /C0068IN1 . . . 250-mW , 500-mA N-Channel; 16-mA Max Supply Current /C0068IN2 . . . 1.3-W , 10-mA P-Channel; 1.5-mA Max Supply Current (VAUX Mode) /C0068Advanced Switch Control Logic /C0068CMOS- and TTL-Compatible Enable Input /C0068Controlled Rise, Fall, and Transition Times /C00682.7-V to 4 V Operating Range /C0068SOT-23-5 and SOIC-8 Package /C0068–40°C to 70°C Ambient Temperature Range /C00682-kV Human-Body-Model, 750-V CDM, 200-V Machine-Model Electrostatic- Discharge Protection typical applications /C0068Notebook and Desktop PCs /C0068Palmtops and PDAs

description

The TPS2100 and TPS2101 are dual-input, single-output power switches designed to provide uninterrupted output voltage when transitioning between two independent power supplies. Both devices combine one n-channel (250 mW ) and one p-channel (1.3 W ) MOSFET with a single output. The p-channel MOSFET (IN2) is used with auxiliary power supplies that deliver lower current for standby modes. The n-channel MOSFET (IN1) is used with a main power supply that delivers higher current required for normal operation. Low on-resistance makes the n-channel the ideal path for higher main supply current when power-supply regulation and system voltage drops are critical. When using the p-channel MOSFET, quiescent current is reduced to 0.75mA to decrease the demand on the standby power supply. The MOSFETs in the TPS2100 and TPS2101 do not have the parasitic diodes, found in discrete MOSFETs, which allow the devices to prevent back-flow current when the switch is off. DBV PACKAGE (TOP VIEW) GND IN2 IN1 OUT EN GND IN2 IN1 OUT EN DBV PACKAGE (TOP VIEW) TPS2100 TPS2101 NC – No internal connection Figure 2. VAUX CardBus Implementation 4 Copyright  2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Figure 1. Typical Dual-Input Single-Output

3.3 V VCC

3.3 V VAUX

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000

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(DBV)† SOIC-8 (D) 40°C to85°C TPS2100 EN TSP2100DBV † TPS2100D –40°C to 85°C TPS2101 EN TPS2101DBV † TPS2101D Both packages are available left-end taped and reeled. Add an R suffix to the D device type (e.g., TPS2101DR). † Add T (e.g., TPS2100DBVT) to indicate tape and reel at order quantity of 250 parts. Add R (e.g., TPS2100DBVR) to indicate tape and reel at order quantity of 3000 parts. TPS2100 functional block diagram VCC Select Charge Pump Driver GND OUT SW2 1.3 W SW1 250 mW Pullup Circuit Driver IN1 EN IN2 Discharge Circuit TPS2101 functional block diagram VCC Select Charge Pump Driver GND OUT SW2 1.3 W SW1 250 mW Driver IN1 EN IN2 Pulldown Circuit Discharge Circuit

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables TPS2100 TPS2101 VIN1 VIN2 EN OUT VIN1 VIN2 EN OUT

0 V 0 V XX GND 0 V 0 V XX GND

0 V 3.3 V L GND 0 V 3.3 V H GND 3.3 V 3.3 V L VIN1 3.3 V 3.3 V H VIN1 3.3 V 0 V L VIN1 3.3 V 0 V H VIN1 0 V 3.3 V H VIN2 0 V 3.3 V L VIN2 3.3 V 0 V H VIN2 3.3 V 0 V L VIN2 3.3 V 3.3 V H VIN2 3.3 V 3.3 V L VIN2 XX = don’t care Terminal Functions TERMINAL NO. DESCRIPTIONNAME TPS2100 TPS2101 I/O DESCRIPTION DBV D DBV D EN 1 3 Active-high enable for IN1-OUT switch EN 1 3 I Active-low enable for IN1-OUT switch GND 2 2 2 2 I Ground IN1 5 5 5 5 I Main Input voltage, NMOS drain (250 mW ) IN2 3 1 3 1 I Auxilliary input voltage, PMOS drain (1.3 W ) OUT 4 7, 8 4 7, 8 O Power switch output NC 4, 6 4, 6 No connection detailed description power switches n-channel MOSFET The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 mW at 3.3-V input voltage, and is configured as a high-side switch. p-channel MOSFET The IN2-OUT p-channel MOSFET power switch with typical on-resistance of 1.3 W at 3.3-V input voltage and is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to less than 1.5 mA. charge pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. driver The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that controls the rise times and fall times of the output voltage.

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000

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detailed description (continued) enable The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN (TPS2100) or logic low is present on EN (TPS2101). A logic low input on EN (TPS2100) or logic high on EN (TPS2101) restores bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible with both TTL and CMOS logic levels. the VAUX application for CardBus controllers The PC Card specification requires the support of VAUX to the CardBus controller as well as to the PC Card sockets. Both are 3.3-V requirements; however the CardBus controller’s current demand from the VAUX supply is limited to 10 mA, whereas the PC Card may consume as much as 200 mA. In either implementation, if support of a wake-up event is required, the controller and the socket will transition from the 3.3-V VCC rail to the 3.3-V VAUX rail when the equipment moves into a low power mode such as D3. The transition from VCC to VAUX needs to be seamless in order to maintain all memory and register information in the system. If VAUX is not supported, the system will lose all register information when it transitions to the D3 state. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DBV 309 mW 3.1 mW/°C 170 mW 123 mW D 568 mW 5.7 mW/°C 313 mW 227 mW recommended operating conditions MIN MAX UNIT Input voltage, VI(INx) 2.7 4 V Input voltage, VI at EN and EN 0 4 V Continuous output current, IO(IN1) 500 mA Continuous output current, IO(IN2) 10‡ mA Operating virtual junction temperature, TJ –40 85 °C ‡ The device can deliver up to 220 mA at IO(IN2). However, operation at the higher current levels will result in greater voltage drop across the device, and greater voltage droop when switching between IN1 and IN2.

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating junction temperature range, VI(IN1) = V(IN2) = 3.3 V, IO = rated current (unless otherwise noted) power switch PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT IN1 OUT TJ = 25°C 250 m W rDS( ) On state resistance IN1-OUT TJ = 85°C 300 375 m W rDS(on) On -state resistance IN2 OUT TJ = 25°C 1.3 WIN2-OUT TJ = 85°C 1.5 2.1 W † Pulse-testing techniques maintain junction temperature close to ambient termperature; thermal effects must be taken into account separately. enable input (EN and EN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 2.7 V ≤ VI(INx) ≤ 4 V 2 V VIL Low-level input voltage 2.7 V ≤ VI(INx) ≤ 4 V 0.8 V II Input current TPS2100 EN = 0 V or EN = VI(INx) –0.5 0.5 mA II Input current TPS2101 EN = 0 V or EN = VI(INx) –0.5 0.5 mA supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN = H, TJ = 25°C 0.75 mA TPS2100 EN H, IN2 selected –40°C ≤ TJ ≤ 85°C 1.5 mA TPS2100 EN = L, TJ = 25°C 10 mA II Supply current EN L, IN1 selected –40°C ≤ TJ ≤ 85°C 16 mA II Supply current EN = L, TJ = 25°C 0.75 mA TPS2101 IN2 selected –40°C ≤ TJ ≤ 85°C 1.5 mA TPS2101 EN = H, TJ = 25°C 10 mA, IN1 selected –40°C ≤ TJ ≤ 85°C 16 mA

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switching characteristics, TJ = 25°C, VI(IN1) = VI(IN2) = 3.3 V (unless otherwise noted)† PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT C L = 1 mF, IL = 500 mA 830 IN1-OUT VI(IN2) = 0 C L = 10 mF, IL = 500 mA 840 t Output rise time C L = 1 mF, IL = 10 mA 640 mstr O utput rise time C L = 1 mF, IL = 10 mA 5.5 ms IN2-OUT VI(IN1) = 0 C L = 10 mF, IL = 10 mA 70() C L = 1 mF, IL = 1 mA 5.5 C L = 1 mF, IL = 500 mA 8 IN1-OUT VI(IN2) = 0 C L = 10 mF, IL = 500 mA 93 tf Output fall time C L = 1 mF, IL = 10 mA 23 mstf O utput fall time C L = 1 mF, IL = 10 mA 690 ms IN2-OUT VI(IN1) = 0 C L = 10 mF, IL = 10 mA 6900() C L = 1 mF, IL = 1 mA 6900 tPLH Propagation delay time low to high output IN1-OUT VI(IN2) = 0 C L =1 0mF IL =1 0m A mstPLH Propagation delay time, low-to-high output IN2-OUT VI(IN1) = 0 C L = 10 mF, IL = 10 mA ms tPHL Propagation delay time high to low output IN1-OUT VI(IN2) = 0 C L =1 0mF IL =1 0m A mstPHL Propagation delay time, high-to-low output IN2-OUT VI(IN1) = 0 C L = 10 mF, IL = 10 mA 370 ms † All timing parameters refer to Figure 3.

Figure 3. Test Circuit and Voltage Waveforms

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Figure 4. Propagation Delay and Rise Time Figure 5. Propagation Delay and Fall Time Figure 6. Propagation Delay and Fall Time Figure 7. Propagation Delay and Fall Time

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000

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IN1 Switch Rise Time vs Output Current 12 IN2 Switch Fall Time vs Output Current 13 IN1 Switch Fall Time vs Output Current 14 IN2 Switch Fall Time vs Output Current 15 Output Voltage Droop vs Output Current When Output Is Switched From IN2 to IN1 16 Inrush Current vs Output Capacitance 17 IN1 Supply Current vs Junction Temperature (IN1 Enabled) 18 IN1 Supply Current vs Junction Temperature (IN1 Disabled) 19 IN2 Supply Current vs Junction Temperature (IN2 Enabled) 20 IN2 Supply Current vs Junction Temperature (IN2 Disabled) 21 IN1-OUT On-State Resistance vs Junction Temperature 22 IN2-OUT On-State Resistance vs Junction Temperature 23 Figure 12 700 650 600 500 0.01 0.1 1 10 – Rise Time – 800 850 IN1 SWTICH RISE TIME vs OUTPUT CURRENT 900 100 1000 750 550 C L = 100 mF C L = 47 mF C L = 10 mF C L = 1 mFC L = 0.1 mF IO – Output Current – mA tr sm VI(IN1) = 3.3 V VI(IN2) = 0 V TJ = 25°C Figure 13 0.1 0123456 100 IN2 SWTICH RISE TIME vs OUTPUT CURRENT 1000 789 1 0 – Rise Time – C L = 100 mF C L = 47 mF C L = 10 mF C L = 1 mF C L = 0.1 mF IO – Output Current – mA tr sm VI(IN1) = 0 V VI(IN2) = 3.3 V TJ = 25°C

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–40 –20 0 20 40 – Supply Currenmt – IN1 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN1 ENABLED) 60 80 100 ICC Am VI(INx) = 4 V VI(INx) = 3.3 V VI(INx) = 2.7 V TJ Junction Temperature – °C Figure 19 0.19 0.17 0.15 –40 –20 0 20 40 0.21 0.23 IN1 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN1 DISABLED) 0.25 60 80 100 – Supply Currenmt –ICC Am VI(INx) = 4 V VI(INx) = 3.3 V VI(INx) = 2.7 V TJ Junction Temperature – °C Figure 20 0.6 0.55 0.5 –40 –20 0 20 40 0.65 0.7 IN2 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN2 ENABLED) 0.75 60 80 100 – Supply Currenmt –ICC Am VI(INx) = 4 V VI(INx) = 3.3 V VI(INx) = 2.7 V TJ Junction Temperature – °C Figure 21 0.48 0.44 0.4 –40 –20 0 20 40 0.52 0.56 IN2 SUPPLY CURRENT vs JUNCTION TEMPERATURE (IN2 DISABLED) 0.6 60 80 100 – Supply Currenmt –ICC Am VI(INx) = 4 V VI(INx) = 3.3 V VI(INx) = 2.7 V TJ Junction Temperature – °C

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 22 230 205 180 –40 –20 0 20 40 – IN1-OUT On-State resistance – 255 280 IN1-OUT ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 305 60 80 100 ron m W VI(INx) = 4 V VI(INx) = 3.3 V VI(INx) = 2.7 V TJ Junction Temperature – °C Figure 23 1.25 0.75 0.5 –40 –20 0 20 40 1.5 1.75 IN2-OUT ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 60 80 100 – IN1-OUT On-State resistance –ron W VI(INx) = 4 V VI(INx) = 3.3 V VI(INx) = 2.7 V TJ Junction Temperature – °C

APPLICATION INFORMATION

CardBus or System Controller TPS2100 0.1 mF 0.1 mF 0.1 mF xx mF 3.3 V Figure 24. Typical Application

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000

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power supply considerations (continued) switch transition The n-channel MOSFET on IN1 uses a charge-pump to create the gate-drive voltage, which gives the IN1 switch a rise time of approximately 1 ms. The p-channel MOSFET on IN2 has a simpler drive circuit that allows a rise time of approximately 8 ms. Because the device has two switches and a single enable pin, these rise times are seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limit the surge currents seen by the power supply during switching. thermal protection Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The increased dissipation causes the junction temperature to rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts it off at approximately 125°C (T J). The switch remains off until the junction temperature has dropped. The switch continues to cycle in this manner until the load fault or input power is removed. undervoltage lockout An undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up. Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before input power is removed. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMI and voltage overshoots. power dissipation and junction temperature The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to that of power packages; it is good design practice to check power dissipation and junction temperature. First, find r on at the input voltage, and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r on from Figure 22 or Figure 23. Next calculate the power dissipation using: P D /C0043ron /C0032I2 Finally, calculate the junction temperature: TJ /C0043P D /C0032R /C0113JA /C0041TA Where: TA = Ambient temperature R qJA = Thermal resistance Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally sufficient to obtain a reasonable answer. ESD protection All TPS2100 and TPS2101 terminals incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C.

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,10 M0,200,95 0°–8° 0,25 0,35 0,55 Gage Plane 0,15 NOM 4073253-4/E 05/99 2,60 3,00 0,50 0,30 1,50 1,70 2,80 3,00 0,95 1,45 0,05 MIN Seating Plane NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-178

TPS2100, TPS2101 VAUX POWER-DISTRIBUTION SWITCHES SLVS197D – JUNE 1999 – REVISED JUNE 2000

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D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS2100DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBYI TPS2100DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBYI TPS2100DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBYI TPS2100DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBYI TPS2101D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2101 TPS2101D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2101 TPS2101DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBZI TPS2101DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBZI TPS2101DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBZI TPS2101DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PBZI (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 23-May-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2100DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TPS2100DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TPS2101DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TPS2101DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS2101D D SOIC 8 75 505.46 6.76 3810 4 TPS2101D.A D SOIC 8 75 505.46 6.76 3810 4 Pack Materials-Page 3

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