TSM4405P TSC | Alldatasheet

Document overview

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Technical content

Features

— Low profile package: less than 0.8mm height when mounted on PCB — Occupies only 1.21mm2 of PCB area — Less than 30% of the area of a SC-70 — Excellent thermal and electrical capabilities — Lead free solder bumps available Block Diagram

Ordering Information

Part No. Packing Q’ty TSM4405P Tape & Reel 3kpcs / 7” Absolute Maximum Rating (Ta = 25 oC unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage V DS - 12V V Gate-Source Voltage V GS ± 8 V Continuous Drain Current I D - 4.9 A Pulsed Drain Current I DM - 10 A Maximum Power Dissipation (Steady State) P D 1. 5 W Operating Junction Temperature T J +150 oC Operating Junction and Storage Temperature Range T J, TSTG - 55 to +150 oC Thermal Performance Parameter Symbol Limit Unit Junction to Ambient Thermal Resistance R θja 85 oC/W Junction to Balls Thermal Resistance R θjR 20 oC/W Lateral Power™ for Load Switching and PA Switch SS GD SS GD Bump Side ViewPatent Pending

TSM4405P 2-6 2003/10 rev. F

Electrical Characteristics

Ta = 25 oC, unless otherwise noted Parameter Conditions Symbol Min Typ Max Unit Static Drain-Source Breakdown Voltage V GS = 0V, ID = - 250uA BV DSS - - -- -12 V Drain-Source On-State Resistance VGS = - 1.8V, ID = -1.0A RDS(ON) -- -- 90 mΩ Gate Threshold Voltage V DS = VGS, ID = - 250uA V GS(TH) -- - 0.7 -- V Ta=25 oC -- -- - 1.0 Zero Gate Voltage Drain Current V DS =-12V, VGS = 0V Ta=70 oC IDSS -- -- - 5.0 uA Gate Body Leakage V GS = ± 8V, VDS = 0V I GSS -- -- ± 100 nA Dynamic Total Gate Charge V DS = - 6V, ID = - 1.0A, VGS = - 4.5V Qg -- 9.0 -- nC Input Capacitance C iss -- 800 -- Output Capacitance C oss -- 250 -- Reverse Transfer Capacitance VDS = - 12V, VGS = 0V, f = 1.0MHz Crss -- 100 -- pF Source-Drain Diode Max. Diode Forward Current I S -- -- - 1.0 A Diode Forward Voltage I S = - 1.0A, VGS = 0V V SD -- - 0.7.1 - 1.2 V Source-Drain Reverse Recovery Time I S = - 1.0A, VGS = 0V, di / dt = 100A / uS Trr -- 40 -- nS Note : pulse test: pulse width <=300uS, duty cycle <=2%

TSM4405P 3-6 2003/10 rev. F Typical Characteristics Curve (Ta = 25 oC unless otherwise noted)

TSM4405P 4-6 2003/10 rev. F Typical Characteristics Curve (Ta = 25 oC unless otherwise noted)

TSM4405P 5-6 2003/10 rev. F Dimensional Outline and Pad Layout 0.50mm 0.50mm Ø 0.30mm Solder Mask Ø ~ 0.28mm (Solder Mask Defined Pads) S S D G D = Drain Pad S = Source Pad G = Gate Pad SILICON 0.27mm LAND PATTERN RECOMMENDATION 0.757mm +/-0.03mm 1.15mm +/- 0.05mm 0.50mm 0.30mm Bump Ø 0.37mm 1.15mm +/-0.05mm 0.30mm0.50mm Bumps are Lead Free solder 96.8 Sn / 2.6 Ag / 0.6 Cu CXXXX BACKSIDE VIEW (No Bump Side View) Mark on backside of die C = 4405P Product Code XXXX = Lot Traceability Code Mark is located in lower right quadrant on top of Drain pad. Gate pad is located in lower left quadrant. Patents are pending on the product described in the data sheet. Lateral Power TM and MicroSURFTM are trademarks of Great Wall Semiconductor Corporation.

TSM4405P 6-6 2003/10 rev. F BGA FET Tape and reel Specification 1. Tape and Reel 1.1. Reel Size: 7 inch diameter. 1.2. Qty / Reel: 3,000pcs 1.3. Peel Strength: 1.3.1. Peel strength must be between 20 to 80 grams. 1.3.2. Minimum peel back length is 150 mm. 1.3.3. Peel back speed must be between 300 +/-5 mm per minute. 1.3.4. Peel back angle must be bet ween 165 to 185 degrees with respect to the component carrier along the longitudinal axis of the carrier tape. 1.3.5 Peel strength test must be performed at the trailer. 1.4. Part Orientation: Ma rking in upper right quadrant 2. Tape Leader and Trailer Die Size Leader Trailer 1.1 mm x 1.1 mm 500 mm 160 mm 3. Tape Dimension Die Size Tape size W1 C D K H P F B