TSLW201R

TSLW201R TAOS | Alldatasheet

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TAOS047B – JANUARY 2003 The LUMENOLOGY Company Copyright 2003, TAOS Inc. www.taosinc.com Optical Glass Window 64 × 1 Sensor-Element Organization

200 Dots-Per-Inch (DPI) Sensor Pitch

High Linearity and Uniformity Wide Dynamic Range... 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply Replacement for TSLW201

Description

The TSLW201R linear sensor array consists of a 64 × 1 array of photodiodes, associated charge amplifier circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 120 µm (H) by 70 µm (W) with 125-µm center-to-center spacing and 55-µm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. The TSLW201R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear and rotary encoding. Functional Block Diagram SI CLK 64-Bit Shift Register Q64 Switch Control Logic Integrator Reset Pixel 1 Pixel Pixel Pixel Sample/ Output Analog Bus Output Amplifier 6,7 Gain Trim Q3Q2Q1 VDD R L (External Load) AO (TOP VIEW) SI CLK AO VDD GND GND GND GND Texas Advanced Optoelectronic Solutions Inc.

800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759

TAOS047B – JANUARY 2003 Copyright 2003, TAOS Inc. The LUMENOLOGY Company www.taosinc.com Terminal Functions TERMINAL DESCRIPTIONNAME NO. DESCRIPTION AO 3 Analog output. CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 5, 6, 7, 8Ground (substrate). All voltages are referenced to the substrate. SI 1 Serial input. SI defines the start of the data-out sequence. VDD 4 Supply voltage. Supply voltage for both analog and digital circuits. Detailed Description The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2) †. As the SI pulse is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 65th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 65th clock pulse is required to terminate the output of the 64th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented on the 66th clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee) (tint) where: Vout is the analog output voltage for white condition Vdrk is the analog output voltage for dark condition R e is the device responsivity for a given wavelength of light given in V/(µJ/cm2) Ee is the incident irradiance in µW/cm 2 tint is integration time in seconds AO is driven by a source follower that requires an external pulldown resistor (330 ohms typ.). The source follower configuration permits an analog wired OR hookup of multiple devices. When the device is not in the output phase AO is in a high impedance state. The output is nominally 0 volts for no light and 2 volts for a nominal white level output, with a nominal full-scale (saturation) voltage of 2.5V. A 0.1 µF bypass capacitor should be connected between V DD and ground as close as possible to the device. † For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.

TAOS047B – JANUARY 2003 The LUMENOLOGY Company Copyright 2003, TAOS Inc. www.taosinc.com Absolute Maximum Ratings† Voltage range applied to any output in the high impedance or † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) MIN NOM MAX UNIT Supply voltage, VDD 4.5 5 5.5 V Input voltage, VI 0 VDD V High-level input voltage, VIH 2 VDD V Low-level input voltage, VIL 0 0.8 V Wavelength of light source, λ 400 1000 nm Clock frequency, fclock 5 5000 kHz Sensor integration time, tint 0.017 100 ms Operating free-air temperature, TA 0 70 °C Load resistance, RL 300 4700 Ω Load capacitance, CL 470 pF

TAOS047B – JANUARY 2003 Copyright 2003, TAOS Inc. The LUMENOLOGY Company www.taosinc.com Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, R L = 330 Ω , Ee = 18 µW/cm 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vout Analog output voltage (white, average over 64 pixels)See Note 1 1.6 2 2.4 V Vdrk Analog output voltage (dark, average over 128 pixels) 0 0.07 0.15 V PRNU Pixel response nonuniformity See Notes 2 & 3 ±4% ±7.5% Nonlinearity of analog output voltage See Note 3 ±0.4% FS Output noise voltage See Note 4 1 mVrms R e Responsivity 50 120 mV SE Saturation exposure See Note 5 155 nJ/cm2 Vsat Analog output saturation voltage 2.5 3.4 V DSNU Dark signal nonuniformity All pixels See Note 6 25 120 mV IL Image lag See Note 7 0.5% IDD Supply current 3.4 4 mA IIH High-level input current VI = VDD 1 µA IIL Low-level input current VI = 0 1 µA C i(SI) Input capacitance, SI 5 pF C i(CLK) Input capacitance, CLK 5 pF NOTES: 1. The array is uniformly illuminated with a diffuse LED source having a peak wavelength of 640 nm. 2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 5. Minimum saturation exposure is calculated using the maximum responsivity and minimum output saturation voltage figures. 6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination. 7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL V AO (IL)V AO (dark) V AO (white)V AO (dark) 100 Timing Requirements (see Figure 1 and Figure 2) MIN NOM MAX UNIT Setup time, serial input, tsu(SI) (see Note 8) 20 ns Hold time, serial input, th(SI) (see Note 9 and Note 9) 0 ns Pulse duration, clock high or low, tw 50 ns Input transition (rise and fall) time, tr, tf 0 500 ns NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 9. SI must go low before the rising edge of the next clock pulse. Operating Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ts Analog output settling time to ±1% R L = 330 Ω , C L = 10 pF 185 ns

65 Clock Cycles

Figure 1. Timing Waveforms Figure 2. Operational Waveforms

TAOS047B – JANUARY 2003 Copyright 2003, TAOS Inc. The LUMENOLOGY Company www.taosinc.com TYPICAL CHARACTERISTICS 0.4 300 500 700 900 0.6 0.8 PHOTODIODE SPECTRAL RESPONSIVITY 0.2 λ – Wavelength – nm Normalized Responsivity TA = 25°C 1100400 600 800 1000 Figure 3 Figure 4 ANALOG OUTPUT SETTLING TIME vs LOAD CAPACITANCE AND RESISTANCE R L – Load Resistance – Ω 200 0 400 800 1200 300 400 100 VDD = 5 V Vout = 1 V 500 200 600 1000 ts — Settling Time to 1% — ns 600 100 pF 470 pF 220 pF 10 pF

The integrated circuit is mounted in a window frame package with a clear, flat glass cover. NOTES: A. All linear dimensions are in inches and parenthetically in [millimeters] ( ± 0.1 mm unless otherwise noted). B. Pixel 1 typical location aligns on leading edge of pin 1 and 0.71 mm above package centerline. C. Glass thickness nominally 1 mm with refraction index of 1.5186. Figure 5. Packaging Configuration

TAOS047B – JANUARY 2003 Copyright 2003, TAOS Inc. The LUMENOLOGY Company www.taosinc.com PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated.