TSLW1401R

TSLW1401R TAOS | Alldatasheet

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128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS044E − NOVEMBER 2004 The LUMENOLOGY Company Copyright 2004, TAOS Inc. www.taosinc.com 128 × 1 Sensor-Element Organization

400 Dots-Per-Inch (DPI) Sensor Pitch

High Linearity and Uniformity Wide Dynamic Range... 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required Replacement for TSLW1401

Description

The TSLW1401R linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier circuitry, and an internal pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 µm (H) by 55.5 µm (W) with 63.5-µm center-to-center spacing and 8-µm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. Functional Block Diagram SI CLK 128-Bit Shift Register Q128 Switch Control Logic Integrator Reset Pixel 1 Pixel Pixel 128 Pixel Sample/ Output Analog Bus Q3Q2Q1Hold Output Buffer Gain Trim VDD AO GND 5 − 8 Texas Advanced Optoelectronic Solutions Inc.

800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759

(TOP VIEW) SI CLK AO VDD GND GND GND GND

128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS044E − NOVEMBER 2004 Copyright 2004, TAOS Inc. The LUMENOLOGY Company www.taosinc.com Terminal Functions TERMINAL DESCRIPTIONNAME NO. DESCRIPTION AO 3 Analog output. CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 5, 6, 7, 8 Ground (substrate). All voltages are referenced to the substrate. SI 1 Serial input. SI defines the start of the data-out sequence. VDD 4 Supply voltage. Supply voltage for both analog and digital circuits. Detailed Description The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to a known state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of t qt (pixel charge transfer time) after the 129th clock pulse. AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout is the analog output voltage for white condition Vdrk is the analog output voltage for dark condition R e is the device responsivity for a given wavelength of light given in V/(µJ/cm2) Ee is the incident irradiance in µW/cm 2 tint is integration time in seconds A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device. The TSLW1401R is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding.

128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS044E − NOVEMBER 2004 The LUMENOLOGY Company Copyright 2004, TAOS Inc. www.taosinc.com Absolute Maximum Ratings† † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) MIN NOM MAX UNIT Supply voltage, VDD 3 5 5.5 V Input voltage, VI 0 VDD V High-level input voltage, VIH 2 VDD V Low-level input voltage, VIL 0 0.8 V Wavelength of light source, λ 400 1000 nm Clock frequency, fclock 5 8000 kHz Sensor integration time, tint (see Note 1) 0.03375 100 ms Setup time, serial input, tsu(SI) 20 ns Hold time, serial input, th(SI) (see Note 2) 0 ns Operating free-air temperature, TA −40 85 °C NOTES: 1. Integration time is calculated as follows: tint = (128 − 18) clock period + 20 s where 128 is the number of pixels in series, 18 is the required logic setup clocks, and 20 s is the pixel charge transfer time (tqt) 2. SI must go low before the rising edge of the next clock pulse.

128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS044E − NOVEMBER 2004 Copyright 2004, TAOS Inc. The LUMENOLOGY Company www.taosinc.com Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, R L = 330 Ω , Ee = 12.5 µW/cm 2 (unless otherwise noted) (see Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vout Analog output voltage (white, average over 128 pixels)See Note 4 1.6 2 2.4 V Vdrk Analog output voltage (dark, average over 128 pixels)Ee = 0 0 0.1 0.2 V PRNU Pixel response nonuniformity See Note 5 ± 4% ± 7.5% Nonlinearity of analog output voltage See Note 6 ± 0.4% FS Output noise voltage See Note 7 1 mVrms R e Responsivity See Note 8 20 30 40 V/ (µJ/cm2) V Analog output saturation voltage VDD = 5 V, RL = 330 Ω 4.5 4.8 VVsat Analog output saturation voltage VDD = 3 V, RL = 330 Ω 2.5 2.8 V SE Saturation exposure VDD = 5 V, See Note 9 155 nJ/cm2SE Saturation exposure VDD = 3 V, See Note 9 89 nJ/cm2 DSNU Dark signal nonuniformity All pixels, Ee = 0, See Note 10 0.02 0.05 V IL Image lag See Note 11 0.5% I Supply current VDD = 5 V, Ee = 0 2.8 4.5 mAIDD Supply current VDD = 3 V, Ee = 0 2.6 4.5 mA IIH High-level input current VI = VDD 1 µA IIL Low-level input current VI = 0 1 µA C i Input capacitance 5 pF NOTES: 3. All measurements made with a 0.1 µF capacitor connected between VDD and ground. 4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. R e(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint) 9. SE(min) = [Vsat(min) − Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) − Vdrk(min)] 10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL V out (IL)V drk V out (white)V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN NOM MAX UNIT tsu(SI) Setup time, serial input (see Note 12) 20 ns th(SI) Hold time, serial input (see Note 12 and Note 13) 0 ns tw Pulse duration, clock high or low 50 ns tr, tf Input transition (rise and fall) time 0 500 ns tqt Pixel charge transfer time 20 µs NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 13. SI must go low before the rising edge of the next clock pulse. Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ts Analog output settling time to ± 1% R L = 330 Ω , C L = 10 pF 120 ns

18 Clock Cycles

129 Clock Cycles

Figure 1. Timing Waveforms Figure 2. Operational Waveforms

The integrated circuit is mounted in a window frame package with a clear, flat glass cover. NOTES: A. All linear dimensions are in inches and parenthetically in [millimeters] ( ± 0.1 mm unless otherwise noted). B. Pixel 1 typical location aligns on leading edge of pin 1 and 0.71 mm above package centerline. C. Glass thickness nominally 1 mm with refraction index of 1.5186. Figure 9. Packaging Configuration

128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS044E − NOVEMBER 2004 The LUMENOLOGY Company Copyright 2004, TAOS Inc. www.taosinc.com PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced Optoelectronic Solutions Incorporated.

128 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS044E − NOVEMBER 2004 Copyright 2004, TAOS Inc. The LUMENOLOGY Company www.taosinc.com