TSH343_07 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 17
Technical content
Datasheet sections
- 1 Absolute maximum ratings and operating conditions
- 2 Electrical characteristics
- 3 Application information
- 3.1 Using the TSH343 to drive Y -Pb-Pr video components
- 3.2 PSRR and improvement of power supply noise rejection
- 3.3 Delay between channels
- 4 Package mechanical data
- 5 Ordering information
- 6 Revision history
Features
■ Bandwidth: 280MHz ■ 5V single-supply operation ■ Internal input DC level shifter ■ No input capacitor required ■ 6dB internal gain for a matching between 3 channels ■ Very low harmonic distortion ■ Slew rate: 780V/μs ■ Specified for 150Ω and 100Ω loads ■ Min. and max. data tested during production
Applications
■ High-end video systems ■ High definition TV (HDTV) ■ Broadcast and graphic video ■ Multimedia products
Description
The TSH343 is a triple single-supply video buffer featuring an internal gain of 6dB and a large 280MHz bandwidth. The main advantage of this circuit is that its input DC level shifter allows for video signals on 75Ω video lines without damage to the synchronization tip of the video signal, while using a single 5V power supply with no input capacitor. The DC level shifter is internally fixed and optimized to keep the output video signals between low and high output rails in the best position for the greatest linearity. This datasheet provides information on using the TSH343 as a Y -Pb-Pr driver for video DAC output on a video line. See the TSH344 datasheet for R- G-B signals. The TSH343 is available in the compact SO8 plastic package for optimum space-saving. Top View OUT2 IN2 OUT1 +Vcc OUT3 IN1 6IN3 GND SO8 Pin1 identification DC Shifter 6dB 6dB 6dB
1 Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
- All voltage values, except differential volt age, are with respect to network terminal.
- The magnitude of input and output voltages must never exceed V CC +0.3V.
Table 2. Operating conditions
- Tested in full production at 0V/5V single power supply.
2 Electrical characteristics
Table 3. V CC = +5V single supply, Tamb = 25°C (unless otherwise specified)
- See Figure 28 and Figure 29.
- See Figure 30 and Figure 31.
- Non-tested value, guaranteed by design.
Table 3. V CC = +5V single supply, Tamb = 25°C (unless otherwise specified) (continued)
3 Application information
3.1 Using the TSH343 to dri ve Y-Pb-Pr video components
Figure 25. Shapes of video signals coming from DACs Figure 26. TSH343 in single supply for any DAC output
- See the TSH344 datasheet on st.com for more informat ion. It is possible to drive RGB signals with the
- Fclock=74.25MHz t=1/Fclock=13.5ns Synchronization tip (0 IRE) White (100 IRE) 0.030V 0.330V 1.030V 700mV time Frequency Amplitude 30MHz 1Vp-p Pb,B video outputs LPF LPF LPF Cable Cable Cable +5V 75Ω 75Ω 75Ω TSH343 SO8 Y,G(+synchro) DAC DAC DAC Pr,R G video outputs LPF LPF LPF Cable Cable Cable +5V 75Ω 75Ω 75Ω TSH344 SO8 R DAC DAC DAC B HDTV Digital synchro
3.2 PSRR and improvement of power supply noise rejection
Figure 28. Circuit for power supply bypassing on how carefully the power supply decoupling is achieved. Figure 29. Power supply noise rejection
- In DC, the resistance (R) of the ferrite must be as low as possible to keep +5V power supply on the chip.
- In AC, along a 30MHz bandwidth (HD spectrum), the equivalent impedance (Z=R+jX) must be as high as possible to optimize rejection of the noise generated by the power supply. 50Ω +5V 75Ω TSH343 T-bias AGILENT 4395A S R A L CLF CHF 50Ω +5V 75Ω TSH343 T-bias AGILENT 4395A S R A L CLF CHF 100k 1M 10M 100M -80 -70 -60 -50 -40 -30 -20 -10 L= Ferrite FBMJ4516HM900 CHF=100nF CLF=10uF PSRR L=2uH CHF=100nF CLF=10uF PSRR (dB) Frequency (Hz)
3.3 Delay between channels
Figure 30. Measurement of the delay between each channel between the inputs and the outputs is 4ns. Figure 31. Relative delay between each channel
4 Package mechanical data
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com
Figure 32. SO-8 package
5 Ordering information
6 Revision history
Table 4. Order codes Table 5. Document revision history 1-Dec-2005 1 First release of datasheet. 2-Jan-2006 2 Capa-load option paragraph deleted on page 11. 10-Jul-2006 3 Application information. Max limit for input DC shift reduced from 800mV to 670mV.