TSH111IPT

TSH110 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

■ LOW NOISE: 3nV/ √Hz ■ LOW SUPPLY CURRENT: 3.2mA ■ 47mA OUTPUT CURRENT ■ BANDWIDTH: 100MHz ■ 5V to 12V SUPPLY VOLTAGE ■ SLEW-RATE: 450V/ µs ■ SPECIFIED FOR 100 Ω Load ■ VERY LOW DISTORTION ■ TINY: SOT23-5, TSSOP and SO PACKAGES

DESCRIPTION

The singles TSH110 and TSH111, the dual TSH112, the triple TSH113 and the quad TSH114 are current feedback operational amplifiers featur- ing a very high slew rate of 450V/µs and a large bandwidth of 100MHz, with only a 3.2mA quies- cent supply current. The TSH111 and TSH113 feature a Standby function for each operator. This function is a power down mode with a high output impedance. These devices operate from ±2.5V to ±6V dual supply voltage or from 5V to 12V single supply voltage. They are able to drive a 100Ω load with a swing of 9V minimum (for a 12V power supply). The harmonic and intermodulation distortions of these devices are very low, making this circuit a good choice for applications requiring wide band- width with multiple carriers. For board space and weight saving, the TSH110 comes in miniature SOT23-5 package, the TSH111 comes in SO8 and TSSOP8 packages, the TSH112 comes in SO8 and TSSOP8 packag- es, the TSH113 and TSH114 comes in SO14 and TSSOP14 packages.

APPLICATIONS

■ High End Video Drivers ■ Receiver for xDSL ■ A/D Converter Driver ■ High End Audio Applications PIN CONNECTIONS (top view) VCC - VCC + + - Non Inverting Input Inverting Input TSH110 : SOT23-5 VCC - VCC + NC NC STANDBY Non Inverting Input Inverting Input Output TSH111 : SO8/TSSOP8 VCC - VCC +1 6Non Inverting Input1 Inverting Input1 Output2 Output1 Non Inverting Input2 Inverting Input2+ TSH112 : SO8/TSSOP8 VCC + VCC - 114 Non Inverting Input1 Inverting Input1 Output3 Output1 Non Inverting Input3 Inverting Input3 7 8 Output2 Non Inverting Input2 Inverting Input2 STANDBY1 STANDBY2 STANDBY3 TSH113 : SO14/TSSOP14 VCC + VCC - 114 Non Inverting Input2 Inverting Input2 Output4 Output2 Non Inverting Input4 Inverting Input4 7 8 Output3 Non Inverting Input3 Inverting Input3 Output1 Non Inverting Input1 Inverting Input1 TSH114 : SO14/TSSOP14 Output 1 VCC - VCC + + - Non Inverting Input Inverting Input TSH110 : SOT23-5 VCC - VCC + NC NC STANDBY Non Inverting Input Inverting Input Output TSH111 : SO8/TSSOP8 VCC - VCC +1 6Non Inverting Input1 Inverting Input1 Output2 Output1 Non Inverting Input2 Inverting Input2+ TSH112 : SO8/TSSOP8 VCC + VCC - 114 Non Inverting Input1 Inverting Input1 Output3 Output1 Non Inverting Input3 Inverting Input3 7 8 Output2 Non Inverting Input2 Inverting Input2 STANDBY1 STANDBY2 STANDBY3 TSH113 : SO14/TSSOP14 VCC + VCC - 114 Non Inverting Input2 Inverting Input2 Output4 Output2 Non Inverting Input4 Inverting Input4 7 8 Output3 Non Inverting Input3 Inverting Input3 Output1 Non Inverting Input1 Inverting Input1 TSH114 : SO14/TSSOP14 Output TSH110-111-112-113-114 WIDE BAND, LOW NOISE OPERATIONAL AMPLIFIERS February 2002

TSH110-TSH111-TSH112-TSH113-TSH114 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS ORDER CODES D = Small Outline Package (SO) - also available in Tape & Reel (DT) P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape & Reel (PT) L = Tiny Package (SOT23-5) - only available in Tape & Reel (LT) Symbol Parameter Value Unit VCC Supply Voltage 1) 14 V Vid Differential Input Voltage 2) ±1 V Vi Input Voltage 3) ±6 V Toper Operating Free Air Temperature Range -40 to +85 °C Tstg Storage Temperature -65 to +150 °C Tj Maximum Junction Temperature 150 °C R thjc Thermal resistance junction to case °C/W SOT23-5 80 SO8 28 SO14 22 TSSOP8 37 TSSOP14 32 R thja Thermal resistance junction to ambiante area °C/W SOT23-5 250 SO8 157 SO14 125 TSSOP8 130 TSSOP14 110 ESD Human Body Model 2.0 kVMachine Model 0.2 Charged Device Model 1.5 ouput short circuit duration 4) 1. All voltages values, except differential voltage are with respect to network ground terminal 2. Differential voltages are non-inverting input terminal with respect to the inverting terminal 3. The magnitude of input and output must never exceed VCC +0.3V 4. Short-circuits can cause excessive heating. Destructive dissipation can result. Symbol Parameter Value Unit VCC Supply Voltage 5 to 12 V Vicm Common Mode Input Voltage Range VCC-+1.5 to VCC+ -1.5 V Type Temperature Package TSH110ILT (code K302) -40° to +85°C SOT23-5 TSH111ID SO8 TSH111IDT SO8 TSH111IPT TSSOP8 TSH112ID SO8 TSH112IDT SO8 TSH112IPT TSSOP8 TSH113ID SO14 TSH113IDT SO14 TSH113IPT TSSOP14 TSH114ID SO14 TSH114IDT SO14 TSH114IPT TSSOP14

TSH110-TSH111-TSH112-TSH113-TSH114 ELECTRICAL CHARACTERISTICS (pages 3 and 4) Dual Supply Voltage, VCC = ±2.5Volts, R*fb = 680Ω , Tamb = 25°C (unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit DC PERFORMANCE Vio Input Offset Voltage Tamb -1.5 0.3 2.0 mV Tmin. < Tamb < Tmax. 1m V Δ Vio Input Offset Voltage Drift vs. TemperatureTmin. < Tamb < Tmax. 5 µV/°C Iib+ Non Inverting Input Bias Current Tamb -10 1.4 13 µA Tmin. < Tamb < Tmax. 2.5 µA Iib- Inverting Input Bias Current Tamb -3 1.9 7 µA Tmin. < Tamb < Tmax. 2.5 µA R OL Transimpedance R L=100Ω 500 750 k Ω ICC Supply Current per Operator Tamb 3.2 4 mA Tmin. < Tamb < Tmax. 3.5 mA CMR Common Mode Rejection Ratio (Δ Vic/ΔVio) 56 60 dB SVR Supply Voltage Rejection Ratio (Δ VCC/ ΔVio) 70 80 dB PSR Power Supply Rejection Ratio (Δ VCC/ ΔVout) Gain=1, Rload=3.9kΩ 48 dB DYNAMIC PERFORMANCE and OUTPUT CHARACTERISTICS V oh High Level Output Voltage Tamb R L = 100Ω 1.4 2 V Tmin. < Tamb < Tmax. R L = 100Ω GND 1.9 V Vol Low Level Output Voltage Tamb R L = 100Ω -1.8 -1.3 V Tmin. < Tamb < Tmax. R L = 100Ω -1.7 V | Isink | Output Sink current Tmin. < Tamb < Tmax. 20 mA Isource Output Source current Tmin. < Tamb < Tmax. 18 mA BW -3dB Bandwidth Vout=1Vpk, Rfb*=820Ω //2pF Load=100Ω AVCL =+2 81 MHz SR Slew Rate AVCL =+2, 2V step Load=100Ω 160 230 V/ µs Tr Rise Time for 200mV step AVCL =+2, Rfb*=820Ω //2pF Load=100Ω 9n s Tf Fall Time 9n s Ov Overshoot 16 % St Settling Time @ 0.05% 60 ns ΔG Differential gain AVCL =+2, RL=100Ω F=4.5MHz, Vout=1Vpeak 0.05 % Δφ Differential phase 0.05 °

TSH110-TSH111-TSH112-TSH113-TSH114 (*) Rfb is the feedback resistance between the output and the inverting input of the amplifier. NOISE AND HARMONIC PERFORMANCE en Equivalent Input Voltage Noise Frequency : 1MHz 3 nV/ √Hz in Equivalent Input Current Noise 8.5 pA/ √Hz THD Total Harmonic Distortion AVCL =+2, F=2MHz R L=100Ω Vout=2Vpeak 64.4 dB IM3 Third order inter modulation product AVCL =+2, Vout=2Vpp R L=100Ω F1=1MHz, F2=1.1MHz dBc@900kHz 90 @1.2MHz 90 @3.1MHz 86 @3.2MHz 83 MATCHING CHARACTERISTICS Gf Gain Flatness F=(DC) to 6MHz A VCL =+2, Vout=2Vpp 0.1 dB Vo1/Vo2 Channel Separation F=1MHz to 10MHz 65 dB Symbol Parameter Test Condition Min. Typ. Max. Unit

TSH110-TSH111-TSH112-TSH113-TSH114 ELECTRICAL CHARACTERISTICS (pages 5 and 6) Dual Supply Voltage, VCC =±6Volts, R*fb = 680Ω , Tamb = 25°C (unless otherwise specified) Symbol Parameter TestCondition Min. Typ. Max. Unit DC PERFORMANCE Vio Input Offset Voltage Tamb -1.0 0.9 3.0 mV Tmin. < Tamb < Tmax. 1.3 mV Δ Vio Input Offset Voltage Drift vs TemperatureTmin. < Tamb < Tmax. 5 µV/°C Iib+ Non Inverting Input Bias Current Tamb -12 1 14 µA Tmin. < Tamb < Tmax. 1.7 µA Iib - Inverting Input Bias Current Tamb -4 3 10 µA Tmin. < Tamb < Tmax. 3.4 µA R OL Transimpedance R L=100Ω 600 900 k Ω ICC Supply Current per Operator Tamb 45m A Tmin. < Tamb < Tmax. 4.1 mA CMR Common Mode Rejection Ratio (Δ Vic/ΔVio) 58 63 dB SVR Supply Voltage Rejection Ratio (Δ Vcc/ΔVio) 72 80 dB PSR Power Supply Rejection Ratio (Δ Vcc/ΔVout) Gain=1, Rload=3.9kΩ 49 dB DYNAMIC PERFORMANCE and OUTPUT CHARACTERISTICS V oh High Level Output Voltage Tamb R L = 100Ω 4.5 4.7 V Tmin. < Tamb < Tmax. R L = 100Ω 4.6 V Vol Low Level Output Voltage Tamb R L = 100Ω -4.7 -4.3 V Tmin. < Tamb < Tmax. R L = 100Ω -4.6 V | Isink | Output Sink current Tmin. < Tamb < Tmax. 47 mA Isource Output Source current Tmin. < Tamb < Tmax. 46 mA Bw -3dB Bandwidth Vout=1Vpk, Rfb*=680Ω //2pF Load=100Ω AVCL =+2 100 MHz SR Slew Rate AVCL =+2, 6V step Load=100Ω 240 450 V/ µs Tr Rise Time for 200mV step AVCL =+2, Rfb*=680Ω //2pF Load=100Ω 10.4 ns Tf Fall Time 12.2 ns Ov Overshoot 17 % St Settling Time @ 0.05% 40 ns ΔG Differential gain AVCL =+2, RL=100Ω F=4.5MHz, Vout=2Vpeak 0.05 % Δφ Differential phase 0.05 °

TSH110-TSH111-TSH112-TSH113-TSH114 (*) Rfb is the feedback resistance between the output and the inverting input of the amplifier. NOISE AND HARMONIC PERFORMANCE en Equivalent Input Voltage Noise Frequency : 1MHz 3 nV/ √Hz in Equivalent Input Current Noise 8.6 pA/ √Hz THD Total Harmonic Distortion AVCL =+2, F=2MHz R L=100Ω Vout=4Vpp 67.7 dB IM3 Third order inter modulation product AVCL =+2, Vout=4Vpp R L=100Ω F1=1MHz, F2=1.1MHz dBc@900kHz 82 @1.2MHz 84 @3.1MHz 77 @3.2MHz 73 MATCHING CHARACTERISTICS Gf Gain Flatness F=(DC) to 6MHz A VCL =+2, Vout=4Vpp 0.1 dB Vo1/Vo2 Channel Separation F=1MHz to 10MHz 65 dB Symbol Parameter TestCondition Min. Typ. Max. Unit

TSH110-TSH111-TSH112-TSH113-TSH114 STANDBY MODE Tamb = 25°C (unless otherwise specified), VCC =±6Volts Symbol Parameter Test Condition Min. Typ. Max. Unit Vlow Standby Low Level VCC - (VCC +0.8) V Vhigh Standby High Level (VCC - +2) (V CC +) V ICC SBY Current Consumption per Operator in Standby mode 26 40 µA Isol Input/Output Isolation F=1MHz -90 dB Zout Output Impedance (Rout // Cout) R out C out M Ω pF Ton Time from Standby Mode to Active Mode 2 µs Toff Time from Active Mode to Standby Mode Down to ICC SBY = 40µA 13 µs TSH111 STANDBY CONTROL pin 8 (SBY ) OPERATOR STATUS Vlow Standby Vhigh Active TSH113 STANDBY CONTROL OPERATOR STATUS pin 1 (SBY OP1) pin 2 (SBY OP2) pin 3 (SBY OP) OP1 OP1 OP3 Vlow x x Standby x x Vhigh x x Active x x x Vlow x x Standby x x Vhigh x Active x xx Vlow x x Standby xx Vhigh x x Active

TSH110-TSH111-TSH112-TSH113-TSH114 (fig.1) Closed Loop Gain vs. Frequency AV=+1, Rfb=2.2kΩ , Cfb=2pF, RL=100Ω , Vin=100mVp (fig.3) Closed Loop Gain vs. Frequency AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vin=100mVp (fig.5) Closed Loop Gain vs. Frequency AV=+10, Rfb=510Ω , RL=100Ω , Vin=30mVp (fig.2) Closed Loop Gain vs. Frequency AV=-1, Rfb=2.2kΩ , Cfb=2pF, RL=100Ω , Vin=100mVp (fig.4) Closed Loop Gain vs. Frequency AV=-2, Rfb=680kΩ , Cfb=2pF, RL=100Ω , Vin=100mVp (fig.6) Closed Loop Gain vs. Frequency AV=-10, Rfb=510Ω , RL=100Ω , Vin=30mVp 1 10 100 -10 -120 -100 -80 -60 -40 -20 Vcc=±6V Vcc=±2.5V Vcc=±6V Vcc=±2.5V gain(dB)- AV Frequency (MHz) phase gain Phase (°) 11 0 1 0 0 -120 -100 -80 -60 -40 -20 phase gain Vcc=±6V Vcc=±2.5V Vcc=±6V Vcc=±2.5V gain(dB)- AV Frequency (MHz) Phase (°) 1 10 100 -120 -100 -80 -60 -40 -20 phase gain Vcc=±6V Vcc=±2.5V Vcc=±6V Vcc=±2.5V gain(dB)- AV Frequency (MHz) Phase (°) 1 10 100 -10 -300 -280 -260 -240 -220 -200 -180 -160 -140 Vcc=±6V Vcc=±2.5V Vcc=±6V Vcc=±2.5V gain(dB) Frequency (MHz) Phase (°) 11 0 1 0 0 -300 -280 -260 -240 -220 -200 -180 -160 -140 phase gain Vcc=±6V Vcc=±2.5V Vcc=±6V Vcc=±2.5V gain(dB)- AV Frequency (MHz) Phase (°) 11 0 1 0 0 -300 -280 -260 -240 -220 -200 -180 -160 -140 phase gain Vcc=±6V Vcc=±2.5V Vcc=±2.5V Vcc=±6V gain(dB)- AV Frequency (MHz) Phase (°)

TSH110-TSH111-TSH112-TSH113-TSH114 (fig.7): Positive Slew Rate AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vcc=±6V (fig.9): Positive Slew Rate AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vcc=±2.5V (fig.11): Input Voltage Noise Level AV=+100, Rfb=1kΩ , Input+ connected to Gnd via 10Ω (fig.8): Negative Slew Rate AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vcc=±6V (fig.10): Negative Slew Rate AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vcc=±2.5V (fig.12): Vio vs. Power Supply Open loop, no load 5ns /div. 1V /div. 5ns /div. 1V /div. 5ns /div. 0.4V /div. 5ns /div. 0.4V /div. 100 1k 10k 100k 1M Voltage Noise (nV/√Hz) Frequency (Hz) 5ns /div. 1V /div. 5ns /div. 1V /div. 5ns /div. 0.4V /div. 5ns /div. 0.4V /div. 56789 1 0 1 1 1 2 200 300 400 500 600 700 800 900 1000 Vio (µV) Vcc (V)

TSH110-TSH111-TSH112-TSH113-TSH114 (fig.13): Icc(-) vs. Power Supply Open loop, no load (fig.15): Iib(-) vs. Power Supply Open loop, no load (fig.17): Vol vs. Power Supply Open loop, RL=100Ω (fig.14): Icc(+) vs. Power Supply Open loop, no load (fig.16): Iib(+) vs. Power Supply Open loop, no load (fig.18): Voh vs. Power Supply Open loop, RL=100Ω 56789 1 0 1 1 1 2 -3.9 -3.8 -3.7 -3.6 -3.5 -3.4 -3.3 Icc(-) (mA) V cc (V) 56789 1 0 1 1 1 2 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Iib(-) (mA) V cc (V) 56789 1 0 1 1 1 2 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 Vol (V) Vcc (V) 56789 1 0 1 1 1 2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Icc(+) (mA) V cc (V) 56789 1 0 1 1 1 2 0.0 0.2 0.4 0.6 0.8 1.0 Iib(+) (mA) V cc (V) 56789 1 0 1 1 1 2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Voh (V) V cc (V)

TSH110-TSH111-TSH112-TSH113-TSH114 (fig.19): Icc vs. Temperature Open loop, no load (fig.21): ROL vs. Temperature Open loop, no load (fig.23): VOH & VOL vs. Temperature Open loop, RL=100Ω (fig.20): Icc (Standby) vs. Temperaure Open loop, no load (fig.22): CMR vs. Temperature Open loop, no load (fig.24): Slew Rate vs. Temperature AV=+2, RL=100Ω -40 -20 0 20 40 60 80 100 Icc(-) for Vcc=±6V Icc(-) for Vcc=±2.5V Icc(+) for Vcc=±2.5V Icc(+) for Vcc=±6V Icc (mA) Temperature (°C) - 4 0 - 2 00 2 04 06 08 0 1 0 0 800 850 900 950 1000 Vcc=±2.5V Vcc=±6V R OL (kΩ ) Temperature (°C) -40 -20 0 20 40 60 80 100 VOH for Vcc=±6V V OH for Vcc=±2.5V V OL for Vcc=±6V V OL for Vcc=±2.5V VOH and VOL (V) Temperature (°C) - 4 0 - 2 00 2 04 06 08 0 1 0 0 -30 -20 -10 IccStand-By (µA) Temperature (°C) -40 -20 0 20 40 60 80 100 Vcc=±2.5V Vcc=±6V CMR (dB) Temperature (°C) - 4 0 - 2 0 0 2 04 06 08 0 1 0 0 100 150 200 250 300 350 400 450 500 550 600 neg. SR for Vcc=±6V pos. SR for Vcc=±6V pos. SR for Vcc=±2.5V neg. SR for Vcc=±2.5V Slew Rate (V/µs) Temperature (°C)

TSH110-TSH111-TSH112-TSH113-TSH114 (fig.25): Group Delay AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω (fig.27): Frequency Response vs. Load AV=+2, Rfb=680Ω , Cfb=2pF, VCC =±2.5V, (fig.29) (fig.29): Capacitive Load Schematic. measurements on (fig.27) and (fig.28) (fig.26): Gain Flatness AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω (fig.28): Frequency Response vs. Load AV=+2, Rfb=680Ω , Cfb=2pF, VCC =±6V, (fig.29) 0.1 1 10 100 Vcc=±6V Vcc=±2.5V Delay Time (ns) Frequency (MHz) 1 10 100 C=30pF Rs=39 C=100pF Rs=12 C=1nF Rs=5 Gain(dB) - AV Frequency (MHz) R G 680Ω 1kΩ OUT R s(Ω ) R fb, 680Ω C fb 2pF TSH11x C R G 680Ω 1kΩ OUT R s(Ω ) R fb, 680Ω C fb 2pF TSH11x C 1k 10k 100k 1M 10M 100M 5.90 5.95 6.00 6.05 6.10 6.15 6.20 6.25 6.30 Vcc=±6V Vcc=±2.5V Gain Flatness (dB) Frequency (Hz) 11 0 1 0 0 C=30pF Rs=30 C=100pF Rs=12 C=1nF Rs=6 Gain(dB) - AV Frequency (MHz)

TSH110-TSH111-TSH112-TSH113-TSH114 Intermodulation Distortion A non-ideal output of the amplifier can be de- scribed by the following development : Vout=C 0+C 1(Vin)+C2(Vin)2+C 3(Vin)3+...+Cn(Vin)n due to a non-linearity in the input-output amplitude transfert. In the case of Vin=Asinω t, CO is the DC component, C1(Vin) is the fundamental, CnAn is the amplitude of the harmonics. A one-frequency or one-tone input signal contrib- utes to a harmonic distortion. A two-tones input signal contributes to a harmonic distortion and in- termodulation product. This intermodulation product or intermodulation distortion of a two-tones input signal is the first step of the amplifier study for driving capability in the case of a multitone signal. In this case V in=Asinω 1t+Bsinω 2t, and : Vout= C O +C 1(Asinω 1t+Bsinω 2t) C 2(Asinω 1t+Bsinω 2t)2+C 3(Asinω 1t+Bsinω 2t)3 ...Cn(Vin)n Vout= C O +C 1(Asinω 1t+Bsinω 2t) C 2(A2+B 2)/2-(C2/2)(A2cos2ω 1t+B2cos2ω 2t) 2C 2AB(cos(ω 1-ω 2)t-cos(ω 1+ω 2)t) (3C3/4) (A3sinω 1t+B3sinω 2t+2A2Bsinω 2t+2B2Asinω 1t) (C3A3sin3ω 1t+B3sin3ω 2t) (3C3A2B/2)(sin(2ω 1-ω 2)t-1/2sin(2ω 1+ω 2)t) (3C3B2A/2)(sin(−ω 1+2ω 2)t-1/2sin(ω 1+2ω 2)t) ...C n(Vin)n In this expression, we can recognize the second order intermodulation IM2 by the frequencies 1-ω 2) and (ω 1+ω 2) and the third order intermod- ulation IM3 by the frequencies (2ω 1-ω 2), (2ω 1+ω 2), (−ω 1+2ω 2) and (ω 1+2ω 2). The following graphs show the IM3 of the amplifier in two cases as a function of the output amplitude. The two-tones input signal is achieved by the mul- tisource generator Marconi 2026. Each tone has the same amplitude. The measurement is achieved by the spectrum analyser HP 3585A. Both instruments are phase locked to enhance measurement precision. (fig.30): 3 rd Order Intermodulation (180kHz & 280kHz) AV=+4, Rfb=680Ω , no Cfb, RL=100Ω , Vcc=±6V (fig.31): 3rd Order Intermodulation (1MHz & 1.1MHz) AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vcc=±2.5V 012345 -100 -95 -90 -85 -80 -75 -70 -65 -60 640kHz 80kHz 380kHz 740kHz IM3 (dBc) Output Amplitude (Vpeak ) -100 -95 -90 -85 -80 -75 -70 -65 -60 900kHz 1.2MHz 3.1MHz 3.2MHz IM3 (dBc) Output Amplitude (Vpeak )

TSH110-TSH111-TSH112-TSH113-TSH114 Printed Circuit Board Layout Considerations In this range of frequency, printed circuit board parasitics can affect the closed-loop performance. The implementation of a proper ground plane in both sides of the PCB is mandatory to provide low inductance and low resistance common return. Most important for controlling the gain flatness and the bandwidth are stray capacitances at the output and inverting input. For minimizing the cou- pling, the space between signal lines and ground plane will be increased. Connections of the feed- back components must be as short as possible on order to decrease the associated inductance which affect high frequency gain errors. It is very important to choose external components as small as possible such as surface mounted devices, SMD, in order to minimize the size of all the dc and ac connections. Power Supply Bypassing A proper power supply bypassing comes very im- portant for optimizing the performance in high fre- quency range. Bypass capacitors must be placed as close as possible to the IC pins to improve high frequency bypassing. A capacitor greater than 1µF is necessary to minimize the distortion. For a better quality bypassing a capacitor of 0.1µF will be added following the same condition of imple- mentation. These bypass capacitors must be in- corporated for the negative and the positive sup- plies. (fig.32): Circuit for power supply bypassing. Channel Separation or Crosstalk The following figure show the crosstalk from an amplifier to a second amplifier. This phenomenon, accented in high frequencies, is unavoidable and intrinsic of the circuit. Nevertheless, the PCB layout has also an effect on the crosstalk level. Capacitive coupling be- tween signal wires, distance between critical sig- nal nodes, power supply bypassing, are the most significant points. (fig.33): Crosstalk vs. Frequency. AV=+2, Rfb=680Ω , Cfb=2pF, RL=100Ω , Vcc=±6V, ±2.5V Single Power Supply The TSH11x operates from 12V down to 5V power supplies. This is achieved with a dual power sup- ply of ±6V and ±2.5V or a single power supply of 12V and 5V referenced to the ground. In the case of this asymmetrical supplying, a biasing is neces- sary to assume a positive output dynamic range between 0V and +Vcc supply rails. Considering the values of V OH and VOL , the amplifier will pro- vide an ouput dynamic from +1.35V to 10.75V for a 12V supplying, from 0.6V to 4.5V for a 5V sup- plying. The following figure show the case of a 5V single power supply configuration. (fig.34): Circuit for +5V single supply. -VCC 0.1µF 1µF +V CC 1µF 0.1µF TSH11x -VCC 0.1µF 1µF +V CC 1µF 0.1µF TSH11x 10k 100k 1M 10M 100M -100 -80 -60 -40 -20 X-Talk (dB) Frequency (Hz) 5kΩ R G 680Ω IN +5V 50Ω OUT 50Ω R fb, 680Ω 10µF + 1µF C fb 2pF TSH11x 100µF 5kΩ +5V 10nF Rin 1kΩ C G 5kΩ R G 680Ω IN +5V 50Ω OUT 50Ω R fb, 680Ω 10µF + 1µF C fb 2pF TSH11x 100µF 5kΩ +5V 10nF Rin 1kΩ C G

TSH110-TSH111-TSH112-TSH113-TSH114 The amplifier must be biased with a mid supply (nominaly +Vcc/2), in order to maintain the DC component of the signal at this value. Several op- tions are possible to provide this bias supply (such as a virtual ground using an operational amplifier), or a two-resistance divider which is the cheapest solution. A high resistance value is required to lim- it the current consumption. On the other hand, the current must be high enough to bias the non-in- verting input of the amplifier. If we consider this bias current (5µA) as the 1% of the current through the resistance divider (500µA) to keep a stable mid supply, two 5kΩ resistances can be used. The input provides a high pass filter with a break frequency below 10Hz which is necessary to re- move the original 0 volt DC component of the input signal, and to hold it at 2.5V. Video Multiplexing using the TSH113 (fig.35): Circuit for switching 3 video signals with the tri- ple TSH113. Assuming a low level active onto the disable pins (1,2,3) as described on page 7 of the datasheet, any operator can be disable/enable independent- ly. The two disabled operators will be in standby mode featuring a high ouput impedance with a high input/output isolation and a low quiescent current. (fig.36): Typical output response in standby mode on/off (fig.37): Typical output response in standby mode off/on R G 680Ω IN1 R fb, 680Ω C fb, 2pF TSH113 R G 680Ω IN2 75Ω Common OUT75Ω R fb, 680Ω C fb, 2pF TSH113 R G 680Ω IN3 R fb, 680Ω C fb, 2pF TSH113 75Ω cable ENABLE1 ENABLE2 ENABLE3 R G 680Ω IN1 R fb, 680Ω C fb, 2pF TSH113 R G 680Ω IN2 75Ω Common OUT75Ω R fb, 680Ω C fb, 2pF TSH113 R G 680Ω IN3 R fb, 680Ω C fb, 2pF TSH113 75Ω cable ENABLE1 ENABLE2 ENABLE3 100ns /div. 0.4V /div. Disabled Output Standby Signal +2.4V -2.4V Enabled Output 100ns /div. 0.4V /div. Disabled Output Standby Signal +2.4V -2.4V Enabled Output 10µs /div. 0.4V /div. Standby Signal +2.4V -2.4V Disabled Output Enabled Output 10µs /div. 0.4V /div. Standby Signal +2.4V -2.4V Disabled Output Enabled Output

TSH110-TSH111-TSH112-TSH113-TSH114 (fig.38): Input / Output Isolation vs. Frequency.. Choice of the Feedback Circuit The TSH11x is a serie of current feedback amplifiers. For a current feedback structure the bandwidth depends on the value of the feedback components and the value of supply voltage. A good choice of these components is necessary to achieve the gain flatness and the stability. The following table shows the typical -3dB bandwidth and 0.1dB bandwidth assuming different gains and power supply on 100Ω load. Please see also the Closed Loop Gain vs. Frequency curves on page 8 of the datasheet. (fig.39): Non-inverting and Inverting Implementation.. (tab.1): Closed-loop Gain and Feedback Components. Inverting Amplifier Biasing In this case a resistance (R on fig.40) is necessary to achieve a good input biasing. This resistance is calculated by assuming the negative and positive input bias current. The aim is to make the compensation of the offset bias current which could affect the input offset voltage and the output DC component. Assuming Ib-, Ib+, R in, Rfb and a zero volt output, the resistance R comes : R = Rin // Rfb . (fig.40): Compensation of the Input Bias Current.. 0.01 0.1 1 10 100 -120 -100 -80 -60 -40 -20 Standby mode Input/output Isolation (dB) Frequency (MHz) R G 50Ω Output 49.9Ω R fb C fb Input Non-Inverting Gain = 1+ Rfb / R G R 50Ω Output 49.9Ω R fb C fb Inverting Gain = - Rfb / R inR inInput R G 50Ω Output 49.9Ω R fb C fb Input Non-Inverting Gain = 1+ Rfb / R G R 50Ω Output 49.9Ω R fb C fb Inverting Gain = - Rfb / R inR inInput VCC (V) Gain R fb (Ω ) C fb (pF) -3dB Bw (MHz) 0.1dB Bw (MHz) +10 510 - 46 14 -10 510 - 42 13 +2 680 2 105 50 -2 680 2 90 40 +1 2.2k 2 170 30 -1 2.2k 2 110 20 ±2.5 +10 510 - 37 13 -10 510 - 36 12 +2 680 2 93 25 -2 680 2 86 30 +1 2.2k 2 130 50 -1 2.2k 2 100 18 R Load Output R fb R inIb- Ib+ Vcc+ Vcc- R Load Output R fb R inIb- Ib+ Vcc+ Vcc-

TSH110-TSH111-TSH112-TSH113-TSH114 PACKAGE MECHANICAL DATA

8 PINS - PLASTIC MICROPACKAGE (SO)

8 PINS - THIN SHRINK SMALL OUTLINE

PACKAGE (TSSOP) Dim. Millimeters Inches A 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45° (typ.) D 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.150 0.157 L 0.4 1.27 0.016 0.050 M 0.6 0.024 S 8° (max.) Dim. Millimeters Inches A 1.20 0.05 A1 0.05 0.15 0.01 0.006 b 0.19 0.30 0.007 0.15 c 0.09 0.20 0.003 0.012 E 6.40 0.252 e 0.65 0.025 k0 ° 8 ° 0 ° 8 ° 0,25 mm .010 inch GAGE PLANE Caaa C PLANE SEATING EA D b e L k c 8 5 PIN 1 IDENTIFICATION

TSH110-TSH111-TSH112-TSH113-TSH114 PACKAGE MECHANICAL DATA

14 PINS - PLASTIC MICROPACKAGE (SO)

14 PINS - THIN SHRINK SMALL OUTLINE

PACKAGE (TSSOP) Dim. Millimeters Inches A 1.75 0.069 a1 0.1 0.2 0.004 0.008 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D (1) 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F (1) 3.8 4.0 0.150 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.020 0.050 M 0.68 0.027 S 8° (max.) Note : (1) D and F do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA BOOK. D M F 1 7 b e E LG C c1 A b1s Dim. Millimeters Inches A 1.20 0.05 A1 0.05 0.15 0.01 0.006 b 0.19 0.30 0.007 0.15 c 0.09 0.20 0.003 0.012 E 6.40 0.252 e 0.65 0.025 k0 ° 8 ° 0 ° 8 ° c k L E e b D PIN 1 IDENTIFICATION SEATING PLANE C aaa C 0,25 mm .010 inch GAGE PLANE A

TSH110-TSH111-TSH112-TSH113-TSH114 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © http://www.st.com PACKAGE MECHANICAL DATA

5 PINS - TINY PACKAGE (SOT23)

Dim. Millimeters Inches A1 0 0.15 0.006 D1 1.90 0.075 e 0.95 0.037 K 0d 10d 0d 10d L C A b E D