TSF10N70C THINKISEMI | Alldatasheet

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R DS(on) (Max 1.20 Ω )@V GS =10V Gate Charge (Typical 45nC) Improved dv/dt Capability High ruggedness 100% Avalanche Tested R DS(ON) = 1.2 ohm I D = 10A BV DSS = 700V 2. Drain 3. Source 1. Gate TSF10N70C Pb Free Plating Product TSF10N70C Pb 10A,700V Insulated N-Channel Type Power MOSFET General Description This N-channel enhancement mode field-effect power transistor using THINKI Semiconductor advanced planar stripe, DMOS technol- ogy intended for off-line switch mode power supply. Also, especially designed to minimize rds(on) and high rugged avalanche characteristics. The TO-220F pkg is well suited for adaptor power unit and small power inverter application. 1 2 3 TO-220F © 2006 Thinki Semiconductor Co., Ltd. http://www.thinkisemi.com/ Page 1/4Rev.05 „ ABSOLUTE MAXIMUM RATINGS C = 25°C unless otherwise specified) PARAMETER SYMBOL RATINGS UNIT Drain-Source Voltage V DSS 700 V Gate-Source Voltage V GSS ±30 V Avalanche Current (Note 2) I AR 10 A Drain Current Continuous I D 10 A Pulsed (Note 2) I DM 40 A Avalanche Energy Single Pulsed (Note 3) E AS 700 mJ Repetitive (Note 2) E AR 15.6 mJ Peak Diode Recovery dv/dt (Note 4) dv/dt 4.5 V/ns Power Dissipation P D 50 W Junction Temperature T J +150 °C Operating Temperature T OPR -55 ~ +150 °C Storage Temperature T STG -55 ~ +150 °C Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. 2. Repetitive Rating: Pulse width lim ited by maximum junction temperature 3. L = 14.2mH, I AS = 10A, V DD = 50V, R G = 25 Ω Starting T J = 25°C 4. I SD ≤ 9.5A, di/dt ≤200A/μs, V DD ≤BV DSS , Starting T J = 25°C „ THERMAL DATA PARAMETER SYMBOL RATING UNIT Junction to Ambient θ JA 62.5 °C/W Junction to Case θ JC 2.5 °C/W

„ ELECTRICAL CHARACTERISTICS ( T C =25°C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT OFF CHARACTERISTICS Drain-Source Breakdown Voltage BV DSS V GS = 0V, I D = 250μA 700 V Drain-Source Leakage Current I DSS V DS = 700V, V GS = 0V 10 µA Gate-Source Leakage Current Forward I GSS V GS = 30 V, V DS = 0 V 100 nA Reverse V GS = -30 V, V DS = 0 V -100 nA Breakdown Voltage Temperature Coefficient ΔBV DSS /ΔT J I D = 250 µA, Referenced to 25°C 0.7 V/°C ON CHARACTERISTICS Gate Threshold Voltage V GS TH V DS = V GS , I D = 250μA 2.0 4.0 V Static Drain-Source On-State Resistance R DS ON V GS = 10V, I D = 5A 0.9 1.2 Ω DYNAMIC CHARACTERISTICS Input Capacitance C ISS V DS =25V, V GS =0V, f=1.0 MHz 1570 2040 pF Output Capacitance C OSS 166 215 pF Reverse Transfer Capacitance C RSS 18 24 pF SWITCHING CHARACTERISTICS Turn-On Delay Time t D ON V DD =350V, I D =10A, R G =25Ω (Note 1, 2) 23 55 ns Turn-On Rise Time t R 69 150 ns Turn-Off Delay Time t D OFF 144 300 ns Turn-Off Fall Time t F 77 165 ns Total Gate Charge Q G V DS =560V, I D =10A, V GS =10 V (Note 1, 2) 44 57 nC Gate-Source Charge Q GS 6.7 nC Gate-Drain Charge Q GD 18.5 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS Drain-Source Diode Forward Voltage V SD V GS = 0 V, I S =10A 1.4 V Maximum Continuous Drain-Source Diode Forward Current I S 10 A Maximum Pulsed Drain-Source Diode Forward Current I SM 40 A Reverse Recovery Time t r r V GS = 0 V, I S = 10A, dI F / dt = 100 A/µs (Note 1) 420 ns Reverse Recovery Charge Q RR 4.2 µC Notes: 1. Pulse Test : Pulse width ≤300µs, Duty cycle ≤2% 2. Essentially independent of operating temperature TSF10N70C © 2006 Thinki Semiconductor Co., Ltd. http://www.thinkisemi.com/ Page 2/4Rev.05

TEST CIRCUITS AND WAVEFORMS Peak Diode Recovery dv/dt Test Circuit P. W. Period D=V GS (Driver) I SD (D.U.T.) I FM , Body Diode Forward Current di/dt I RM Body Diode Reverse Current Body Diode Recovery dv/dt Body Diode Forward Voltage Drop V DD 10V V DS (D.U.T.) V GS P.W. Period Peak Diode Recovery dv/dt Waveforms © 2006 Thinki Semiconductor Co., Ltd. http://www.thinkisemi.com/ Page 3/4Rev.05

„ TEST CIRCUITS AND WAVEFORMS (Cont.) Switching Test Circuit Switching Waveforms Gate Charge Test Circuit Gate Charge Waveform D.U.T. R D 10V V DS L V DD t p V DD t p Time BV DSS I AS I D(t) V DS(t) Unclamped Inductive Switching Test Circuit Unclamped Inductive Switching Waveforms © 2006 Thinki Semiconductor Co., Ltd. http://www.thinkisemi.com/ Page 4/4Rev.05