TSE2004GB2C0

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▪ Compliant to JEDEC TSE2004av Device Specification (JEDEC Standard No. 21-C, Section 4.1.6) ▪ Temperature Sensor plus a 512-byte Serial EEPROM ▪ A 512-byte Serial EEPROM for SPD ▪ Single supply: 2.2V to 3.6V ▪ Accurate timeout support that meets strict SMBus specifications for: 25ms (minimum), 35ms (maximum) ▪ Timeout supported for Temperature Sensor and EEPROM ▪ Timeout supported in all modes:

• Active mode for Temperature Sensor and EEPROM
• EEPROM in standby or Temperature Sensor in shutdown
• EEPROM in standby and Temperature Sensor in shutdown ▪ Schmitt trigger and noise filtering on bus inputs ▪ A 2-wire serial interface: 10kHz to 1MHz (maximum) I 2C™/ SMBus™ ▪ Available package: 8-DFN, 2.0  3.0  0.75 mm Temperature Sensor Features ▪ Temperature converted to digital data ▪ Sampling rate of 125ms (maximum) ▪ Selectable 0, 1.5°C, 3°C, 6°C Hysteresis ▪ Programmable resolution from 0.0625°C to 0.5°C ▪ Accuracy:
• 0.5°C / ±1.0°C (typ./max.) from +75°C to +95°C
• ±1.0°C / ±2.0°C (typ./max.) from +40°C to +125°C
• ±2.0°C / ±3.0°C (typ./max.) from -40°C to +125°C Serial EEPROM Features ▪ Individual Reversible Software Data Protection for all 128-byte blocks ▪ Byte and page (up to 16 bytes) Write operation ▪ Self-time Write cycle ▪ Automatic address incrementing ▪ Random and sequential Read modesChipset MCH CPU Memory Module Memory Bus Temperature sensor and EEPROM DRAMs DRAMs SMBus EVENT# (for memory throttling) EVENT_n TSE2004GB2C0 Datasheet DDR4 Temperature Sensor with Integrated 4Kbit EEPROM for Memory Module

3©2018 Integrated Device Technology, Inc. May 10, 2018 TSE2004GB2C0 Datasheet Block Diagram Temperature Registers TUPPDER TLOWER TCRIT Resolution Capability and ID Registers Temperature Range Accuracy Event Feature Resolution Support Manufacturer ID Device ID Configuration Registers Resolution Hysteresis Event Status Event Polarity Event Mode Critical Event Only Clear Event Shutdown Output Control Temperature Sensor up to 0.5° accuracy ADC Control Logic SMBus/ I2C Interface 4kB EEPROM with Write Protect SCL SDA EVENT_n GND VDD

Figure 2. Pin Assignments for 2 x 3 mm 8-DFN Package – Top View in the i 2C Bus chain (to calculate the value of the pull-up resistor, see Figure 3). Table 1. Pin Descriptions[a] e and the temperature sensor.

1 SA0 Select Address 0

2 SA1 Select Address 1

3 SA2 Select Address 2

5 SDA Serial Data In

6 SCL Serial Clock In

7 EVENT_n Temperature Event Out

Figure 3. Maximum RL Value vs. Bus Capacitance (CBUS) for an I2C Bus decoding details (see Table 9). current out-of-limit conditions. These modes are Interrupt, Comparator, or TCRIT Only . value to Write is independent of the EVENT_n polarity bit. temperature is compared against the TCRIT limit, then this mode is always used. operation of the different modes over time and temperature are illustrated ( Figure 4 ). through the pull-up resistor.

Figure 4. EVENT_n Pin Mode Functionality page is comprised of two 128-byte blocks. The device is able to selectively lock the data in any or all of the four 128-byte bl ocks. elimination of the Permanent Write Protect feature are documented. four blocks is cleared simultaneously, and Write protection may be reasserted after being cleared. and can be configured to operate as an interrupt or as a comparator output.

Figure 5. Device Diagram specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability . Table 2. Absolute Maximum Ratings Table 3. Operating Conditions Table 4. AC Measurement Conditions

Figure 6. AC Measurement I/O Waveform Table 5. Input Parameters [b] Verified by design and characterization, not necessarily tested on all devices.

Table 6. DC Characteristics

Table 7. AC Characteristics[a] [a] TSE devices are not required to support the I 2C Bus ALERT function. [b] 400kHz timing defined for compatibility with TSE2002av applications. [c] The TSE2004GB2C0 does not initiate clock stretching, which is an optional SMBus feature. [d] The TSE2004GB2C0 supports bus time-out on EE access. than tTIMEOUT,MAX . Typical device examples include the host controller, an embe dded controller, and most devices that can master the SMBus. a stop condition. A timeout condition can only be ensured if, the device that is forcing the timeout holds SCL low for t IMEOUT,MAX or longer. [f] Guaranteed by design and characterization at 50°C, 3.6V. Not tested on all devices. [g] To avoid spurious START and STOP condit ions, a minimum delay is plac ed between the fall ing edge of SCL an d the falling or ri sing edge of SDA. [h] For a re-START condition, or following a write cycle.

The TSE2004GB2C0 functions as a slave device in the I 2C Bus protocol with all memory operations synchronized by the serial clock. is an optional I 2C Bus feature. SWPn, RSPn, or CSWP operations, a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011). or VSSSPD, and the Logical Serial Address (LSA) is equal to the code on the Serial Address pins. Table 9. I2C Bus Addressing Modes[a]

transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Bus Master generated STOP condition after an Ack for WRITE, and after a NoAck for READ. Violations of the command protocol result in an unpredictable operation. and received, starting first with the Most Significant Bit. Figure 9. I2C Bus Protocol

14©2018 Integrated Device Technology, Inc. May 10, 2018 TSE2004GB2C0 Datasheet Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition mu st precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA), while Serial Clock (SCL) is stable and driven High. A Stop condition term inates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop conditi on to force the SPD into Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle for the SPD. Neither of these conditions changes the operation of the TS section. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be the bus master or the sl ave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. No Acknowledge Bit (NACK) The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus master releases Serial Data (SDA) after sending eight bits of data and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.

master sends the Device Select Code ( Table 10 ) on Serial Data (SDA) most significant bit first). Sensor settings is 0011b. Additionally, writing or clearing the reversible EE write protect requires SA0 be raised to the VHV v oltage level. only responds if the Select Address is the same as the Logical Serial Address. Table 10. Device Select Code[a][b] [a] Permanent Write Protect features for the TSE2002av has been eliminated from the TSE2004GB2C0. [b] Don’t Care values for word address and data fields following commands may result in Ack or No_Ack responses. [c] For commands, SWPn, CWP, RPSn, SPAn, RPA ( Figure 9 ). [d] The most significant bit, b7, is sent first. [e] Logical Serial Addresses (LSA) are generated by the combination of inputs on the SA pins ( Table 9). [f] For backward compatibility with previous de vices, the order of block se lect bits (b3 and b1) are not a simple binary encodin g of the block number. [g] SA0 pin is driven to 0 = VSSSPD, 1 = VDDSPD, or VHV. EEPROM. Subsequent Read EE or Write EE commands oper ate on the sele cted EE page. [i] Reading the EE page address results in Ack, when the current page is 0, and NoAck, when the current page is 1.

external device programmers rather than in-system applications. The eighth bit is the Read/Write bit (R/W_n). This bit is set to 1 for Read, and 0 for Write operations. mode. The I 2C Bus operating modes are shown in Table 11 . a Write instruction, until the completion of the internal Write cycle (t W). Figure 10. Device Reset and Initialization Table 11. I2C Bus Operating Modes

16 START, Device Select, R/W_n = 0, data, STOP

cold power-on reset timing when restoring power. The device is delivered with all bits in the EEPROM memory array when set to 1 (each byte contains 0xFF). The TSE2004GB2C0 has three software commands for setting, clearing, or interrogating the Write-protection status.

1. SWPn: Set Write Protection for Block n
2. CWP: Clear Write Protection for all Blocks
3. RPSn: Read Protection Status for Block n

single block as specified in the SWPn command, but CWP clears the write protection for all blocks. Figure 11. Protocol for Write Protection Commands SWPn, CWP , RPSn replies to the data byte with an Ack. If the Software Write Protection has been set, the device replies to the data byte with a NoAck.

Figure 12. Write Mode Sequences in a Non-Write Protected Area any requests. Access to the TS portion of the TSE2004GB2C0 is permitted during this period. protected block, the internal address counter is not incremented. device replies with Ack. After the byte is transferred, the internal byte address counter is incremented unless the block is wr ite protected. The bus master terminates the transfer by generating a Stop condition ( Figure 12 ). condition known as “roll-over” occurs. This should be avoided, as data starts to be over-written in an implementation dependent fashion. internal byte address counter is incremented. The transfer is terminated by the bus master generating a Stop condition.

make use of this, a polling sequence can be used by the bus master. ▪ Initial condition: a Write cycle is in progress.

• Step 1: The bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).
• Step 2: If the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the sec ond part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 13. Write Cycle Polling Flowchart Using ACK

incremented each time a byte is read. Figure 14. Read Mode Sequences incremented. The bus master terminates the transfer with a Stop condition ( Figure 14 ), without acknowledging the byte.

address, the address counter 'rolls-over', and the device continues to output data from memory address 0x00. the next valid START condition. This has no effect on the TS operational status. 16-bit registers accessed through block read and write commands ( Write Operations ). Behavior on accesses to invalid register locations is vendor-specific, and may return an Ack or a NoAck. entire write transaction on the bus. Table 12. Acknowledge when Writing Data or Defining Write Protection (R/W_n Bit = 0) Table 13. Acknowledge When Reading the Protection Status (R/W_n Bit = 1)

The register set address is shown in Table 12 . These values also used in the I 2C Bus operations as the “REG_PTR”. Table 14. Device Registers

00 R Capabilities Indicates the functions and capabilities of the temperature

01 R/W Configuration Controls the operation of the temperature monitor 0000

02 R/W High Limit Temperature High Limit 0000

03 R/W Low Limit Temperature Low Limit 0000

04 R/W TCRIT Limit Critical Temperature 0000

05 R Ambient Temperature Current Ambient temperature N/A

06 R Manufacturer ID manufacturer ID 00b3

07 R Device/Revision Device ID and Revision number 2215

08 R/W Vendor Defined Change resolution of temperature sensor 0018

The Capabilities Register indicates the supported features of the temperature sensor. ▪ Bits 15 through Bit 8: RFU – Reserved for future use. These bits will always read 0 and writing to them will have no affect. ▪ Bit 7: EVSD – EVENT_n with shutdown action. Must be 1. may or may not be asserted when exiting shutdown if a pending interrupt has not been cleared. ▪ Bit 6: TMOUT is a bus timeout period for thermal sensor access during normal operation. — 1 (default): Parameter t TIMEOUT is supported within the range of 25ms to 35ms (SMBus compatible). — 1: Defined for compatibility with TS3000 devices. Since all TSE2004av devices are required to support VHV, this bit is not use d. ▪ Bits 4 through 3: TRES[1:0] – Indicates the resolution of the temperature monitor (default = 11), ( Table 16 ). ▪ Bit 2: RANGE – Indicates the supported temperature range. ▪ 0: The temperature monitor clamp values lower than 0°C. ▪ 1 (default): The temperature monitor can read temperatures below 0°C, and sets the sign bit appropriately. ▪ Bit 1: ACC indicates the supported temperature accuracy. monitoring range (40°C to 125°C). ▪ Bit 0: EVENT – Indicates whether the temperature monitor supports interrupt capabilities. — 1 (default): The device supports interrupt capabilities. Table 15. Capabilities Register Table 16. TRES Bit Decode

compatibility, all RFU bits must be programmed as 0. minus the hysteresis in order to be flagged as an interrupt event. Note that hysteresis is also applied to the EVENT_n pin func tionality. When either of the lock bits are set, these bits cannot be altered. ▪ Bit 8: SHDN (Shutdown) – The thermal sensing device and A/D converters are disabled to save power, no events will be generated. mode, the TSE2004GB2C0 still responds to commands normally, however bus timeout may or may not be supported in this mode.

• 0 (default): The temperature monitor is active and converting
• 1: The temperature monitor is disabled and will not generate interrupts or update the temperature data. ▪ Bit 7: TCRIT_LOCK. Locks the TCRIT Limit Register from being updated.
• 0 (default): The TCRIT Limit Register can be updated normally.
• 1: The TCRIT Limit Register is locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal power on reset. ▪ Bit 6: EVENT_LOCK – Locks the High and Low Limit Registers from being updated.
• 0: (default – The High and Low Limit Registers can be updated normally.
• 1: The High and Low Limit Registers are locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal power on reset. ▪ Bit 5: CLEAR – Clears the EVENT_n pin when it has been asserted. This bit is write only and will always read 0.
• 0: does nothing
• 1: The EVENT_n pin is released and will not be asserted until a new interrupt condition occurs. This bit is ignored if the devi ce is operating in Comparator Mode. This bit is self clearing.

Table 17. Configuration Register

01 R/W

Table 18. HYST Bit Decode

▪ Bit 4: EVENT_STS – Indicates if the EVENT_n pin is asserted. This bit is read only.

• 0 (default): The EVENT_n pin is not asserted.
• 1: The EVENT_n pin is being asserted by the device. ▪ Bit 3: EVENT_CTRL – Masks the EVENT_n pin from generating an interrupt. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered.
• 0 (default): The EVENT_n pin is disabled and will not generate interrupts.
• 1: The EVENT_n pin is enabled. ▪ Bit 2: TCRIT_ONLY – Controls whether the EVENT_n pin will be asserted from a high or low out-of-limit condition. When the EVENT_LOCK bit is set, this bit cannot be altered.
• 0 (default): The EVENT_n pin will be asserted if the measured temperature is above the High Limit or below the Low Limit, in addition to, if the temperature is above the TCRIT Limit.
• 1: The EVENT_n pin will only be asserted if the measured temperature is above the TCRIT Limit. ▪ Bit 1: EVENT_POL – Controls the active state of the EVENT_n pin. The EVENT_n pin is driven to this state when it is asserted. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered.
• 0 (default): The EVENT_n pin is active low. The “active” state of the pin will be logical 0.
• 1: The EVENT_n pin is active high. The active state of the pin will be logical 1. ▪ Bit 0: EVENT_MODE – Controls the behavior of the EVENT_n pin. The EVENT_n pin may function in either comparator or interrupt mode. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered.
• 0: The EVENT_n pin will function in comparator mode.
• 1: The EVENT_n pin will function in interrupt mode. Temperature Register Value Definitions Temperatures in the High Limit Register, Low Limit Register, TCRIT Register, and Temperature Data Register are expressed in two 's complement format. Bits B12 through B2 for each of these registers, are defined for all device resolutions as defined in the TR ES field of the Capabilities Register, a 0.25°C minimum granularity is supported in all registers. Examples of valid settings and interpret ation of temperature register bits: The TRES field of the Capabilities Register optionally defines higher resolution devices. For compatibility and simplicity, thi s additional resolution affects only the Temperature Data Register but none of the Limit Registers. When higher resolution devices generate status or EVENT_n pin changes, only bits B12 through B2 are used in the comparison; however, all 11 bits (TRES[1:0] = 10) or all 12 bits (TRES[1:0] = 11) are visible in reads from the Temperature Data Register.

Table 19. Temperature Register Coding Examples

this is detected, bit 2 of all Limit Registers should be programmed to 0 to assure correct operation of the temperature compara tors. device temperature status and thermal EVENTs. For future compatibility, unused bits ‘-’ must be programmed as 0. then this register becomes read-only. this register becomes read-only. Table 20. High Limit Register

02 R/W

Table 21. Low Limit Register

03 R/W

Table 22. TCRIT Limit Register

04 R/W

indicating which error conditions, if any, are active. The encoding of bits B12 through B0 is the same as for the temperature l imit registers. and will automatically clear once the temperature has dropped below the limit minus the hysteresis. limit. Once set, it will only be cleared when the temperature drops below or equal to the High Limit minus the hysteresis. Limit minus the hysteresis. Once set, it will only be cleared when the temperature meets or exceeds the Low Limit. The Manufacturer ID Register holds the PCI SIG number assigned to the specific manufacturer. byte holds the revision value. Table 23. Temperature Data Register [a] Resolution defined based on value of TRES field of the Capabilities Regist er. Unused/unsup ported bits will read as 0. Table 24. Manufacturer ID Register

06 R/W

Table 25. Device ID/Revision Register

07 R/W

implemented via this register is also reflected in the capability register. EVENT_n on a wire-OR bus, will show the combined results of all devices wired to the EVENT_n signal. 2C Bus”. Line capacitance limitations should be calculated using this assumption. Table 26. Resolution Register

000 T R E S [ 1 ] T R E S [ 0 ] 000

Table 27. Unique Addressing of SPDs in DIMM Applications[a] [a] 0 = V SSSPD, 1 = VDDSPD.

Figure 19. Pull-up Resistor Value

1. When the DIMM is isolated (not inserted on the PCB motherboard)
2. When the DIMM is inserted on the PCB motherboard

specific programming equipment, to modify the protected bytes, and finally to set the write-protection with the SWPn instructio n. commands are fully supported. is the most current data available. Line 1. Line 1 is the truncated part number/ Product Description. Line 2. DCY denotes Produce Description + Y, where Y = last digit of year assembled. ***” denotes sequential lot number characters from AAA to ZZZ.

31©2018 Integrated Device Technology, Inc. May 10, 2018 TSE2004GB2C0 Datasheet

Ordering Information

JEDEC Standard No. 21-C , Release 26, modified February 3, 2016; Section 4.1.6 Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 KBit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications. Orderable Part Number Package Carrier Type Temperature TSE2004GB2C0NCG Tray -40° to +125°C TSE2004GB2C0NCG8 Tape and Reel -40° to +125°C XXXXX XX X Rev.Voltage Shipping

8 Tape and Reel

X Device Type 2004G Temperature Sensor with EEPROM X Temp B Temperature Accuracy Grade Carrier TSE Range 2 = (2.2V to 3.6V) XXX Package NCG - Green DFN

DISCLAIMER Integrated Device Te chnology, Inc. (IDT) and its aff iliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specific ations described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of IDT's products for any particular purpose, an implied warran ty of merchantability, or non-infringement of the intellectual p roperty rights of others. This documen t is presented only as a guide and does not convey any license under intellectual propert y rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other c ountries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

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San Jose, CA 95138 USA www.IDT.com 32©2018 Integrated Device Technology, Inc. May 10, 2018 TSE2004GB2C0 Datasheet

Revision History

Revision Date Description of Change May 10, 2018 ▪ Updated t SP symbol in Table 5 ▪ Removed several functions from Table 10 ▪ Updated the Package Outline Drawings ; however, no technical changes ▪ Completed other minor changes October 23, 2017 Updated the operating temperature values in Ordering Information September 14, 2017 ▪ Added reference to JEDEC compliancy in Features ▪ Updated the package outline drawings; however, no mechanical changes ▪ Completed numerous minor changes May 15, 2017 Table 25 - corrected units for I LI, ILO, IDD1 rows. May 2, 2017 Initial release.

© Integrated Device Technology, Inc. NCG8P1, PSC-4244-01, Rev 01, Page 1

© Integrated Device Technology, Inc. NCG8P1, PSC-4244-01, Rev 01, Page 2 Package Revision History Rev No.Date Created Description April 25, 2018 Rev 00 Initial Release, "VFQFPN Rename to DFN" June 26, 2018 Rev 01 Add Component Outline for Foot Print in Green

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