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▪ Temperature Sensor plus a 512 byte Serial EEPROM ▪ A 512 byte Serial EEPROM for SPD ▪ Single supply: 2.2V to 3.6V ▪ Accurate timeout support: — Meets strict SMBus specifications for: 25ms (minimum), 35ms (maximum) ▪ Timeout supported for Temperature Sensor and EEPROM ▪ Timeout supported in all modes: — Active mode for Temperature Sensor and EEPROM — EEPROM in standby, or Temperature Sensor in shutdown — EEPROM in standby, and Temperature Sensor in shutdown ▪ Schmitt trigger and noise filtering on bus inputs ▪ A 2-wire serial interface: 10kHz to 1MHz (maximum) I2C™/ SMBus™ ▪ Available package: TDFN-8 Temperature Sensor Features ▪ Temperature converted to digital data ▪ Sampling rate of 125ms (maximum) ▪ Selectable 0, 1.5°C, 3°C, 6°C hysteresis ▪ Programmable resolution from 0.0625°C to 0.5°C ▪ Accuracy: — 0.5°C/ ±1.0°C (typ./ max.) from +75°C to +95°C — ±1.0°C/ ±2.0°C (typ./ max.) from +40°C to +125°C — ±2.0°C/ ±3.0°C (typ./max.) from -40°C to +125°C Serial EEPROM Features ▪ Individual Reversible Software Data Protection for all 128 byte blocks ▪ Byte and page (up to 16 bytes) Write operation ▪ Self-time Write cycle ▪ Automatic address incrementing ▪ Random and sequential Read modes ▪ Industrial temperature monitors ▪ Hard disk drives and other PC peripherals Chipset MCH CPU Memory Module Memory Bus Temperature sensor and EEPROM DRAMs DRAMs SMBus EVENT# (for memory throttling) EVENT_n TSE2004GB2C0 Datasheet DDR4 Temperature Sensor with Integrated 4Kbit EEPROM for Memory Module
2©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet Block Diagram Temperature Registers TUPPDER TLOWER TCRIT Resolution Capability and ID Registers Temperature Range Accuracy Event Feature Resolution Support Manufacturer ID Device ID Configuration Registers Resolution Hysteresis Event Status Event Polarity Event Mode Critical Event Only Clear Event Shutdown Output Control Temperature Sensor up to 0.5° accuracy ADC Control Logic SMBus/ I2C Interface 4kB EEPROM with Write Protect SCL SDA EVENT_n GND VDD
Figure 2. Pin Assignments for 2 x 3 mm 8-TDFN Package – Top View Table 1. Pin Descriptions[a] between the DIMM PCB plane and the temperature sensor.
1 SA0 Select Address 0
2 SA1 Select Address 1
3 SA2 Select Address 2
5 SDA Serial Data In
6 SCL Serial Clock In
7 EVENT_n Temperature Event Out
in the i 2C Bus chain (to calculate the value of the pull-up resistor, see Figure 3 ). Figure 3. Maximum RL Value vs. Bus Capacitance (CBUS) for an I2C Bus decoding details (see Table 2).
current out-of-limit conditions. These modes are Interrupt, Comparator, or TCRIT Only . value to Write is independent of the EVENT_n polarity bit. temperature is compared against the TCRIT limit, then this mode is always used. operation of the different modes over time and temperature are illustrated ( Figure 4 ). through the pull-up resistor. Figure 4. EVENT_n Pin Mode Functionality
page is comprised of two 128 byte blocks. The device is able to selectively lock the data in any or all of the four 128-byte bl ocks. elimination of the Permanent Write Protect feature are documented. four blocks is cleared simultaneously, and Write protection may be reasserted after being cleared. and can be configured to operate as an interrupt or as a comparator output. Figure 5. Device Diagram
The TSE2004GB2C0 functions as a slave device in the I 2C Bus protocol with all memory operations synchronized by the serial clock. is an optional I 2C Bus feature. SWPn, RSPn, or CSWP operations, a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011). or VSSSPD, and the Logical Serial Address (LSA) is equal to the code on the Serial Address pins. Table 2. I2C Bus Addressing Modes[a]
transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Bus Master generated STOP condition after an Ack for WRITE, and after a NoAck for READ. Violations of the command protocol result in an unpredictable operation. and received, starting first with the Most Significant Bit. Figure 6. I2C Bus Protocol
9©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition mu st precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA), while Serial Clock (SCL) is stable and driven High. A Stop condition term inates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop conditi on to force the SPD into Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle for the SPD. Neither of these conditions changes the operation of the TS section. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be the bus master or the sl ave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. No Acknowledge Bit (NACK) The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus master releases Serial Data (SDA) after sending eight bits of data and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following, the bus master sends the Device Select Code ( Table 3) on Serial Data (SDA) most significant bit first).
Table 3. Device Select Code[a] [b] [a] Permanent Write Protect features for the TSE2002av has been eliminated from the TSE2004GB2C0. [b] Don’t Care values for word address and data fields following commands may result in Ack or No_Ack responses. [c] For commands, SWPn, CWP, RPSn, SPAn, RPA ( Figure 6 ). [d] The most significant bit, b7, is sent first. [f] For backward compatibility with previous devices, the order of block select bits (b3 and b1) are not a simple binary encodin g of the block number. [g] SA0 pin is driven to 0 = VSSSPD, 1 = VDDSPD, or VHV. [h] SWP2L command affects only the lower half of Block 2; the upper half is left unprotected unless SWP2 is issued. [i] RPS2 command returns the combined status of the entire Block 2, the AND of both lower and upper halves. [j] RPS2L command responds with the status of write protection of the lower half of Block 2 whether protected by SWP2 or by SWP2 L commands. EEPROM. Subsequent Read EE or Write EE commands oper ate on the selected EE page. [l] Reading the EE page address results in Ack, when the current page is 0, and NoAck, when the current page is 1.
11©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Select Address. To address the EE memory array, the 4-bit Device Type Identifier is 1010b; to access the write-protection settings or EE page address, it is 0110b; and to access the Tem perature Sensor settings is 0011b. Additionally, writing or clearing the reversible EE write protect requires SA0 be raised to the VHV v oltage level. Up to eight memory devices can be connected on a single I 2C Bus. Each one is given a unique 3-bit Logical Serial Address code. The LSA is a decoding of information on the SA pins SA0, SA1, and SA2 ( Table 3). When the Device Select Code is received, the device only responds if the Select Address is the same as the Logical Serial Address. Write Protection commands SWPn, CWP, and RPSn, and the EE Page Address commands SPAn and RPA, do not use the Select Address or Logical Serial Address, therefore, all devices on the I 2C Bus will act on these commands simultaneously. Since it is impossible to determine which device is responding to RPSn or RPA commands, for example, these functions are primarily used for external device programmers rather than in-system applications. The eighth bit is the Read/Write bit (R/W_n). This bit is set to 1 for Read, and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the n inth bit time. If the device does not match the EE Device Select code, the EE section deselects itself from the bus, and switches in to Standby mode. The I 2C Bus operating modes are shown in Table 4.
Figure 7. VDDSPD Ramp-up and Ramp-down a Write instruction, until the completion of the internal Write cycle (t W). cold power-on reset timing when restoring power. The device is delivered with all bits in the EEPROM memory array when set to 1 (each byte contains 0xFF). Table 4. I2C Bus Operating Modes
16 START, Device Select, R/W_n = 0, data, STOP
The TSE2004GB2C0 has three software commands for setting, clearing, or interrogating the Write-protection status.
- SWPn: Set Write Protection for Block n
- CWP: Clear Write Protection for all Blocks
- RPSn: Read Protection Status for Block n
single block as specified in the SWPn command, but CWP clears the write protection for all blocks. Figure 8. Protocol for Write Protection Commands SWPn, CWP, RPSn replies to the data byte with an Ack. If the Software Write Protection has been set, the device replies to the data byte with a NoAck.
any requests. Access to the TS portion of the TSE2004GB2C0 is permitted during this period. protected block, the internal address counter is not incremented. Figure 9. Write Mode Sequences in a Non-Write Protected Area device replies with Ack. After the byte is transferred, the internal byte address counter is incremented unless the block is wr ite protected. The bus master terminates the transfer by generating a Stop condition ( Figure 9 ). condition known as “roll-over” occurs. This should be avoided, as data starts to be over-written in an implementation dependent fashion. internal byte address counter is incremented. The transfer is terminated by the bus master generating a Stop condition.
make use of this, a polling sequence can be used by the bus master. ▪ Initial condition: a Write cycle is in progress. Step 1: The bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). instruction (the first byte of this instruction having been sent during Step 1). Figure 10. Write Cycle Polling Flowchart Using ACK
incremented each time a byte is read. Figure 11. Read Mode Sequences incremented. The bus master terminates the transfer with a Stop condition ( Figure 11 ), without acknowledging the byte.
address, the address counter 'rolls-over', and the device continues to output data from memory address 0x00. the next valid START condition. This has no effect on the TS operational status. Table 5. Acknowledge when Writing Data or Defining Write Protection (R/W_n Bit = 0) Table 6. Acknowledge When Reading the Protection Status (R/W_n Bit = 1)
Figure 14. I2C Preset Pointer Register Word Read Figure 15. I2C Pointer Write Register Word Read Table 7. Temperature Register Addresses
00 R Capabilities Indicates the functions and capabilities of the
01 R/W Configuration Controls the operation of the temperature monitor 0000
02 R/W High Limit Temperature High Limit 0000
03 R/W Low Limit Temperature Low Limit 0000
04 R/W TCRIT Limit Critical Temperature 0000
05 R Ambient Temperature Current Ambient temperature N/A
06 R Manufacturer ID manufacturer ID 00b3
07 R Device/Revision Device ID and Revision number 2215
The Capabilities Register indicates the supported features of the temperature sensor. ▪ Bits 15 through Bit 8: RFU – Reserved for future use. These bits will always read 0 and writing to them will have no affect. ▪ Bit 7: EVSD – EVENT_n with shutdown action. Must be 1. may or may not be asserted when exiting shutdown if a pending interrupt has not been cleared. ▪ Bit 6: TMOUT is a bus timeout period for thermal sensor access during normal operation. — 1 (default): Parameter t TIMEOUT is supported within the range of 25ms to 35ms (SMBus compatible). — 1: Defined for compatibility with TS3000 devices. Since all TSE2004av devices are required to support VHV, this bit is not use d. ▪ Bits 4 through 3: TRES[1:0] – Indicates the resolution of the temperature monitor (default = 11), ( Table 9). ▪ Bit 2: RANGE – Indicates the supported temperature range. ▪ 0: The temperature monitor clamp values lower than 0°C. ▪ 1 (default): The temperature monitor can read temperatures below 0°C, and sets the sign bit appropriately. ▪ Bit 1: ACC indicates the supported temperature accuracy. monitoring range (40°C to 125°C). ▪ Bit 0: EVENT – Indicates whether the temperature monitor supports interrupt capabilities. — 1 (default): The device supports interrupt capabilities. Table 8. TS Capabilities Register Table 9. TRES Bit Decode
compatibility, all RFU bits must be programmed as 0. minus the hysteresis in order to be flagged as an interrupt event. Note that hysteresis is also applied to the EVENT_n pin func tionality. When either of the lock bits are set, these bits cannot be altered. ▪ Bit 8: SHDN (Shutdown) – The thermal sensing device and A/D converters are disabled to save power, no events will be generated. mode, the TSE2004GB2C0 still responds to commands normally, however bus timeout may or may not be supported in this mode. — 1: The temperature monitor is disabled and will not generate interrupts or update the temperature data. ▪ Bit 7: TCRIT_LOCK. Locks the TCRIT Limit Register from being updated. — 0 (default): The TCRIT Limit Register can be updated normally. ▪ Bit 6: EVENT_LOCK – Locks the High and Low Limit Registers from being updated. — 0: (default – The High and Low Limit Registers can be updated normally. ▪ Bit 5: CLEAR – Clears the EVENT_n pin when it has been asserted. This bit is write only and will always read 0. operating in Comparator Mode. This bit is self clearing. Table 10. TS Configuration Register
01 R/W
Table 11. HYST Bit Decode
22©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet ▪ Bit 4: EVENT_STS – Indicates if the EVENT_n pin is asserted. This bit is read only. — 0 (default): The EVENT_n pin is not asserted. — 1: The EVENT_n pin is being asserted by the device. ▪ Bit 3: EVENT_CTRL – Masks the EVENT_n pin from generating an interrupt. If either of the lock bits are set (bit 7 and bit 6), t hen this bit cannot be altered. — 0 (default): The EVENT_n pin is disabled and will not generate interrupts. — 1: The EVENT_n pin is enabled. ▪ Bit 2: TCRIT_ONLY – Controls whether the EVENT_n pin will be asserted from a high or low out-of-limit condition. When the EVENT_LOCK bit is set, this bit cannot be altered. — 0 (default): The EVENT_n pin will be asserted if the measured temperature is above the High Limit or below the Low Limit, in addition to, if the temperature is above the TCRIT Limit. — 1: The EVENT_n pin will only be asserted if the measured temperature is above the TCRIT Limit. ▪ Bit 1: EVENT_POL – Controls the active state of the EVENT_n pin. The EVENT_n pin is driven to this state when it is asserted. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. — 0 (default): The EVENT_n pin is active low. The “active” state of the pin will be logical 0. — 1: The EVENT_n pin is active high. The active state of the pin will be logical 1. ▪ Bit 0: EVENT_MODE – Controls the behavior of the EVENT_n pin. The EVENT_n pin may function in either comparator or interrupt mode. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. — 0: The EVENT_n pin will function in comparator mode. — 1: The EVENT_n pin will function in interrupt mode.
(TRES[1:0] = 11) are visible in reads from the Temperature Data Register. this is detected, bit 2 of all Limit Registers should be programmed to 0 to assure correct operation of the temperature compara tors. device temperature status and thermal EVENTs. For future compatibility, unused bits ‘-’ must be programmed as 0. Table 12. Temperature Register Coding Examples Table 13. High Limit Register
02 R/W
indicating which error conditions, if any, are active. The encoding of bits B12 through B0 is the same as for the temperature l imit registers. TCRIT, and will automatically clear once the temperature has dropped below the limit minus the hysteresis. HIGH limit. Once set, it will only be cleared when the temperature drops below or equal to the High Limit minus the hysteresis. Limit minus the hysteresis. Once set, it will only be cleared when the temperature meets or exceeds the Low Limit. Table 14. Low Limit Register
03 R/W
Table 15. TCRIT Limit Register
04 R/W
Table 16. Temperature Data Register [a] Resolution defined based on value of TRES field of the Capabilities Regist er. Unused/unsup ported bits will read as 0.
implemented via this register is also reflected in the capability register. Table 17. Manufacturer ID Register[a] [a] The Manufacturer ID Register holds the PCI SIG number assigned to the specific manufacturer.
06 R/W
Table 18. Device ID/Revision Register[a]
07 R/W
Table 19. Resolution Register
EVENT_n on a wire-OR bus, will show the combined results of all devices wired to the EVENT_n signal. 2C Bus”. Line capacitance limitations should be calculated using this assumption. Figure 16. Pull-up Resistor Value Table 20. Unique Addressing of SPDs in DIMM Applications[a] [a] 0 = V SSSPD, 1 = VDDSPD.
27©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet Programming the TSE2004GB2C0 The situations in which the TSE2004GB2C0 is programmed, can be considered under two headings: 1. When the DIMM is isolated (not inserted on the PCB motherboard) 2. When the DIMM is inserted on the PCB motherboard DIMM Isolated With specific programming equipment, it is possible to define the TSE2004GB2C0 content, using Byte and Page Write instructions, and its write-protection using the SWPn and CWP instructions. To issue the SWPn and CWP instructions, the DIMM must be inserted in the application-specific slot where the SA0 signal can be driven to VHV during the whole instruction. This programming step is main ly intended for use by DIMM makers, whose end application manufacturers will want to clear this write-protection with the CWP on t heir own specific programming equipment, to modify the protected bytes, and finally to set the write-protection with the SWPn instructio n. In DIMM Isolation usage, the Read Protection Status (RPSn), Set EE Page Address (SPAn), and Read EE Page Address (RPA) commands are fully supported.
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability . Figure 17. AC Measurement I/O Waveform Table 21. Absolute Maximum Ratings Table 22. Operating Conditions Table 23. AC Measurement Conditions
Table 24. Input Parameters [b] Verified by design and characterization, not necessarily tested on all devices.
Table 25. DC Characteristics
Table 26. AC Characteristics[a] [a] TSE devices are not required to support the I 2C Bus ALERT function. [b] 400kHz timing defined for compatibility with TSE2002av applications. [c] The TSE2004GB2C0 does not initiate clock stretching, which is an optional SMBus feature. [d] The TSE2004GB2C0 supports bus time-out on EE access. than tTIMEOUT,MAX . Typical device examples include the host controller, an embe dded controller, and most devices that can master the SMBus. a stop condition. A timeout condition can only be ensured if, the device that is forcing the timeout holds SCL low for t IMEOUT,MAX or longer. [f] Guaranteed by design and characterization at 50°C, 3.6V. Not tested on all devices. [g] To avoid spurious START and ST OP conditions, a mi nimum delay is placed be tween the falling edge of SCL and the falling or ri sing edge of SDA. [h] For a re-START condition, or following a Write cycle.
Figure 18. AC Waveforms Table 27. Temperature-to-Digital Conversion Performance [b] Assuming 10-bit resolution.
Figure 19. EE/TSE Bus Timeout Waveforms
Figure 20. Package Drawings
Figure 21. Package Drawings, (CONT.)
Figure 22. Recommended Land Pattern
37©2017 Integrated Device Technology, Inc. May 15, 2017 TSE2004GB2C0 Datasheet Marking Diagram
Ordering Information
Orderable Part Number Package Carrier Type Temperature TSE2004GB2C0NCG 4B2DCY Tray -40° to +85°C TSE2004GB2C0NCG 4B2DCY Tape and Reel -40° to +85°C Line 1. Line 1 is the truncated part number/ Product Description. Line 2. DCY denotes Produce Description + Y, where Y = last digit of year assembled. Line 3. “***” denotes sequential lot number characters from AAA to ZZZ. XXXXX XX X Rev.Voltage Shipping
8 Tape and Reel
X Device Type 2004G Temperature Sensor with EEPROM X Temp B Temperature Accuracy Grade Carrier TSE Range 2 = (2.2V to 3.6V) XXX Package NCG - Green TDFN
38©2017 Integrated Device Technology, Inc. May 15, 2017 DISCLAIMER Integrated Device Te chnology, Inc. (IDT) and its aff iliated companies (herein referred to as “IDT”) reserve the righ t to modify the products and/or specific ations described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of IDT's products for any particular purpose, an implied warran ty of merchantab ility, or non-infringement of the intellectual p roperty rights of others. This documen t is presented only as a guide and does not convey any license under intellectual propert y rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other c ountries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
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Revision History
Revision Date Description of Change May 15, 2017 Table 25 - corrected units for I LI, ILO, IDD1 rows. May 2, 2017 Initial release. Reference Information JEDEC Standard No. 21-C, Release 26, modified February 3, 2016; Section 4.1.6 Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 KBit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications