TSE2004GB2B0

TSE2004GB2B0 IDT | Alldatasheet

Document overview

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Technical content

Features

• Temperature Sensor + 512 Byte Serial EEPROM
• 512 Byte Serial EEPROM for SPD
• Single Supply: 2.2V to 3.6V
• Accurate timeout support - Meets strict SMBus spec of 25ms (min), 35ms (max)
• Timeout supported for Temp Sensor and EEPROM
• Timeout supported in all Modes – Active mode for T emp sensor and EEPROM – EEPROM in standby or T emp sensor in shutdown – EEPROM in standby and T emp sensor in shutdown
• Schmitt trigger and noise filtering on bus inputs
• 2-wire Serial Interface: 10KHz to 1 MHz max I2C™ /SMBus™
• Available Package: TDFN-8 Temperature Sensor Features
• Temperature Converted to Digital Data
• Sampling Rate of 125ms (max)
• Selectable 0, 1.5°C, 3°C, 6°C Hysteresis
• Programmable Resolution from 0.0625°C to 0.5°C
• Accuracy: – ±0.5°C/ ±1.0°C (typ/max)from +75°C to +95°C – ±1.0°C/±2.0°C (typ/max) from +40°C to +125°C – ±2.0°C/ ±3.0°C (typ/max) from -40°C to +125°C Serial EEPROM Features
• Individual Reversible Software Data Protection for all 128 Byte Blocks
• Byte and page (up to 16 Bytes) Write Operation
• Self-time Write cycle
• Automatic address incrementing
• Random and Sequential Read modes Typical Applications
• DIMM Modules (DDR3, DDR4)
• Servers, Laptops, Ultra-portables, PCs, etc.
• Industrial temperature monitors
• Hard Disk Drives and Other PC Peripherals TSE2004GB2B0 Data Sheet DDR4 Temperature Sensor with Integrated 4Kbit EEPROM for Memory Modules

2 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Block Diagram: Temperature Sensor with EEPROM

3 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Maximum Ratings Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at th ese or any other conditions above those indi cated in the Operating sections of th is specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings DC and AC Parameters This section summarizes the operating and measurement conditions, and the DC and AC char acteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the M easurement Conditions summarized in the re levant tables. Designers should check that the operating conditions in their ci rcuit match the measurement c onditions when relying on the quot ed parameters. DC Characteristics Operating Conditions Symbol Parameter Min. Max. Units TSTG Storage Temperature -65 150 C VIO Input or output range, SA0 -0.50 10 V Input or output range, other pins -0.50 4.3 V VDDSPD Supply V oltage -0.5 4.3 V Symbol Parameter Min. Max. Units VDDSPD Supply V oltage 2.2 3.6 V TA Ambient operating temperature -40 +125 C

4 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice AC Measurement Conditions AC Measurement I/O Waveform Input Parameters for the TSE2004GB2B0 1.TA=25°C, f=400 kHz 2.Verified by design and characterization not necessarily tested on all devices Symbol Parameter Min. Max. Units CL Load capacitance 100 pF Input rise and fall times 50 ns Input levels 0.2*V DDSPD to 0.8*VDDSPD V Input and output timing reference levels 0.3*V DDSPD to 0.7*VDDSPD V Symbol Parameter 1,2 Test Condition Min. Max. Units CIN Input capacitance (SDA) 8 pF CIN Input rise and fall times 6 ns ZEIL Ei (SA0,SA1,SA2) input impedance V IN< 0.3* VDDSPD 30 k  ZEIH Ei (SA0,SA1,SA2) input impedance V IN> 0.7* VDDSPD 800 k  tSP Pulse width ignored (input filter on SCL and SDA) Single glitch, f < 100 KHz 100 ns Single glitch, f> 100 KHz 50

5 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice DC Characteristics 1. In order to drive full bus load at 400 KHz, 6 mA IOL is required at 0.6 V VOL. Parts not meeting this specification can still function, but not at 400 KHz and 400 pF. Parameter Conditions f < 400KHz f > 400 KHz Units Min Max Min Max ILI Input leakage current (SCL, SDA) VIN = VSSSPD or VDDSPD -- ± 5 -- ± 5 A ILO Output leakage current VOUT = VSSSPD or VDDSPD, SDA in Hi-Z -- ± 5 -- ± 5 A IDD Supply current V DDSPD = 3.3 V, fC = 100 kHz (rise/fall time < 30 ns) -- 2 -- 2 mA IDD1 Standby Supply current VIN = VSSSPD or VDDSPD, VDDSPD = 3.6 V -- 100 -- 100 A VIN = VSSSPD or VDDSPD, VDDSPD = 2.2V -- 100 -- 100 A VIL Input low voltage (SCL, SDA) -- -0.5 0.3 * VDDSPD -0.5 0.3 * VDDSPD V VIH Input high voltage (SCL, SDA) -- 0.7 * VDDSPD VDDSPD + 0.5 0.7 * VDDSPD VDDSPD + 0.5 V VHV SA0 high voltage VHV - V DDSPD > 4.8 V 71 071 0 V VOL1 Output low voltage open-drain or open-collector 3 mA sink current, VDDSPD > 2 V -- 0.4 -- 0.4 V IOL LOW-level output current1 VOL = 0.4 V 3 20 mA VOL = 0.6 V 6 -- mA VHYST Input hysteresis VDDSPD > 2 V 0.05 * VDDSPD -- 0.05 * VDDSPD -- V VPON Power On Reset threshold Monotonic rise between VPON and VDDSPD(min) without ringback 1.6 -- 1.6 -- V VPOFF Power Off threshold for warm power on cycle No ringback above VPOFF -- 0.9 -- 0.9 V Notes:

6 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice AC Characteristics VDDSPD ≥ 2.2 V

400 KHz8 1000 KHz

Symbol Parameter Min Max Min Max Units fSCL Clock frequency 10 400 10 1000 kHz tHIGH Clock pulse width high time 600 -- 260 -- ns tLOW5 Clock pulse width low time 1300 -- 500 -- ns tTIME-OUT4,6 Detect clock low timeout 25 35 25 35 ms tR2 SDA rise time 20 300 -- 120 ns tF2 SDA fall time 20 300 -- 120 ns tSU:DAT Data in setup time 100 -- 50 -- ns tHD:DI Data in hold time 0 -- 0 -- ns tHD:DAT Data out hold time 200 900 0 350 ns tHD:STA1 Start condition setup time 600 -- 260 -- ns tHD:STA Start condition hold time 600 -- 260 -- ns tSU:STO Stop condition setup time 600 -- 260 -- ns tBUF Time between Stop Condition and next Start Condition 1300 -- 500 -- ns tW Write time -- 5 -- 5 ms tPOFF Warm power cycle off time 1 -- 1 -- ms tINIT Time from power on to first command 10 -- 10 -- ms Note 1: For a reSTART condition, or following a write cycle Note 2: Guaranteed by design and characterization, not necessarily tested Note 3: To avoid spurious START and STOP conditions, a minimum delay is placed between falling edge of SCL and the falling or rising edge of SDA Note 4: The TSE2004GB2B0 supports bus timeout on EE access. Note 5: The TSE2004GB2B0 does not initiate clock stretching, which is an optional SMBus feature. Note 6: Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds the value of t TIMEOUT,MIN. After the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include the host controller, and embedded controller and most devices that can master the SMBus. Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or a stop condition. A timeout condition can only be ensured if the device that is forcing the timeout holds SCL low for tTIMEOUT,MAX or longer. Note 7: TSE devices are not required to support the I2C Bus ALERT function. Note 8: 400 KHz timing defined for compatibility with TSE2002av applications.

7 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Temperature-to-Digital Conversion Performance 1. Assuming 10-bit resolution. 2. VDDSPDMIN < VDDSPD < VDDSPDMAX AC Waveforms Parameter Typ Max Unit Test Conditions 2 Temperature Sensor Accuracy (JEDEC B-grade) TA < 95°C, Active Range ±1.0 ±2.0 °C 40°C < TA < 125°C, Monitor Range Resolution 0.0625 °C Conversion Time1 125 ms Worse case conversion time

8 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Pin Assignment Pin Description1 1. The thermal sensing heat paddle is located on the backside of the package. JEDEC suggests connecting the heat paddle to grou nd for better thermal connection between the DIMM PCB plane and the temperature sensor. Pin Functional Descriptions Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain out put, and a pull-up resistor can be co nnected from Serial Clock (SCL) to VDDSPD. (refer to the Maximum R L Value vs. Bus Capacitance figure on how the value of the pull- up resistor can be calculated). In most applications, though, th is method of synchronization is not employed, and so the pull-up resist or is not necessary, provided that the bus master has a pus h-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-ORed w ith other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to the most positive VDDSPD in the i2C Bus chain. (refer to the Maximum RL Value vs. Bus Capacitance figure on how the value of the pull-up resistor can be calculated). Pin # Pin Name Definition

1 SA0 Select Address 0

2 SA1 Select Address 1

3 SA2 Select Address 2

5S D A S e r i a l D a t a I n

6 SCL Serial Clock In

7 EVENT

9 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Maximum RL Value vs. Bus Capacitance (CBUS) for an I2C Bus Select Address (SA0, SA1, SA2) These input signals are used to create the Logica l Serial Address LSA that is compared to the least significant bits (b3, b2, b 1) of the 7-bit Slave Address. Refer to the SMBus Address Modes t able. The SA0 input is used to detect the V HV voltage, when decoding an SWPn or CWP instruction. Refer to the SMBus Operating Modes table for decoding details. EVENT The TSE2004GB2B0 EVENT pin is an open drain output that requires a pull-up to V DDSPD on the system motherboard or integrated into the master controller. The TSE2004GB2B0 EVENT pin has three operating modes, depending on configuration settings and any current out-of-limit condi- tions. These modes are Interrupt, Comparator, or TCRIT Only. In Interrupt Mode the EVENT pin will remain asserted until it is released by writing a '1' to the “Clear Event” bit in the Status Register. The value to write is independent of the EVENT polarity bit. In Comparator Mode the EVENT pin will clear itself when the error condition that caused the pin to be asserted is removed. When the temperature is compared against the TCRIT limit, then this mode is always used. Finally, in the TCRIT Only Mode the EVENT pin will only be asserted if the measured temperature exceeds the TCRIT Limit. Once the pin has been asserted, it will remain asserted until the temperature drops bel ow the TCRIT Limit minus the TCRIT hysteresis. The next figure illustrates the opera- tion of the different modes over time and temperature. Systems that use the active high mode for EVENT must be wired point to point between the T SE2004GB2B0 and the sensing controller. Wire-OR configurations should not be used with active high EVENT since any device pulling the EVENT signal low will mask the other devices on the bus. Also note that the normal state of EVENT in active high mode is a 0 which will continually draw power through the pull-up resistor.

10 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice EVENT Pin Mode Functionality Serial Communications The TSE2004GB2B0 includes a 4 Kbit serial EEPR OM organized as two pages of 256 bytes each, or 512 bytes of total memory. Each p age is comprised of two 128 byte blocks. The devices are able to selectively lock the data in any or all of the four 128-byte blocks. Designed specifically for use in DRAM DIMMs (Dual Inline Memory Modules) with Serial Presence Detect, al l the information concerning the DRAM module configura- tion (such as its access speed, its size, its organization) can be kept write protected in one or more of the blocks of memory. The TSE2004GB2B0 devices are protocol compatible with previous generation 2 Kbit devices such as the TSE2002. The page selectio n method allows commands used with legacy devices such as TSE2002 to be applied to the lower or upper pages of the TSE2004GB2B0. In this way, the TSE2004GB2B0 may be used in legacy applications without software changes. Minor exceptions to this compatibility, such as elimi nation of the Permanent Write Protect feature, are documented. Individually locking a 128-byte block of the SPD may be accomplished using a software write protection mechanism in conjunction with a high input voltage VHV on input SA0. By sending the device a specific SMBus sequence, each block may be protected from writes until write protection is elec- trically reversed using a separate SMBus s equence which also requires VHV on input SA0. Write protection for all four blocks is cleared simultane- ously, and write protection may be reasserted after being cleared. The Thermal Sensor (TS) section of the TSE2004GB2B0 continuou sly monitors the temperature and updates the temperature data a minimum of eight times per second. Temperature data is latched internally by the device and may be read by software from the bus host at any time. Internal registers are used to configure both the TS performance and response to over-temperature conditions. The device contains programmable high, low, and critical temperature limits. Finally, the device EVENT_n pin can be conf igured as active high or active low and can be configured to operate as an interrupt or as a comparator output.

11 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Device Diagram Device Interface The TSE2004GB2B0 behaves as a slave device in the I 2C Bus protocol, with all memo ry operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START conditi on is followed by a Device S elect Code and R/W# bit (as described in the I 2C Bus Operating Mode table), terminated by an acknow ledge bit. The TSE2004GB2B0 does not initiate clock stretching which is an optional I2C Bus feature. In accordance with the I 2C Bus definition, the device uses three (3) built-in, 4-bit Device Type Identifie r Codes (DTIC) and the state of SA0, SA1, and SA2 to generate an I 2C Bus Slave Address. The SPD memory may be accessed us ing a DTIC of (1010), and to perform the SWPn, RSPn, or CSWP operations a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011). Serial Address Selection Inputs SA0, SA1, and SA2 inputs are directly combined with t he DTIC and the EE page address bit to qualify SMBus addresses. Eac h of the SA pins is tied to VDDSPD or VSSSPD and the Logical Serial Address (LSA) is equal to the code on the Serial Address pins. I2C Bus Addressing Modes Logical Serial Address(LSA) SA2 SA1 SA0 000 0 0 0 001 0 0 1 010 0 1 0 011 0 1 1 100 1 0 0 101 1 0 1 110 1 1 0 111 1 1 1 Note 1: 0 = VSSSPD, 1 = VDDSPD

12 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Interface Protocol When writing data to the memory, the SPD inserts an acknowledge bi t during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are te rminated by a Bus Master generated STOP condition after an Ack for WRITE, and after a NoAck for READ. Violations of the command protocol result in unpredictable operation. The TS section of the device uses a pointer register to access all registers in t he device. Additionally, all data transfers to and from this section of the device are performed as block read/ writ e operations. The data is transmitted/receiv ed as 2 bytes, Most Significant Byte (M SB) first, and termi- nated with a NoAck and STOP after the Least Significant byte (LSB). Data and address information is transmitted and received st arting with the Most Significant Bit.first I2C Bus Protocol Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

13 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communica- tion between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to for ce the SPD into Standby mode. A Stop condition at the end of a Write command trigger s the internal EEPROM Write cycle for the SPD. Neither of t hese conditions changes the operation of the TS section. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a su ccessful byte transfer. The bus transmitter, whether it be bus master or slave devi ce, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. No Acknowledge Bit (NACK) The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus master releases Serial Data (SDA) after sending eight bits of data, and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Cloc k (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in the next table (on Serial Data (SDA), most significant bit first).

14 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Device Select Code The Device Select Code consists of a 4-bi t Device Type Identifier, and a 3-bit Select Address. To address the EE memory array, the 4-bit Device Type Identifier is 1010b; to access the write-protection setting s or EE page address, it is 0110b; and to access the Temperatur e Sensor settings is 0011b. Additionally, writing or clearing the reversible EE write protect requires that SA0 be raised to the VHV voltage level. Up to eight memory devices can be connected on a single I 2C Bus. Each one is given a unique 3-bit Logi cal Serial Address code. The LSA is a decoding of information on the SA pins SA0, SA1and SA2 as described in the table above. When the Device Select Code is received, the device only responds if the Select Address is the same as the Logical Serial Address. Write Protection commands SWPn, CWP, and RPSn, and the EE Page A ddress commands SPAn and RPA, do not use the Select Address or Logical Serial Address, ther efore all devices on the I 2C Bus will act on these commands simultaneously. Since it is impossible to determine which device is responding to RPSn or RPA commands , for example, these functions are primar ily used for external device programmers r ather than in-system applications. The 8th bit is the Read/Write bit (R/W_n). This bit is set to 1 for Read and 0 for Write operations. Function Abbr Device Type Identifier1 Select Address2, 4 W_n SA0 Pin3 b7 b6 b5 b4 b3 b2 b1 b0 Read Temperature registers RTR

0011 L S A 2 L S A 1 L S A 0

Write Temperature registers WTR 0 Read EE memory RSPD

1010 L S A 2 L S A 1 L S A 0

Set Write Protection, block 0 SWP0 0110

0010 V HV

Set Write Protection, block 1 SWP1 1 0 0 0 V HV Set Write Protection, block 2 SWP2 1 0 1 0 V HV Set Write Protection, block 3 SWP3 0 0 0 0 V HV Clear All Write Protection CWP 0 1 1 0 V HV Read Protection Status, block 0 RPS0 0 0 1 1 0, 1 or V HV Read Protection Status, block 1 RPS1 1 0 0 1 0, 1 or V HV Read Protection Status, block 2 RPS2 1 0 1 1 0, 1 or V HV Read Protection Status, block 3 RPS3 0 0 0 1 0, 1 or V HV Set SPD Page Address to 05 SPA0 1 1 0 0 0, 1 or V HV Set SPD Page Address to 15 SPA1 1 1 1 0 0, 1 or V HV Read SPD Page Address6 RPA 1 1 0 1 0, 1 or V HV Reserved -- All Other Encodings Note 1: The most significant bit, b7, is sent first. Note 2: Logical Serial Addresses (LSA) are generated by the combination of inputs on the SA pins. Refer to the table “ I2C Bus Addressing Modes” Note 3: SA0 pin is driven to 0 = VSSSPD, 1 = VDDSPD, or VHV. Note 4: For backward compatibility with previous devices, the order of block select bits (b3 and b1) are not a simple binary encoding of the block number. Note 5: Set EE page address to 0 selects the lower 256 bytes of EEPROM, setting to 1 selects the upper 256 bytes of EEPROM. Subsequent Read EE or Write EE commands operate on the selected EE page. Note 6: Reading the EE page address results in Ack when the current page is 0 and NoAck when the current page is 1. Note 7: Permanent Write Protect features of the TSE2002av has been eliminated from the TSE2004GB2B0. Note 8: Don’t Care values for word a ddress and data fields foll owing commands may result in Ack or No_Ack responses. from the TSE. Refer to the figure “ Protocol for Commands SWPn, CWP, RPSn, SPAn, RPA”

15 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice If a match occurs on the Device Select code, the corresponding dev ice gives an acknowledgment on Serial Data (SDA) during the 9 th bit time. If the device does not match the EE Device Select code, the EE se ction deselects itself from the bus, and goes into Standby mode. The I2C Bus oper- ating modes are shown in the following table. I2C Bus Operating Modes Device Reset and Initialization In order to prevent inadvertent Write operat ions during Power-up, a Power-On Reset (P OR) circuit is included. On cold power on, VDDSPD must rise monotonically between V PON and VDDSPD(min) without ringback to ensure proper startup. Once V DDSPD has passed the V PON threshold , the device is reset. Prior to selecting the memory and issuing instructions, a valid and stable VDDSPD voltage must be applied, and no command may be issued to the device for tINIT. This supply voltage must remain stable and valid until the end of the transmission of the instruction and for a Write instruction, until the completion of the internal write cycle (tW). At Power-down (phase during which VDDSPD decreases continuously), as soon as VDDSPD drops below the minimum operating voltage, the device stops responding to commands. On warm power cycling, VDDSPD must remain below VPOFF for tPOFF, and must meet cold power on reset timing when restoring power. The device is delivered with all bits in the EEPROM memory array set to ' 1' (each byte contains 0xFF). Mode R/W_n Bit Bytes Initial Sequence EE Current Address Read 1 1 START, Device Select, R/W_n = 1 EE Random Address Read START, Device Select, R/W_n = 0, Address 1 reSTART, Device Select, R/W_n = 1 EE Sequential Read 1 > 1 Similar to Current or Random Address Read EE Byte Write 0 1 START, Device Select, R/W_n = 0, data, STOP EE Page Write 0 < 16 START, Device Select, R/W_n = 0, data, STOP TS Write 0 2 START, Device Select, R/W_n=0, pointer, data, STOP TS Read 1 2 START, Device Select, R/W_n=1, pointer, data, STOP

16 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Software Write Protect The TSE2004GB2B0 has three software commands for setting, clearing or interrogating the write-protection status Software write-protection is handled by three instructions: SWPn: Set Write Protection for Block n CWP: Clear Write Protection for all Blocks RPSn: Read Protection Status for Block n There are four independent memory blocks, and each block may be independently protected. The memory blocks are:

• Block 0 = memory addresses 0x00 to 0x7F (decimal 0 to 127), SPD Page Address = 0
• Block 1 = memory addresses 0x80 to 0xFF (decimal 128 to 255), SPD Page Address = 0
• Block 2 = memory addresses 0x00 to 0x7F (decimal 0 to 127), SPD Page Address = 1
• Block 3 = memory addresses 0x80 to 0xFF (decimal 128 to 255), SPD Page Address = 1 The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. SWPn and CWP:Set and Clear Write Protection If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. SWPn acts on a single block as specified in the SWPn command, but CWP clears write protection for all blocks Potocol for Write Protection Commands SWPn, CWP, RPSn RPSn: Read Protection Status The controller issues a RPSn command sp ecifying which block to report upon. If Softw are Write Protection has not been set, the device replies to the data byte with an Ack. If Software Write Protection has been set, the device replies to the data byte with a NoAck. SPAn: Set SPD Page Address The controller issues an SPAn command to select the lower 256 bytes (SPA0) or upper 256 bytes (SPA1). After a cold or warm power-on reset, the SPD Page Address is always 0, selecting the lower 256 bytes RPA: Read SPD Page Address The controller issues an RPA command to determine if the currently selected SPD page is 0 (device returns Ack) or 1 (device returns NoAck). Write Operations Following a Start condition the bus master s ends a Device Select Code with the R/W_n bit reset to 0. The device acknowledges th is, as shown in the figure below “Write Mode Sequence in a Non-Write Protected Area”, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte.

17 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice When the bus master generates a Stop condition immediately after the Ack bit (in the “10t h bit” time slot), either at the end o f a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored by the EE, and the EE device does not res pond to any requests. Access to the TS portion of the TSE2004GB2B0 is permitted during this period. The device has an internal address counter which is incremented each time a byte is written. If a Write operation is performed to a protected block, the internal address counter is not incremented Write Mode Sequences in a Non-Write Protected Area Byte Write After the Device Select Code and the address byte, the bus mast er sends one data byte. If the addressed location is write-prote cted, the device replies to the data byte with NoAck, and the location is not mo dified. If, instead, the addressed location is not Write-protect ed, the device replies with Ack. After the byte is transferred, the internal byte address c ounter is incremented unless the block is write protected. The bus master terminates the transfer by generating a Stop condition, as shown in the Write Mode Sequence in a Non-Write Protected Area as shown in the figure above. Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same . If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. This should be avoided, as data starts to be over-written in an implementation dependent fashion. The bus master sends from 1 to 16 bytes of data, each of whic h is acknowledged by the device. If the addressed location is writ e-protected, the device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter is incre- mented. The transfer is terminated by the bus master generating a Stop condition. Write Cycle Polling Using ACK During the internal Write cycle, the devic e disconnects itself from the bus, and writes a copy of the data from its internal la tches to the memory cells. The maximum Write time (t W) is shown in theTSE2004GB2B0 AC Characteristic table, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The polling sequence is shown in the following figure:

• Initial condition: a Write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).

18 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice

• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Write Cycle Polling Flowchart Using ACK Read Operations Read operations are performed independent of t he software protection state. The device has an internal address counter which is incremented each time a byte is read.

19 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Read Mode Sequences Random Address Read A dummy Write is first performed to load the address into this address counter (refer to the Read Mode Sequence figure) but wit hout sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the R/W_n bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read For the Current Address Read operation, following a Start condition, the bus master onl y sends a Device Select Code with the R/ W_n bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address c ounter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in the Read Mode Sequence figure, without acknowledging the byte.

20 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Sequential Read This operation can be used after a Current Address Read or a R andom Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop c ondition (refer to the Read M ode Sequence figure). The output dat a comes from consecutive addresses, with the internal a ddress counter automatically incremented after each byte output. After the last memor y address, the address counter 'rolls-over', and the device continues to output data from memory address 0x00. Acknowledge in Read Mode For all Read commands to the SPD, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and returns to an idle state to await the next valid START condition. This has no effect on the TS operational status. Acknowledge When Writing Data or Defining Write Protection (Instructions with R/W_n Bit=0) Acknowledge When Reading the Protection Status (Instructions with R/W_n Bit=1) Note: X = Set or Not Set. Temperature Sensor (TS) Device Operation The TSE2004GB2B0 Temperature Register Set is accessed though the I 2C Bus address 0011_bbb_R/W_n. The “bbb” denotes the Logical Serial Address code LSA. In the event SA0 is in the high voltage state, the device does not reconize t he LSA. The Temperature Register Set stores the temperature data, limits, and configuration values. All registers in the address spac e from 0x00 through 0x08 are 16-bit regist ers accessed through block read and write commands as detailed in the TS Write Operation section. Behavior on accesses to invalid register locations is vendor-specific and may return an Ack or a NoAck. TS Write Operations Writing to the TSE2004GB2B0 Temperature Register Set is accomplished through a modified block write operation for two (2) data bytes. To main- tain I2C Bus compatibility, the 16 bit register is accessed through a pointer register, requiring the write sequence to include an address pointer in addi- tion to the Slave address. This indicates the storage location for the next two bytes received. The next figure shows an entire write transaction on the bus. Status Instruction ACK Address ACK Data Byte ACK Write Cycle (tW) Protected with SWP SWPn NoACK Not Significant NoACK Not Significant NoACK No CWP ACK Not Significant ACK Not Significant ACK Yes Page or byte write in protected block ACK Address ACK Data NoACK No Not Protected SWPn, or CWP ACK Not Significant ACK Not Significant ACK Yes Page or byte write ACK Address ACK Data ACK Yes SWPn Status Instruction ACK Address ACK Data Byte ACK Set RPSn NoACK Not Significant NoACK Not Significant NoACK Not Set RPSn ACK Not Significan t NoACK Not Significant NoACK

21 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice TS Register Write Operation TS Read Operations Reading data from the TS may be accomplished in one of two ways: 1. If the location latched in the Pointer Register is correct (for normal operation it is expected the same address will be read repeatedly for tempera- ture), the read sequence may consist of a Slave Address from the bus master followed by two bytes of data from the device; or 2. The pointer register is loaded with the correct register address, and the data is read. The sequence to preset the pointer register is shown in the I2C Bus Write to Pointer Register figure, and the preset pointer read is shown in the I2C Bus Preset Pointer Register Word Read figure. If it is desired to read random address each cycle, the complete Pointer Write, Word Read sequence is shown in the I 2C Bus Pointer Write Register Word Read figure. The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (Ack) or No Acknowledge (No Ack) from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte).

22 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice I2C Write to Pointer Register I2C Preset Pointer Register Word Read I2C Pointer Write Register Word Read TS Register Set Definition The register set address are shown in the Acknowledge When Writing Data or Defining Wr ite Protection table. These values are us ed in the I 2C Bus operations as the “REG_PTR” as shown in previous three figures.

23 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Temperature Register Addresses Capabilities Register The Capabilities Register indicates the supported features of the temperature sensor. TS Capabilities Register Bits 15 - Bit 8 – RFU; Reserved for future use. These bits will always read '0' and writing to them will have no affect. Bit 7- EVSD-EVENT with Shutdown action. Must be 1. ‘0’ - Not used ‘1’ The EVENT output is deasserted (not driven) when entering shutdown and re mains deasserted upon exit from shutdown until the next thermal sample is taken, or possibly sooner if EVENT is programmed for comparator mode. Bit 6 - TMOUT – Bus timeout period for thermal sensor access during normal operation. ‘0’ - Not Used ‘1’ - (default) Parameter tTIMEOUT is supported within the range of 25 to 35 ms (SMBus compatible). Bit 5 - VHV ‘0”- Not used ‘1’ Defined for compatibility with TS3000 devices; since all TSE2004av devices are required to support VHV, this bit is not used. Bits 4 - 3 – TRES[1:0]; Indicates the resolution of the temperature monitor as shown in the TRES Bit Decode table. (Default =11) ADDR R/W Name Function Default N/A W Address Pointer Address storag e for subsequent operations N/A

00 R Capabilities Indicates the functions and capabilities of the

01 R/W Configuration Controls the operation of the temperature monitor 0000

02 R/W High Limit Temperature High Limit 0000

03 R/W Low Limit Temperature Low Limit 0000

04 R/W TCRIT Limit Criti cal Temperature 0000

05 R Ambient Temperature Curre nt Ambient temperature N/A

06 R Manufacturer ID ma nufacturer ID 00b3

07 R Device/Revision Device ID and Revision number 2214

08-0F R/W Vendor Defined Vendor specific information 0018 ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default 00 R RFU RFU RFU RFU RFU RFU RFU RFU 00ff EVSD TMOUT VHV TRES[1:0] RANGE ACC EVENT

24 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice TRES Bit Decode Note: Refer to section “Resolution Register” Bit 2 - RANGE; Indicates the supported temperature range. '0' - The temperature monitor clamps values lower than 0 °C. '1' (default) - The temperature monitor can read temperatures below 0 °C and sets the sign bit appropriately. Bit 1 - ACC; Indicates the supported temperature accuracy. '0' - Not Used '1' (default) - Bgrade. The temperature monitor has ±1 °C accuracy over the active range (75 °C to 95 °C) and 2°C accuracy over the monitoring range (40 °C to 125 °C) Bit 0 - EVENT; Indicates whether the temperature monitor supports interrupt capabilities '0'.-Not used. '1' (default); The device supports interrupt capabilities. TS Configuration Register TS Configuration Register The Configuration Register holds the contro l and status bits of the EVENT pin as well as general hysteresis on all limits. To a void glitches on the EVENT_n output in, users should disable EVENT or TCRIT functions prior to programming or changing other device configuration settings. Bits 15 - 11 – RFU; Reserved for future use. These bits will always read '0' and writing to them will have no affect. For futur e compatibility, all RFU bits must be programmed as '0'. Bits 10 - 9 – HYST[1:0]; Control t he hysteresis that is applied to all limits as shown in the HYST Bit Decode table that follow s. This hysteresis applies to all limits when the temperature is dropping below the threshold so that once the temperature is above a given threshold, it must drop below the threshold minus the hysteres is in order to be flagged as an interrupt event. No te that hysteresis is also applied to EVENT pin functionality. When either of the lock bits is set, these bits cannot be altered. TRES[1:0] Temperature Resolution 0 0 0.5°C (9-bit) 1 0 0.125°C (11-bit) 1 1 0.0625°C (12-bit) (default) ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B 11/B3 B10/B2 B9/B1 B8/B0 Default

01 R/W

RFU RFU RFU RFU RFU HYST[1:0] SHDN 0000TCRIT_ LOCK EVENT_ LOCK CLEAR EVENT_ STS EVENT_ CTRL TCRIT_ ONLY EVENT_ POL EVENT_ MODE

25 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice HYST Bit Decode Bit 8 – SHDN-Shutdown. The thermal sensing device and A/D converters are disabled to save power, no events will be generated. W hen either of the lock bits is set, this bit cannot be set until unlocked. Howe ver it can be cleared at any time. When in shutdown mode, the TSE2004GB2B0 still responds to commands normally, however bus timeout may or may not be supported in this mode. '0' (default); The temperature monitor is active and converting '1'; The temperature monitor is disabled and will not generate interrupts or update the temperature data. Bit 7 – TCRIT_LOCK; Locks the TCRIT Limit Register from being updated. '0' (default; The TCRIT Limit Register can be updated normally. '1'; The TCRIT Limit Register is locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal power on reset. Bit 6 – EVENT_LOCK; Locks the High and Low Limit Registers from being updated. '0' (default); The High and Low Limit Registers can be updated normally. '1'; The High and Low Limit Registers are locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal power on reset. Bit 5 – CLEAR; Clears the EVENT pin when it has been asserted. This bit is write only and will always read '0'. '0'; does nothing '1'; The EVENT pin is released and will not be asserted until a new interrupt condition occurs. This bit is ignored if the device is operating in Comparator Mode. This bit is self clearing. Bit 4 – EVENT_STS; Indicates if the EVENT pin is asserted. This bit is read only. ‘0' (default); The EVENT pin is not asserted. '1'; The EVENT pin is being asserted by the device. Bit 3 – EVENT_CTRL; Masks the EVENT pin from generating an interrupt. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. '0' (default); The EVENT pin is disabled and will not generate interrupts. '1'; The EVENT pin is enabled. Bit 2 – TCRIT_ONLY; Controls whether the EVENT pin will be asserted from a high / low out-of-lim it condition. When the EVENT_LOCK bit is set, this bit cannot be altered. '0' (default); The EVENT pin will be asserted if the measured temperature is above the High Limit or below the Low Limit in addition to if the temperature is above the TCRIT Limit. '1'; The EVENT pin will only be asserted if the measured temperature is above the TCRIT Limit. Bit 1 – EVENT_POL; Controls the “active” state of the EVENT pin. The EVENT pin is driven to this state when it is asserted. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. HYST[1:0] Hysteresis 0 0 Disable hysteresis (default) 0 1 1.5°C 1 0 3°C 1 1 6°C

26 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice '0' (default); The EVENT pin is active low. The “active” state of the pin will be logical '0'. '1'; The EVENT pin is active high. The “active” state of the pin will be logical '1'. Bit 0 – EVENT_MODE; Controls the behavior of the EVENT pin. The EVENT pin may function in either comparator or interrupt mode.If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. '0'; The EVENT pin will function in comparator mode. '1'; The EVENT pin will function in interrupt mode. Temperature Register Value Definitions Temperatures in the High Limit Register, Low Limit Register, TCRIT Register, and Temperature Data Register are expressed in two 's complement format. Bits B 12 through B2 for each of these registers are defined for all device resolutions as defined in the TRES field of the Capabilities Register, hence a 0.25°C minimum granularity is supported in all registers. Examples of valid settings and interpretation of temperature register bits: The TRES field of the Capabiliti es Register optionally defines higher resoluti on devices. For compatibility and simplicity, thi s additional resolution affects only the Temperature Data Register but none of the Limit Registers. When higher resolution devices generate status or EVENT changes, only bits B12 through B2 are used in the comparis on; however, all 11 bits (TRES[1-0] = 10) or all 12 bits (TRES[1-0] = 11) are visib le in reads from the Temperature Data Register. When a lower resolution device is indicated in the Capabilities Register (TRES[1-0] = 00), the finest resolution supported is 0 .5°C. When this is detected, bit 2 of all Limit Registers should be programmed to 0 to assure correct operation of the temperature comparators. High Limit Register The temperature limit registers (High, Low, and TCRIT) define the temperatures to be used by various on-chip comparators to det ermine device temperature status and thermal EVENTs. For future compatibility, unused bits “-” must be programmed as 0. High Limit Register The High Limit Register holds the High Limit for the nominal operating window. When the temperature rises above the High Limit, or drops below or equal to the High Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register table), then this register becomes read-only. Temperature Register Coding Examples B15~B0 (binary) Value Units xxx0 0000 0010 11xx +2.75 °C xxx0 0000 0001 00xx +1.00 °C xxx0 0000 0000 01xx +0.25 °C xxx0 0000 0000 00xx 0 °C xxx1 1111 1111 11xx -0.25 °C xxx1 1111 1111 00xx -1.00 °C xxx1 1111 1101 01xx -2.75 °C ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B 11/B3 B10/B2 B9/B1 B8/B0 Default

02 R/W

– – – Sign 128 64 32 16 0000 8 4 2 1 0.5 0.25 – –

27 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Low Limit Register Low Limit Register The Low Limit Register holds the lower limit for the nominal operating window. When the temperature drops below the Low Limit or rises up to meet or exceed the Low Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is se t as shown in the Configuration Register, then this register becomes read-only. TCRIT Limit Register TCRIT Limit Register The TCRIT Limit Register holds the TCRIT Limi t. If the temperature exceeds the limit, the EVENT pin will be asserted. It will remain asserted until the temperature drops below or equal to the limit minus hysteresis. If the TCRIT_LOCK bi t is set as shown in the Configuration Register table, then this register becomes read-only. Temperature Data Register Temperature Data Register * Resolution defined based on value of TRES field of the Capabilities Register. Unused/unsupported bits will read as 0. The Temperature Data Register holds the 10- bit + sign data for the internal temperature measurement as well as the status bits indicating which error conditions, if any, are active. The encoding of bits B12 through B0 is the same as for the temperature limit registers. Bit 15 – TCRIT; When set, the temperature is above the TCRIT Limi t. This bit will remain set so long as the temperature is abov e TCRIT and will automatically clear once the temperature has dropped below the limit minus the hysteresis. Bit 14 – HIGH; When set, the temperature is above the High Limit. This bit will remain set so long as the temperature is above the HIGH limit. Once set, it will only be cleared when the temperature drops below or equal to the HIGH Limit minus the hysteresis. Bit 13 – LOW; When set, the temperature is bel ow the Low Limit. This bit will remain se t so long as the temperature is below th e Low Limit minus the hysteresis. Once set, it will only be cleared when the temperature meets or exceeds the Low Limit. ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B 11/B3 B10/B2 B9/B1 B8/B0 Default

03 R/W

– – – Sign 128 64 32 16 0000 8 4 2 1 0.5 0.25 – – ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B 11/B3 B10/B2 B9/B1 B8/B0 Default

04 R/W

– – – Sign 128 64 32 16 0000 8 4 2 1 0.5 0.25 – – ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B 11/B3 B10/B2 B9/B1 B8/B0 Default 05 R TCRIT HIGH LOW Sign 128 64 32 16 N/A (0000) 8 4 2 1 0.5 0.25* 0.125* 0.0625*

28 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Manufacturer ID Register Manufacturer ID Register The Manufacturer ID Register holds the PCI SIG number assigned to the specific manufacturer. Device ID/Revision Register Device ID/Revision Register The upper byte of the Device ID / Revision Register stores a unique number indicating the TSE2004GB2B0 from other devices. The lower byte holds the revision value. Resolution Register This register allows the user to change t he resolution of the temperature sensor. The POR default resolution is 0.0625°C. The r esolution imple- mented via this register is also reflected in the capability register. Resolution Register Legend: Resolution bits 4-3 TRES[4:3] 00 = LSB = 0.5°C (register value = 0007) 01 = LSB = 0.25°C (register value = 000F) 10 = LSB = 0.125°C (register value = 0017) 11 = LSB = 0.0625°C (register value = 001F) ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B 11/B3 B10/B2 B9/B1 B8/B0 Default

06 R/W

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

07 R/W

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default Value 0 8 h R / W 00000000 0 0 1 8 0 0 0 TRES[1] TRES[0] 0 0 0

29 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Use in a Memory Module In the Dual Inline Memory Module (DIMM) appl ication, the TSE2004GB2B0 is soldered dire ctly onto the printed circuit module. The three Select Address inputs (SA0, SA1, SA2) must be connected to V SSSPD or VDDSPD directly (that is without using a pul l-up or pull-down re sistor) through the DIMM socket (as shown in the Unique Addressing table). Pull-up resistors needed fo r normal behavior are connected to the I 2C Bus signals on the mother-board Unique Addressing of SPDs in DIMM Applications Note: 0 = VSSSPD, 1 = VDDSPD. The Event pin is expected to be used in a wi re-OR configuration with a pull-up resistor to VDDSPD on the motherboard. In this c onfiguration, EVENT should be programmed for the active low mode. Also note that comparator mode or TCRIT-only mode for EVENT on a wire-OR bus will show the combined results of all devices wired to the EVENT signal. In DIMM applications, maximum external pul l-up resistors on signals are s pecified based on the figure below. “ Maximum RL Value Versus Bus Capaitance (CBUS) for an I2C Bus”. Line capacitance limitations should be calculated using this assumption. DIMM Position SA2 SA1 SA0 00 0 0 10 0 1 20 1 0 30 1 1 41 0 0 51 0 1 61 1 0 71 1 1

30 of 31 September 16, 2014 *Notice: The information in this document is subject to change without notice Programming the TSE2004GB2B0 The situations in which the TSE2004GB2B0 is programmed can be considered under two headings:

• When the DIMM is isolated (not inserted on the PCB motherboard)
• When the DIMM is inserted on the PCB motherboard DIMM Isolated With specific programming equipment, it is possible to define the TSE2004GB2B0 conten t, using Byte and Page Write instructions, and its write-protection using the SWPn and CWP instructions. To issu e the SWPn and CWP instructions, the DIMM must be inserted in the applica- tion-specific slot where the SA0 signal can be driven to VHV during the whole instruction. This programming step is mainly intended for use by DIMM makers, whose end application manufacturers will want to clear this write-protection wi th the CWP on their own specific program ming equipment, to modify the protected bytes, and finally to set the write-protection with the SWPn instruction. In DIMM Isolation usage, the Read Protec tion Status (RPSn), Set EE Page Address (SPAn), and Read EE Page Address (RPA) commands are fully supported.

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Ordering Information

Example: TSE2004GB2B0 NCG8 XXXXX XX X Rev.Voltage Shipping

8 Tape and Reel

X Device Type 2004G Temperature Sensor with EEPROM X Temp B Temperature Accuracy Grade Carrier TSE Range 2 = (2.2V to 3.6V) XXX Package NCG - Green TDFN