TSD12C-Q1 TI | Alldatasheet
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Technical content
TSDxxC-Q1 Bidirectional TVS Diodes in SOD-323 Package for Automotive
Applications
1 Features
- ISO 10605 (330pF, 330 Ohm) ESD protection: – ±30kV contact discharge (±27kV for TSD36C- Q1) – ±30kV air gap discharge
- IEC 61000-4-5 surge protection:
- Low IO capacitance < 7pF (typical)
- Ultra low leakage current: 10nA (maximum)
- Industrial temperature range: –55°C to +150°C
- Industry standard SOD-323 leaded package (2.65mm × 1.3mm)
2 Applications
- I/O Protection
- Power Line Protection
- USB VBUS
- Body Electronics & Lighting
- Hybrid, Electric, & Powertrain Systems
3 Description
The TSDxxC-Q1 are a family of bidirectional TVS protection diodes designed for clamping harmful transients such as ESD and surge in automotive applications. The TSDxxC-Q1 devices are rated to dissipate ESD strikes up to ±30kV (contact and air gap discharge) which exceeds the maximum level specified in the IEC 61000-4-2 international standard (Level 4). Combining the robust clamping performance and low capacitance of these devices, TSDxxC-Q1 are excellent TVS diodes to protect both data lines and power lines in many different applications. The TSDxxC-Q1 family is offered in the industry standard, leaded SOD-323 package to enable easy solderability.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TSDxxC-Q1 DYF (SOD-323, 2) 2.65mm × 1.3mm (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. IO GND Functional Block Diagram TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
10 Mechanical, Packaging, and Orderable
TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
4 Pin Configuration and Functions
Figure 4-1. DYF Package, 2-Pin SOD-323 (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 IO I/O Protected Channel. If used as IO, connect pin 2 to ground 2 IO I/O Protected Channel. If used as IO, connect pin 1 to ground (1) I = input, O = output www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) Parameter DEVICE MIN MAX UNIT PPP IEC 61000-4-5 (tp 8/20µs) Peak Pulse Power at 25°C TSD12C-Q1 390 W TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1 400 W IPP IEC 61000-4-5 (tp 8/20µs) Peak Pulse Current at 25°C TSD12C-Q1 15 A TSD15C-Q1 12 A TSD18C-Q1 TSD24C-Q1 9 A TSD36C-Q1 6.5 A TA Ambient Operating Temperature -55 150 °C Tstg Storage Temperature -65 155 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime.
5.2 ESD Ratings - AEC Specifications
Parameter Test Conditions VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q101-001(1) ±2500 VCharged device model (CDM), per AEC Q101-005(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 ESD Ratings—IEC Specification
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±30000 V IEC 61000-4-2 air-gap discharge ±30000 TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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5.4 ESD Ratings - ISO Specifications
Parameter Test Conditions Device VALUE UNIT V(ESD) ISO 10605 Electrostatic Discharge Contact discharge, all pins C = 150 pF; R = 330 Ω TSD12C-Q1 ±30000 V TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1 C = 330 pF; R = 330 Ω TSD12C-Q1 ±30000 V TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1 ±27000 V Air-gap discharge, all pins C = 150 pF; R = 330 Ω TSD12C-Q1 ±30000 V TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1 C = 330 pF; R = 330 Ω TSD12C-Q1 ±30000 V TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Operating free-air temperature -55 150 °C
5.6 Thermal Information
Q1 / TSD18C-Q1 TSD24C-Q1 / TSD36C-Q1 UNITDYF (SOD-323) DYF (SOD-323)
2 PINS 2 PINS
RθJA Junction-to-ambient thermal resistance 683.8 686.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 264.2 267.0 °C/W RθJB Junction-to-board thermal resistance 559.0 560.5 °C/W ΨJT Junction-to-top characterization parameter 89.9 91.4 °C/W ΨJB Junction-to-board characterization parameter 544.8 546.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5.7 Electrical Characteristics - TSD12C-Q1
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <10 nA, across operating temperature range 12 V VBRR Breakdown voltage IIO = 10 mA, IO to GND and GND to IO 13.2 15.6 19 V ILEAK Reverse leakage current VIO = 12 V, IO to GND or GND to IO 5 10 nA VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 1 A, IO to GND or GND to IO 18.5 V IPP = 5 A, IO to GND or GND to IO 21 V IPP = 15 A, IO to GND or GND to IO 26 V TLP clamping voltage, tp = 100 ns IPP = 16 A, IO to GND or GND to IO 19.4 V RDYN Dynamic resistance(3) IO to GND 0.15 Ω GND to IO CL Line capacitance VIO = 0 V; ƒ = 1 MHz, IO to GND 6.5 8 pF (1) Typical parameters are measured at 25℃ (2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5 (3) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5.8 Electrical Characteristics - TSD15C-Q1
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <10 nA, across operating temperature range 15 V VBRR Breakdown voltage IIO = 10 mA, IO to GND and GND to IO 19 22 25 V ILEAK Reverse leakage current VIO = 15 V, IO to GND or GND to IO 5 10 nA VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 1 A, IO to GND or GND to IO 25.6 V IPP = 5 A, IO to GND or GND to IO 28 V IPP = 12 A, IO to GND or GND to IO 33 V TLP clamping voltage, tp = 100 ns IPP = 16 A, IO to GND or GND to IO 25 V RDYN Dynamic resistance(3) IO to GND 0.2 Ω GND to IO CL Line capacitance VIO = 0 V; ƒ = 1 MHz, IO to GND 6.7 9 pF (1) Typical parameters are measured at 25℃ (2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5 (3) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5.9 Electrical Characteristics - TSD18C-Q1
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <10 nA, across operating temperature range 18 V VBRR Breakdown voltage IIO = 10 mA, IO to GND and GND to IO 19 22 25 V ILEAK Reverse leakage current VIO = 18 V, IO to GND or GND to IO 5 10 nA VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 1 A, IO to GND or GND to IO 25.6 V IPP = 5 A, IO to GND or GND to IO 28 V IPP = 12 A, IO to GND or GND to IO 33 V TLP clamping voltage, tp = 100 ns IPP = 16 A, IO to GND or GND to IO 25 V RDYN Dynamic resistance(3) IO to GND 0.2 Ω GND to IO CL Line capacitance VIO = 0 V; ƒ = 1 MHz, IO to GND 6.7 9 pF (1) Typical parameters are measured at 25℃ (2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5 (3) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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5.10 Electrical Characteristics - TSD24C-Q1
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <10 nA, across operating temperature range 24 V VBR Breakdown voltage IIO = 10 mA, IO to GND and GND to IO 25.5 30.5 35.5 V ILEAK Reverse leakage current VIO = 24 V, IO to GND or GND to IO 5 10 nA VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 1 A, IO to GND or GND to IO 34 V IPP = 5 A, IO to GND or GND to IO 43 V IPP = 9 A, IO to GND or GND to IO 50 V TLP clamping voltage, tp = 100 ns IPP = 16 A, IO to GND or GND to IO 36 V RDYN Dynamic resistance(3) IO to GND 0.35 Ω GND to IO CL Line capacitance VIO = 0 V; ƒ = 1 MHz, IO to GND 4.3 6 pF (1) Typical parameters are measured at 25℃ (2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5 (3) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5.11 Electrical Characteristics - TSD36C-Q1
At TA=25℃ (unless otherwise noted) (1) PARAMETER TEST CONDITION MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO <50 nA, across operating temperature range 36 V VBR Breakdown voltage IIO = 10 mA, I/O to GND and GND to I/O 37.8 41.2 44.2 V ILEAK Reverse leakage current VIO = 36 V, IO to GND or GND to IO 5 10 nA VCLAMP Surge clamping voltage, tp = 8/20 µs (2) IPP = 1 A, IO to GND or GND to IO 47 V IPP = 5 A, IO to GND or GND to IO 64 V IPP = 6.5 A, IO to GND or GND to IO 71 V TLP clamping voltage, tp = 100 ns IPP = 16 A, IO to GND or GND to IO 56 V RDYN Dynamic resistance (3) IO to GND 0.6 Ω GND to IO CL Line capacitance VIO = 0 V; ƒ = 1 MHz, IO to GND 4.3 6 pF (1) Typical parameters are measured at 25℃ (2) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5 (3) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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5.12 Typical Characteristics
V o l t a g e ( V ) Current (A) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 - 4 1 2 1 6 2 0 2 4 2 8 Figure 5-1. Positive TLP Curve - TSD12C-Q1 V o l t a g e ( V ) Current (A) 0 3 6 9 1 2 1 5 1 8 2 1 2 4 2 7 3 0 - 4 1 2 1 6 2 0 2 4 2 8 Figure 5-2. Positive TLP Curve - TSD15C-Q1 V o l t a g e ( V ) Current (A) 0 3 6 9 1 2 1 5 1 8 2 1 2 4 2 7 3 0 - 4 1 2 1 6 2 0 2 4 2 8 Figure 5-3. Positive TLP Curve - TSD18C-Q1 V o l t a g e ( V ) Current (A) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 - 4 1 2 1 6 2 0 2 4 2 8 Figure 5-4. Positive TLP Curve - TSD24C-Q1 V o l t a g e ( V ) Current (A) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 - 4 1 2 1 6 2 0 2 4 2 8 Figure 5-5. Positive TLP Curve - TSD36C-Q1 B i a s V o l t a g e ( V ) Capacitance (pF) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 2 . 5 3 . 5 4 . 5 5 . 5 T S D 1 2 C - Q 1 T S D 1 5 C - Q 1 / 1 8 C - Q 1 T S D 2 4 C - Q 1 T S D 3 6 C - Q 1 Figure 5-6. Capacitance vs Bias Voltage www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
5.12 Typical Characteristics (continued)
T e m p e r a t u r e ( C ) Leakage Current (nA) - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 1 1 T S D 1 2 C - Q 1 T S D 1 5 C - Q 1 / 1 8 C - Q 1 T S D 2 4 C - Q 1 T S D 3 6 C - Q 1 Figure 5-7. Leakage Current vs Temperature A m b i e n t T e m p e r a t u r e ( C ) Peak Pulse Power (PPP) or Current (IPP) and Derating in Percentage (%) 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5 2 0 4 0 6 0 8 0 1 0 0 1 2 0 Figure 5-8. Peak Pulse Power Derating Curve t d - P u l s e W i d t h ( s ) PPP- Peak Pulse Power (kW) 0 . 1 0 . 2 0 . 5 1 2 3 4 5 7 1 0 2 0 3 0 5 0 1 0 0 2 0 0 5 0 0 1 0 0 0 0 . 0 50 . 0 5 0 . 0 7 0 . 1 0 . 2 0 . 3 0 . 5 0 . 7 1 0 Figure 5-9. Pulse Power Rating Curve TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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6 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
7 Application Information
The TSDxxC-Q1 are TVS diodes that provide a path to ground for dissipating transient voltage spikes (such as ESD or surge) on signal lines and power lines. Connect the device in parallel to the down stream circuitry for protection. As the current from the transient passes through the TVS, only a small voltage drop is present across the diode. The small voltage drop is presented to the protected IC. The low R DYN of the triggered TVS holds this voltage (VCLAMP) to a safe level for the protected IC. For more information on how to properly use this device, refer to the ESD Packaging and Layout Guide. TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 www.ti.com
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation, see the following:
- Texas Instruments, ESD Packaging and Layout Guide application report
- Texas Instruments, ESD Layout Guide application report
- Texas Instruments, Generic ESD Evaluation Module user's guide
- Texas Instruments, Reading and Understanding an ESD Protection Data Sheet user's guide
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
October 2024 * Initial Release
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation www.ti.com TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1, TSD36C-Q1 SLVSHX0 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TSD12C-Q1 TSD15C-Q1 TSD18C-Q1 TSD24C-Q1 TSD36C-Q1
www.ti.com 30-Oct-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TSD12CDYFRQ1 ACTIVE SOT DYF 2 3000 RoHS & Green SN Level-3-260C-168 HR -55 to 150 3JNF Samples TSD15CDYFRQ1 ACTIVE SOT DYF 2 3000 RoHS & Green SN Level-3-260C-168 HR -55 to 150 3MMF Samples TSD18CDYFRQ1 ACTIVE SOT DYF 2 3000 RoHS & Green SN Level-3-260C-168 HR -55 to 150 3JPF Samples TSD24CDYFRQ1 ACTIVE SOT DYF 2 3000 RoHS & Green SN Level-3-260C-168 HR -55 to 150 3GZF Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1
www.ti.com 30-Oct-2024 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TSD12C-Q1, TSD15C-Q1, TSD18C-Q1, TSD24C-Q1 :
- Catalog : TSD12C , TSD15C , TSD18C , TSD24C NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSD12CDYFRQ1 SOT DYF 2 3000 210.0 200.0 42.0 TSD15CDYFRQ1 SOT DYF 2 3000 210.0 200.0 42.0 TSD18CDYFRQ1 SOT DYF 2 3000 210.0 200.0 42.0 TSD24CDYFRQ1 SOT DYF 2 3000 210.0 200.0 42.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE 0.15
0.08 TYP
0.2 2.75 2.55
1 MAX
0.1
0.0 TYP
2X 0.35 0.25 1.8 1.6 1.4 1.2 0.40
0.25 TYP
(0.475) (0.85) SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 (-) 2 (+) PIN 1 ID GAGE PLANE SCALE 6.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
2X (0.9) 2X (0.5) (2.6) (R0.05) TYP 4228484/A 02/2022 SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR NOTES: (continued) 3. Publication IPC-7351 may have alternate designs. 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:25X PKG 1 2 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X (0.9) 2X (0.5) (R0.05) TYP SOT(SOD-323) - 1 mm max heightDYF0002A SMALL OUTLINE TRANSISTOR 4228484/A 02/2022 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 6. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:25X PKG PKG 1 2
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